struct drm_file *filp);
 
 /* VRAM scratch page for HDP bug, default vram page */
-struct amdgpu_vram_scratch {
+struct amdgpu_mem_scratch {
        struct amdgpu_bo                *robj;
        volatile uint32_t               *ptr;
        u64                             gpu_addr;
 
        /* memory management */
        struct amdgpu_mman              mman;
-       struct amdgpu_vram_scratch      vram_scratch;
+       struct amdgpu_mem_scratch       mem_scratch;
        struct amdgpu_wb                wb;
        atomic64_t                      num_bytes_moved;
        atomic64_t                      num_evictions;
 
 }
 
 /**
- * amdgpu_device_vram_scratch_init - allocate the VRAM scratch page
+ * amdgpu_device_mem_scratch_init - allocate the VRAM scratch page
  *
  * @adev: amdgpu_device pointer
  *
  * Allocates a scratch page of VRAM for use by various things in the
  * driver.
  */
-static int amdgpu_device_vram_scratch_init(struct amdgpu_device *adev)
+static int amdgpu_device_mem_scratch_init(struct amdgpu_device *adev)
 {
-       return amdgpu_bo_create_kernel(adev, AMDGPU_GPU_PAGE_SIZE,
-                                      PAGE_SIZE,
-                                      AMDGPU_GEM_DOMAIN_VRAM,
-                                      &adev->vram_scratch.robj,
-                                      &adev->vram_scratch.gpu_addr,
-                                      (void **)&adev->vram_scratch.ptr);
+       return amdgpu_bo_create_kernel(adev, AMDGPU_GPU_PAGE_SIZE, PAGE_SIZE,
+                                      AMDGPU_GEM_DOMAIN_VRAM |
+                                      AMDGPU_GEM_DOMAIN_GTT,
+                                      &adev->mem_scratch.robj,
+                                      &adev->mem_scratch.gpu_addr,
+                                      (void **)&adev->mem_scratch.ptr);
 }
 
 /**
- * amdgpu_device_vram_scratch_fini - Free the VRAM scratch page
+ * amdgpu_device_mem_scratch_fini - Free the VRAM scratch page
  *
  * @adev: amdgpu_device pointer
  *
  * Frees the VRAM scratch page.
  */
-static void amdgpu_device_vram_scratch_fini(struct amdgpu_device *adev)
+static void amdgpu_device_mem_scratch_fini(struct amdgpu_device *adev)
 {
-       amdgpu_bo_free_kernel(&adev->vram_scratch.robj, NULL, NULL);
+       amdgpu_bo_free_kernel(&adev->mem_scratch.robj, NULL, NULL);
 }
 
 /**
                        if (amdgpu_sriov_vf(adev))
                                amdgpu_virt_exchange_data(adev);
 
-                       r = amdgpu_device_vram_scratch_init(adev);
+                       r = amdgpu_device_mem_scratch_init(adev);
                        if (r) {
-                               DRM_ERROR("amdgpu_vram_scratch_init failed %d\n", r);
+                               DRM_ERROR("amdgpu_mem_scratch_init failed %d\n", r);
                                goto init_failed;
                        }
                        r = adev->ip_blocks[i].version->funcs->hw_init((void *)adev);
                        amdgpu_ucode_free_bo(adev);
                        amdgpu_free_static_csa(&adev->virt.csa_obj);
                        amdgpu_device_wb_fini(adev);
-                       amdgpu_device_vram_scratch_fini(adev);
+                       amdgpu_device_mem_scratch_fini(adev);
                        amdgpu_ib_pool_fini(adev);
                }
 
 
                                max(adev->gmc.fb_end, adev->gmc.agp_end) >> 18);
 
                /* Set default page address. */
-               value = amdgpu_gmc_vram_mc2pa(adev, adev->vram_scratch.gpu_addr);
+               value = amdgpu_gmc_vram_mc2pa(adev, adev->mem_scratch.gpu_addr);
                WREG32_SOC15(GC, 0, mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB,
                             (u32)(value >> 12));
                WREG32_SOC15(GC, 0, mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB,
 
                             max(adev->gmc.fb_end, adev->gmc.agp_end) >> 18);
 
                /* Set default page address. */
-               value = amdgpu_gmc_vram_mc2pa(adev, adev->vram_scratch.gpu_addr);
+               value = amdgpu_gmc_vram_mc2pa(adev, adev->mem_scratch.gpu_addr);
                WREG32_SOC15(GC, 0, mmGCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB,
                             (u32)(value >> 12));
                WREG32_SOC15(GC, 0, mmGCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB,
 
                     max(adev->gmc.fb_end, adev->gmc.agp_end) >> 18);
 
        /* Set default page address. */
-       value = amdgpu_gmc_vram_mc2pa(adev, adev->vram_scratch.gpu_addr);
+       value = amdgpu_gmc_vram_mc2pa(adev, adev->mem_scratch.gpu_addr);
        WREG32_SOC15(GC, 0, mmGCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB,
                     (u32)(value >> 12));
        WREG32_SOC15(GC, 0, mmGCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB,
 
                     adev->gmc.vram_end >> 18);
 
        /* Set default page address. */
-       value = adev->vram_scratch.gpu_addr - adev->gmc.vram_start
+       value = adev->mem_scratch.gpu_addr - adev->gmc.vram_start
                + adev->vm_manager.vram_base_offset;
        WREG32_SOC15(GC, 0, regGCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB,
                     (u32)(value >> 12));
 
                     adev->gmc.vram_end >> 18);
 
        /* Set default page address. */
-       value = adev->vram_scratch.gpu_addr - adev->gmc.vram_start
+       value = adev->mem_scratch.gpu_addr - adev->gmc.vram_start
                + adev->vm_manager.vram_base_offset;
        WREG32_SOC15(GC, 0, regGCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB,
                     (u32)(value >> 12));
 
        WREG32(mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR,
               adev->gmc.vram_end >> 12);
        WREG32(mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR,
-              adev->vram_scratch.gpu_addr >> 12);
+              adev->mem_scratch.gpu_addr >> 12);
        WREG32(mmMC_VM_AGP_BASE, 0);
        WREG32(mmMC_VM_AGP_TOP, 0x0FFFFFFF);
        WREG32(mmMC_VM_AGP_BOT, 0x0FFFFFFF);
 
        WREG32(mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR,
               adev->gmc.vram_end >> 12);
        WREG32(mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR,
-              adev->vram_scratch.gpu_addr >> 12);
+              adev->mem_scratch.gpu_addr >> 12);
        WREG32(mmMC_VM_AGP_BASE, 0);
        WREG32(mmMC_VM_AGP_TOP, 0x0FFFFFFF);
        WREG32(mmMC_VM_AGP_BOT, 0x0FFFFFFF);
 
        WREG32(mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR,
               adev->gmc.vram_end >> 12);
        WREG32(mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR,
-              adev->vram_scratch.gpu_addr >> 12);
+              adev->mem_scratch.gpu_addr >> 12);
 
        if (amdgpu_sriov_vf(adev)) {
                tmp = ((adev->gmc.vram_end >> 24) & 0xFFFF) << 16;
 
                return;
 
        /* Set default page address. */
-       value = amdgpu_gmc_vram_mc2pa(adev, adev->vram_scratch.gpu_addr);
+       value = amdgpu_gmc_vram_mc2pa(adev, adev->mem_scratch.gpu_addr);
        WREG32_SOC15(MMHUB, 0, mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB,
                     (u32)(value >> 12));
        WREG32_SOC15(MMHUB, 0, mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB,
 
        }
 
        /* Set default page address. */
-       value = amdgpu_gmc_vram_mc2pa(adev, adev->vram_scratch.gpu_addr);
+       value = amdgpu_gmc_vram_mc2pa(adev, adev->mem_scratch.gpu_addr);
        WREG32_SOC15(MMHUB, 0, regMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB,
                     (u32)(value >> 12));
        WREG32_SOC15(MMHUB, 0, regMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB,
 
        }
 
        /* Set default page address. */
-       value = amdgpu_gmc_vram_mc2pa(adev, adev->vram_scratch.gpu_addr);
+       value = amdgpu_gmc_vram_mc2pa(adev, adev->mem_scratch.gpu_addr);
        WREG32_SOC15(MMHUB, 0, mmMMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB,
                     (u32)(value >> 12));
        WREG32_SOC15(MMHUB, 0, mmMMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB,
 
                     max(adev->gmc.fb_end, adev->gmc.agp_end) >> 18);
 
        /* Set default page address. */
-       value = amdgpu_gmc_vram_mc2pa(adev, adev->vram_scratch.gpu_addr);
+       value = amdgpu_gmc_vram_mc2pa(adev, adev->mem_scratch.gpu_addr);
        WREG32_SOC15(MMHUB, 0, mmMMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB,
                     (u32)(value >> 12));
        WREG32_SOC15(MMHUB, 0, mmMMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB,
 
        }
 
        /* Set default page address. */
-       value = adev->vram_scratch.gpu_addr - adev->gmc.vram_start +
+       value = adev->mem_scratch.gpu_addr - adev->gmc.vram_start +
                adev->vm_manager.vram_base_offset;
        WREG32_SOC15(MMHUB, 0, regMMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB,
                     (u32)(value >> 12));
 
                     adev->gmc.vram_end >> 18);
 
        /* Set default page address. */
-       value = adev->vram_scratch.gpu_addr - adev->gmc.vram_start +
+       value = adev->mem_scratch.gpu_addr - adev->gmc.vram_start +
                adev->vm_manager.vram_base_offset;
        WREG32_SOC15(MMHUB, 0, regMMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB,
                     (u32)(value >> 12));
 
        }
 
        /* Set default page address. */
-       value = adev->vram_scratch.gpu_addr - adev->gmc.vram_start +
+       value = adev->mem_scratch.gpu_addr - adev->gmc.vram_start +
                adev->vm_manager.vram_base_offset;
        WREG32_SOC15(MMHUB, 0, regMMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB,
                     (u32)(value >> 12));
 
                        max(adev->gmc.fb_end, adev->gmc.agp_end) >> 18);
 
                /* Set default page address. */
-               value = amdgpu_gmc_vram_mc2pa(adev, adev->vram_scratch.gpu_addr);
+               value = amdgpu_gmc_vram_mc2pa(adev, adev->mem_scratch.gpu_addr);
                WREG32_SOC15_OFFSET(
                        MMHUB, 0,
                        mmVMSHAREDPF0_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB,