dma_addr_t              rb_dma_addr; /* only used when use_bus_addr = true */
 };
 
+#define AMDGPU_IH_SRC_DATA_MAX_SIZE_DW 4
+
 struct amdgpu_iv_entry {
        unsigned client_id;
        unsigned src_id;
-       unsigned src_data;
+       unsigned src_data[AMDGPU_IH_SRC_DATA_MAX_SIZE_DW];
        unsigned ring_id;
        unsigned vm_id;
        unsigned vm_id_src;
 
 
        entry->client_id = AMDGPU_IH_CLIENTID_LEGACY;
        entry->src_id = dw[0] & 0xff;
-       entry->src_data = dw[1] & 0xfffffff;
+       entry->src_data[0] = dw[1] & 0xfffffff;
        entry->ring_id = dw[2] & 0xff;
        entry->vm_id = (dw[2] >> 8) & 0xff;
        entry->pas_id = (dw[2] >> 16) & 0xffff;
 
 
        entry->client_id = AMDGPU_IH_CLIENTID_LEGACY;
        entry->src_id = dw[0] & 0xff;
-       entry->src_data = dw[1] & 0xfffffff;
+       entry->src_data[0] = dw[1] & 0xfffffff;
        entry->ring_id = dw[2] & 0xff;
        entry->vm_id = (dw[2] >> 8) & 0xff;
        entry->pas_id = (dw[2] >> 16) & 0xffff;
 
        uint32_t disp_int = RREG32(interrupt_status_offsets[crtc].reg);
        unsigned irq_type = amdgpu_crtc_idx_to_irq_type(adev, crtc);
 
-       switch (entry->src_data) {
+       switch (entry->src_data[0]) {
        case 0: /* vblank */
                if (disp_int & interrupt_status_offsets[crtc].vblank)
                        dce_v10_0_crtc_vblank_int_ack(adev, crtc);
 
                break;
        default:
-               DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data);
+               DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data[0]);
                break;
        }
 
        uint32_t disp_int, mask;
        unsigned hpd;
 
-       if (entry->src_data >= adev->mode_info.num_hpd) {
-               DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data);
+       if (entry->src_data[0] >= adev->mode_info.num_hpd) {
+               DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data[0]);
                return 0;
        }
 
-       hpd = entry->src_data;
+       hpd = entry->src_data[0];
        disp_int = RREG32(interrupt_status_offsets[hpd].reg);
        mask = interrupt_status_offsets[hpd].hpd;
 
 
        uint32_t disp_int = RREG32(interrupt_status_offsets[crtc].reg);
        unsigned irq_type = amdgpu_crtc_idx_to_irq_type(adev, crtc);
 
-       switch (entry->src_data) {
+       switch (entry->src_data[0]) {
        case 0: /* vblank */
                if (disp_int & interrupt_status_offsets[crtc].vblank)
                        dce_v11_0_crtc_vblank_int_ack(adev, crtc);
 
                break;
        default:
-               DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data);
+               DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data[0]);
                break;
        }
 
        uint32_t disp_int, mask;
        unsigned hpd;
 
-       if (entry->src_data >= adev->mode_info.num_hpd) {
-               DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data);
+       if (entry->src_data[0] >= adev->mode_info.num_hpd) {
+               DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data[0]);
                return 0;
        }
 
-       hpd = entry->src_data;
+       hpd = entry->src_data[0];
        disp_int = RREG32(interrupt_status_offsets[hpd].reg);
        mask = interrupt_status_offsets[hpd].hpd;
 
 
        uint32_t disp_int = RREG32(interrupt_status_offsets[crtc].reg);
        unsigned irq_type = amdgpu_crtc_idx_to_irq_type(adev, crtc);
 
-       switch (entry->src_data) {
+       switch (entry->src_data[0]) {
        case 0: /* vblank */
                if (disp_int & interrupt_status_offsets[crtc].vblank)
                        WREG32(mmVBLANK_STATUS + crtc_offsets[crtc], VBLANK_ACK);
                DRM_DEBUG("IH: D%d vline\n", crtc + 1);
                break;
        default:
-               DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data);
+               DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data[0]);
                break;
        }
 
        uint32_t disp_int, mask, tmp;
        unsigned hpd;
 
-       if (entry->src_data >= adev->mode_info.num_hpd) {
-               DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data);
+       if (entry->src_data[0] >= adev->mode_info.num_hpd) {
+               DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data[0]);
                return 0;
        }
 
-       hpd = entry->src_data;
+       hpd = entry->src_data[0];
        disp_int = RREG32(interrupt_status_offsets[hpd].reg);
        mask = interrupt_status_offsets[hpd].hpd;
 
 
        uint32_t disp_int = RREG32(interrupt_status_offsets[crtc].reg);
        unsigned irq_type = amdgpu_crtc_idx_to_irq_type(adev, crtc);
 
-       switch (entry->src_data) {
+       switch (entry->src_data[0]) {
        case 0: /* vblank */
                if (disp_int & interrupt_status_offsets[crtc].vblank)
                        WREG32(mmLB_VBLANK_STATUS + crtc_offsets[crtc], LB_VBLANK_STATUS__VBLANK_ACK_MASK);
                DRM_DEBUG("IH: D%d vline\n", crtc + 1);
                break;
        default:
-               DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data);
+               DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data[0]);
                break;
        }
 
        uint32_t disp_int, mask, tmp;
        unsigned hpd;
 
-       if (entry->src_data >= adev->mode_info.num_hpd) {
-               DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data);
+       if (entry->src_data[0] >= adev->mode_info.num_hpd) {
+               DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data[0]);
                return 0;
        }
 
-       hpd = entry->src_data;
+       hpd = entry->src_data[0];
        disp_int = RREG32(interrupt_status_offsets[hpd].reg);
        mask = interrupt_status_offsets[hpd].hpd;
 
 
 
        if (printk_ratelimit()) {
                dev_err(adev->dev, "GPU fault detected: %d 0x%08x\n",
-                       entry->src_id, entry->src_data);
+                       entry->src_id, entry->src_data[0]);
                dev_err(adev->dev, "  VM_CONTEXT1_PROTECTION_FAULT_ADDR   0x%08X\n",
                        addr);
                dev_err(adev->dev, "  VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n",
 
 
        if (printk_ratelimit()) {
                dev_err(adev->dev, "GPU fault detected: %d 0x%08x\n",
-                       entry->src_id, entry->src_data);
+                       entry->src_id, entry->src_data[0]);
                dev_err(adev->dev, "  VM_CONTEXT1_PROTECTION_FAULT_ADDR   0x%08X\n",
                        addr);
                dev_err(adev->dev, "  VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n",
 
 
        if (amdgpu_sriov_vf(adev)) {
                dev_err(adev->dev, "GPU fault detected: %d 0x%08x\n",
-                       entry->src_id, entry->src_data);
+                       entry->src_id, entry->src_data[0]);
                dev_err(adev->dev, " Can't decode VM fault info here on SRIOV VF\n");
                return 0;
        }
 
        if (printk_ratelimit()) {
                dev_err(adev->dev, "GPU fault detected: %d 0x%08x\n",
-                       entry->src_id, entry->src_data);
+                       entry->src_id, entry->src_data[0]);
                dev_err(adev->dev, "  VM_CONTEXT1_PROTECTION_FAULT_ADDR   0x%08X\n",
                        addr);
                dev_err(adev->dev, "  VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n",
 
 
        entry->client_id = AMDGPU_IH_CLIENTID_LEGACY;
        entry->src_id = dw[0] & 0xff;
-       entry->src_data = dw[1] & 0xfffffff;
+       entry->src_data[0] = dw[1] & 0xfffffff;
        entry->ring_id = dw[2] & 0xff;
        entry->vm_id = (dw[2] >> 8) & 0xff;
        entry->pas_id = (dw[2] >> 16) & 0xffff;
 
 
        entry->client_id = AMDGPU_IH_CLIENTID_LEGACY;
        entry->src_id = dw[0] & 0xff;
-       entry->src_data = dw[1] & 0xfffffff;
+       entry->src_data[0] = dw[1] & 0xfffffff;
        entry->ring_id = dw[2] & 0xff;
        entry->vm_id = (dw[2] >> 8) & 0xff;
 
 
 
        entry->client_id = AMDGPU_IH_CLIENTID_LEGACY;
        entry->src_id = dw[0] & 0xff;
-       entry->src_data = dw[1] & 0xfffffff;
+       entry->src_data[0] = dw[1] & 0xfffffff;
        entry->ring_id = dw[2] & 0xff;
        entry->vm_id = (dw[2] >> 8) & 0xff;
        entry->pas_id = (dw[2] >> 16) & 0xffff;
 
                                      struct amdgpu_iv_entry *entry)
 {
        DRM_DEBUG("IH: VCE\n");
-       switch (entry->src_data) {
+       switch (entry->src_data[0]) {
        case 0:
        case 1:
-               amdgpu_fence_process(&adev->vce.ring[entry->src_data]);
+               amdgpu_fence_process(&adev->vce.ring[entry->src_data[0]]);
                break;
        default:
                DRM_ERROR("Unhandled interrupt: %d %d\n",
-                         entry->src_id, entry->src_data);
+                         entry->src_id, entry->src_data[0]);
                break;
        }
 
 
 
        WREG32_FIELD(VCE_SYS_INT_STATUS, VCE_SYS_INT_TRAP_INTERRUPT_INT, 1);
 
-       switch (entry->src_data) {
+       switch (entry->src_data[0]) {
        case 0:
        case 1:
        case 2:
-               amdgpu_fence_process(&adev->vce.ring[entry->src_data]);
+               amdgpu_fence_process(&adev->vce.ring[entry->src_data[0]]);
                break;
        default:
                DRM_ERROR("Unhandled interrupt: %d %d\n",
-                         entry->src_id, entry->src_data);
+                         entry->src_id, entry->src_data[0]);
                break;
        }