usb: dwc3: reference clock period configuration

Set reference clock period when it differs from dwc3 default hardware
set.

We could calculate clock period based on reference clock frequency. But
this information is not always available. This is the case of PCI bus
attached USB host. For that reason we use a custom property.

Tested (USB2 only) on IPQ6010 SoC based board with 24 MHz reference
clock while hardware default is 19.2 MHz.

[ baruch: rewrite commit message; drop GFLADJ code; remove 'quirk-' from
  property name; mention tested hardware ]

Acked-by: Felipe Balbi <balbi@kernel.org>
Signed-off-by: Balaji Prakash J <bjagadee@codeaurora.org>
Signed-off-by: Baruch Siach <baruch@tkos.co.il>
Nacked-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/9f399bdf1ff752e31ab7497e3d5ce19bbb3ff247.1630389452.git.baruch@tkos.co.il
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
index 01866dcb953bac535c6eda6b03d2f899c1044292..ced366ff839becb8fce2f550cacb5d0da8d0a84f 100644 (file)
--- a/drivers/usb/dwc3/core.c
+++ b/drivers/usb/dwc3/core.c
@@ -26,6 +26,7 @@
 #include <linux/acpi.h>
 #include <linux/pinctrl/consumer.h>
 #include <linux/reset.h>
+#include <linux/bitfield.h>
 
 #include <linux/usb/ch9.h>
 #include <linux/usb/gadget.h>
@@ -351,6 +352,29 @@ static void dwc3_frame_length_adjustment(struct dwc3 *dwc)
        }
 }
 
+/**
+ * dwc3_ref_clk_period - Reference clock period configuration
+ *             Default reference clock period depends on hardware
+ *             configuration. For systems with reference clock that differs
+ *             from the default, this will set clock period in DWC3_GUCTL
+ *             register.
+ * @dwc: Pointer to our controller context structure
+ * @ref_clk_per: reference clock period in ns
+ */
+static void dwc3_ref_clk_period(struct dwc3 *dwc)
+{
+       u32 reg;
+
+       if (dwc->ref_clk_per == 0)
+               return;
+
+       reg = dwc3_readl(dwc->regs, DWC3_GUCTL);
+       reg &= ~DWC3_GUCTL_REFCLKPER_MASK;
+       reg |=  FIELD_PREP(DWC3_GUCTL_REFCLKPER_MASK, dwc->ref_clk_per);
+       dwc3_writel(dwc->regs, DWC3_GUCTL, reg);
+}
+
+
 /**
  * dwc3_free_one_event_buffer - Frees one event buffer
  * @dwc: Pointer to our controller context structure
@@ -1011,6 +1035,9 @@ static int dwc3_core_init(struct dwc3 *dwc)
        /* Adjust Frame Length */
        dwc3_frame_length_adjustment(dwc);
 
+       /* Adjust Reference Clock Period */
+       dwc3_ref_clk_period(dwc);
+
        dwc3_set_incr_burst_type(dwc);
 
        usb_phy_set_suspend(dwc->usb2_phy, 0);
@@ -1393,6 +1420,8 @@ static void dwc3_get_properties(struct dwc3 *dwc)
                                    &dwc->hsphy_interface);
        device_property_read_u32(dev, "snps,quirk-frame-length-adjustment",
                                 &dwc->fladj);
+       device_property_read_u32(dev, "snps,ref-clock-period-ns",
+                                &dwc->ref_clk_per);
 
        dwc->dis_metastability_quirk = device_property_read_bool(dev,
                                "snps,dis_metastability_quirk");

diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h
index 5612bfdf37da92a3f5a3186e81a3e182f6dfc6fb..324ca5f5e98dd1a88dcfe65b747c863853499fef 100644 (file)
--- a/drivers/usb/dwc3/core.h
+++ b/drivers/usb/dwc3/core.h
@@ -387,6 +387,10 @@
 #define DWC3_GFLADJ_30MHZ_SDBND_SEL            BIT(7)
 #define DWC3_GFLADJ_30MHZ_MASK                 0x3f
 
+/* Global User Control Register*/
+#define DWC3_GUCTL_REFCLKPER_MASK              0xffc00000
+#define DWC3_GUCTL_REFCLKPER_SEL               22
+
 /* Global User Control Register 2 */
 #define DWC3_GUCTL2_RST_ACTBITLATER            BIT(14)
 
@@ -970,6 +974,7 @@ struct dwc3_scratchpad_array {
  * @regs: base address for our registers
  * @regs_size: address space size
  * @fladj: frame length adjustment
+ * @ref_clk_per: reference clock period configuration
  * @irq_gadget: peripheral controller's IRQ number
  * @otg_irq: IRQ number for OTG IRQs
  * @current_otg_role: current role of operation while using the OTG block
@@ -1149,6 +1154,7 @@ struct dwc3 {
        struct power_supply     *usb_psy;
 
        u32                     fladj;
+       u32                     ref_clk_per;
        u32                     irq_gadget;
        u32                     otg_irq;
        u32                     current_otg_role;