drm/i915/reg: fix pipe data/link m/n register style

Adhere to the style described at the top of i915_reg.h.

Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/99fb1c8aabb7646ca2565db0b969cf15d9103318.1725974820.git.jani.nikula@intel.com
Signed-off-by: Jani Nikula <jani.nikula@intel.com>

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 591a6dc9c3bc99c9f3271cd777391b4d14b34d50..9ece696baae80a77a020251c69348c232bee34e3 100644 (file)
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2160,32 +2160,35 @@
 # define VFMUNIT_CLOCK_GATE_DISABLE            (1 << 11)
 
 #define _PIPEA_DATA_M1         0x60030
-#define _PIPEA_DATA_N1         0x60034
-#define _PIPEA_DATA_M2         0x60038
-#define _PIPEA_DATA_N2         0x6003c
-#define _PIPEA_LINK_M1         0x60040
-#define _PIPEA_LINK_N1         0x60044
-#define _PIPEA_LINK_M2         0x60048
-#define _PIPEA_LINK_N2         0x6004c
-
-/* PIPEB timing regs are same start from 0x61000 */
-
 #define _PIPEB_DATA_M1         0x61030
-#define _PIPEB_DATA_N1         0x61034
-#define _PIPEB_DATA_M2         0x61038
-#define _PIPEB_DATA_N2         0x6103c
-#define _PIPEB_LINK_M1         0x61040
-#define _PIPEB_LINK_N1         0x61044
-#define _PIPEB_LINK_M2         0x61048
-#define _PIPEB_LINK_N2         0x6104c
-
 #define PIPE_DATA_M1(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_DATA_M1)
+
+#define _PIPEA_DATA_N1         0x60034
+#define _PIPEB_DATA_N1         0x61034
 #define PIPE_DATA_N1(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_DATA_N1)
+
+#define _PIPEA_DATA_M2         0x60038
+#define _PIPEB_DATA_M2         0x61038
 #define PIPE_DATA_M2(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_DATA_M2)
+
+#define _PIPEA_DATA_N2         0x6003c
+#define _PIPEB_DATA_N2         0x6103c
 #define PIPE_DATA_N2(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_DATA_N2)
+
+#define _PIPEA_LINK_M1         0x60040
+#define _PIPEB_LINK_M1         0x61040
 #define PIPE_LINK_M1(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_LINK_M1)
+
+#define _PIPEA_LINK_N1         0x60044
+#define _PIPEB_LINK_N1         0x61044
 #define PIPE_LINK_N1(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_LINK_N1)
+
+#define _PIPEA_LINK_M2         0x60048
+#define _PIPEB_LINK_M2         0x61048
 #define PIPE_LINK_M2(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_LINK_M2)
+
+#define _PIPEA_LINK_N2         0x6004c
+#define _PIPEB_LINK_N2         0x6104c
 #define PIPE_LINK_N2(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_LINK_N2)
 
 /* CPU panel fitter */