drm/i915: Start passing latency as parameter

We need to start passing memory latency as a
parameter when calculating plane wm levels,
as latency can get changed in different
circumstances(for example with or without SAGV).
So we need to be more flexible on that matter.

v2: Changed latency type from u32 to unsigned int(Ville Syrjälä)

Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20200409154730.18568-2-stanislav.lisovskiy@intel.com

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 8375054ba27d92b72f6b03a0e15f2703b5befdb5..b632b6bb9c3ee372a4256dff5261e7df33f5427b 100644 (file)
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4016,6 +4016,7 @@ static int skl_compute_wm_params(const struct intel_crtc_state *crtc_state,
                                 int color_plane);
 static void skl_compute_plane_wm(const struct intel_crtc_state *crtc_state,
                                 int level,
+                                unsigned int latency,
                                 const struct skl_wm_params *wp,
                                 const struct skl_wm_level *result_prev,
                                 struct skl_wm_level *result /* out */);
@@ -4038,7 +4039,9 @@ skl_cursor_allocation(const struct intel_crtc_state *crtc_state,
        drm_WARN_ON(&dev_priv->drm, ret);
 
        for (level = 0; level <= max_level; level++) {
-               skl_compute_plane_wm(crtc_state, level, &wp, &wm, &wm);
+               unsigned int latency = dev_priv->wm.skl_latency[level];
+
+               skl_compute_plane_wm(crtc_state, level, latency, &wp, &wm, &wm);
                if (wm.min_ddb_alloc == U16_MAX)
                        break;
 
@@ -4972,12 +4975,12 @@ static bool skl_wm_has_lines(struct drm_i915_private *dev_priv, int level)
 
 static void skl_compute_plane_wm(const struct intel_crtc_state *crtc_state,
                                 int level,
+                                unsigned int latency,
                                 const struct skl_wm_params *wp,
                                 const struct skl_wm_level *result_prev,
                                 struct skl_wm_level *result /* out */)
 {
        struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
-       u32 latency = dev_priv->wm.skl_latency[level];
        uint_fixed_16_16_t method1, method2;
        uint_fixed_16_16_t selected_result;
        u32 res_blocks, res_lines, min_ddb_alloc = 0;
@@ -5106,9 +5109,10 @@ skl_compute_wm_levels(const struct intel_crtc_state *crtc_state,
 
        for (level = 0; level <= max_level; level++) {
                struct skl_wm_level *result = &levels[level];
+               unsigned int latency = dev_priv->wm.skl_latency[level];
 
-               skl_compute_plane_wm(crtc_state, level, wm_params,
-                                    result_prev, result);
+               skl_compute_plane_wm(crtc_state, level, latency,
+                                    wm_params, result_prev, result);
 
                result_prev = result;
        }