if (!res->end)
                        res->end = limit + 0xfff;
                dev_printk(KERN_DEBUG, &dev->dev, "  bridge window %pR\n", res);
-       } else {
-               dev_printk(KERN_DEBUG, &dev->dev,
-                        "  bridge window [io  %#06lx-%#06lx] (disabled)\n",
-                                base, limit);
        }
 }
 
                res->start = base;
                res->end = limit + 0xfffff;
                dev_printk(KERN_DEBUG, &dev->dev, "  bridge window %pR\n", res);
-       } else {
-               dev_printk(KERN_DEBUG, &dev->dev,
-                       "  bridge window [mem %#010lx-%#010lx] (disabled)\n",
-                                        base, limit + 0xfffff);
        }
 }
 
                res->start = base;
                res->end = limit + 0xfffff;
                dev_printk(KERN_DEBUG, &dev->dev, "  bridge window %pR\n", res);
-       } else {
-               dev_printk(KERN_DEBUG, &dev->dev,
-                    "  bridge window [mem %#010lx-%#010lx pref] (disabled)\n",
-                                        base, limit + 0xfffff);
        }
 }
 
 
                /* Clear upper 16 bits of I/O base/limit. */
                io_upper16 = 0;
                l = 0x00f0;
-               dev_info(&bridge->dev, "  bridge window [io  disabled]\n");
        }
        /* Temporarily disable the I/O range before updating PCI_IO_BASE. */
        pci_write_config_dword(bridge, PCI_IO_BASE_UPPER16, 0x0000ffff);
                dev_info(&bridge->dev, "  bridge window %pR\n", res);
        } else {
                l = 0x0000fff0;
-               dev_info(&bridge->dev, "  bridge window [mem disabled]\n");
        }
        pci_write_config_dword(bridge, PCI_MEMORY_BASE, l);
 }
                dev_info(&bridge->dev, "  bridge window %pR\n", res);
        } else {
                l = 0x0000fff0;
-               dev_info(&bridge->dev, "  bridge window [mem pref disabled]\n");
        }
        pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE, l);