#include <linux/mfd/syscon.h>
 #include <linux/regmap.h>
 #include <linux/delay.h>
-#include <linux/reset.h>
 #include <linux/of.h>
 #include <linux/clk.h>
 #include <linux/io.h>
  * @muxmode: the current muxing mode
  * @ide_pins: if the device is using the plain IDE interface pins
  * @sata_bridge: if the device enables the SATA bridge
- * @sata0_reset: SATA0 reset handler
- * @sata1_reset: SATA1 reset handler
  * @sata0_pclk: SATA0 PCLK handler
  * @sata1_pclk: SATA1 PCLK handler
  */
        enum gemini_muxmode muxmode;
        bool ide_pins;
        bool sata_bridge;
-       struct reset_control *sata0_reset;
-       struct reset_control *sata1_reset;
        struct clk *sata0_pclk;
        struct clk *sata1_pclk;
 };
                return ret;
        }
 
-       sg->sata0_reset = devm_reset_control_get_exclusive(dev, "sata0");
-       if (IS_ERR(sg->sata0_reset)) {
-               dev_err(dev, "no SATA0 reset controller\n");
-               clk_disable_unprepare(sg->sata1_pclk);
-               clk_disable_unprepare(sg->sata0_pclk);
-               return PTR_ERR(sg->sata0_reset);
-       }
-       sg->sata1_reset = devm_reset_control_get_exclusive(dev, "sata1");
-       if (IS_ERR(sg->sata1_reset)) {
-               dev_err(dev, "no SATA1 reset controller\n");
-               clk_disable_unprepare(sg->sata1_pclk);
-               clk_disable_unprepare(sg->sata0_pclk);
-               return PTR_ERR(sg->sata1_reset);
-       }
-
        sata_id = readl(sg->base + GEMINI_SATA_ID);
        sata_phy_id = readl(sg->base + GEMINI_SATA_PHY_ID);
        sg->sata_bridge = true;