wifi: rtw89: 8852c: support different SAR configs by antenna

Set SAR configs to the corresponding CRs (control registers) according to
RF path. Then, declare to support SAR by antenna in chip info.

Signed-off-by: Zong-Zhe Yang <kevin_yang@realtek.com>
Signed-off-by: Ping-Ke Shih <pkshih@realtek.com>
Link: https://patch.msgid.link/20250326020643.14487-12-pkshih@realtek.com

diff --git a/drivers/net/wireless/realtek/rtw89/reg.h b/drivers/net/wireless/realtek/rtw89/reg.h
index d0840ad95e56cb646e0841ea9fd96cfa57924d06..f05c81ae586949212044f60362ba78b0f4b3fdcd 100644 (file)
--- a/drivers/net/wireless/realtek/rtw89/reg.h
+++ b/drivers/net/wireless/realtek/rtw89/reg.h
@@ -8745,8 +8745,10 @@
 #define B_DPD_GDIS BIT(13)
 #define B_IQK_RFC_ON BIT(1)
 #define R_TXPWRB 0x56CC
+#define R_P1_TXPWRB 0x76CC
 #define B_TXPWRB_ON BIT(28)
 #define B_TXPWRB_VAL GENMASK(27, 19)
+#define B_TXPWRB_MAX GENMASK(8, 0)
 #define R_DPD_OFT_EN 0x5800
 #define B_DPD_OFT_EN BIT(28)
 #define B_DPD_TSSI_CW GENMASK(26, 18)

diff --git a/drivers/net/wireless/realtek/rtw89/rtw8852c.c b/drivers/net/wireless/realtek/rtw89/rtw8852c.c
index cbbb6a9169d1f0aa547085aec4d9c0625ae74b32..a8fd573d50481510fd77d4e0aa19f08d72f9b012 100644 (file)
--- a/drivers/net/wireless/realtek/rtw89/rtw8852c.c
+++ b/drivers/net/wireless/realtek/rtw89/rtw8852c.c
@@ -2079,6 +2079,31 @@ static void rtw8852c_set_txpwr_diff(struct rtw89_dev *rtwdev,
        rtw8852c_set_txpwr_ref(rtwdev, phy_idx, pwr_ofst);
 }
 
+static void rtw8852c_set_txpwr_sar_diff(struct rtw89_dev *rtwdev,
+                                       const struct rtw89_chan *chan,
+                                       enum rtw89_phy_idx phy_idx)
+{
+       struct rtw89_sar_parm sar_parm = {
+               .center_freq = chan->freq,
+               .force_path = true,
+       };
+       s16 sar_rf;
+       s8 sar_mac;
+
+       if (phy_idx != RTW89_PHY_0)
+               return;
+
+       sar_parm.path = RF_PATH_A;
+       sar_mac = rtw89_query_sar(rtwdev, &sar_parm);
+       sar_rf = rtw89_phy_txpwr_mac_to_rf(rtwdev, sar_mac);
+       rtw89_phy_write32_mask(rtwdev, R_TXPWRB, B_TXPWRB_MAX, sar_rf);
+
+       sar_parm.path = RF_PATH_B;
+       sar_mac = rtw89_query_sar(rtwdev, &sar_parm);
+       sar_rf = rtw89_phy_txpwr_mac_to_rf(rtwdev, sar_mac);
+       rtw89_phy_write32_mask(rtwdev, R_P1_TXPWRB, B_TXPWRB_MAX, sar_rf);
+}
+
 static void rtw8852c_set_txpwr(struct rtw89_dev *rtwdev,
                               const struct rtw89_chan *chan,
                               enum rtw89_phy_idx phy_idx)
@@ -2089,6 +2114,7 @@ static void rtw8852c_set_txpwr(struct rtw89_dev *rtwdev,
        rtw89_phy_set_txpwr_limit(rtwdev, chan, phy_idx);
        rtw89_phy_set_txpwr_limit_ru(rtwdev, chan, phy_idx);
        rtw8852c_set_txpwr_diff(rtwdev, chan, phy_idx);
+       rtw8852c_set_txpwr_sar_diff(rtwdev, chan, phy_idx);
 }
 
 static void rtw8852c_set_txpwr_ctrl(struct rtw89_dev *rtwdev,
@@ -3014,7 +3040,7 @@ const struct rtw89_chip_info rtw8852c_chip_info = {
        .support_unii4          = true,
        .support_ant_gain       = true,
        .support_tas            = true,
-       .support_sar_by_ant     = false,
+       .support_sar_by_ant     = true,
        .ul_tb_waveform_ctrl    = false,
        .ul_tb_pwr_diff         = true,
        .rx_freq_frome_ie       = false,