uint32_t                        ras_hw_enabled;
        uint32_t                        ras_enabled;
 
-       bool                            in_pci_err_recovery;
+       bool                            no_hw_access;
        struct pci_saved_state          *pci_state;
 
        struct amdgpu_reset_control     *reset_cntl;
 
 /* Check if hw access should be skipped because of hotplug or device error */
 bool amdgpu_device_skip_hw_access(struct amdgpu_device *adev)
 {
-       if (adev->in_pci_err_recovery)
+       if (adev->no_hw_access)
                return true;
 
 #ifdef CONFIG_LOCKDEP
        set_bit(AMDGPU_NEED_FULL_RESET, &reset_context.flags);
        set_bit(AMDGPU_SKIP_HW_RESET, &reset_context.flags);
 
-       adev->in_pci_err_recovery = true;
+       adev->no_hw_access = true;
        r = amdgpu_device_pre_asic_reset(adev, &reset_context);
-       adev->in_pci_err_recovery = false;
+       adev->no_hw_access = false;
        if (r)
                goto out;
 
 
        int i;
        struct amdgpu_device *adev = psp->adev;
 
-       if (psp->adev->in_pci_err_recovery)
+       if (psp->adev->no_hw_access)
                return 0;
 
        for (i = 0; i < adev->usec_timeout; i++) {
        bool ras_intr = false;
        bool skip_unsupport = false;
 
-       if (psp->adev->in_pci_err_recovery)
+       if (psp->adev->no_hw_access)
                return 0;
 
        if (!drm_dev_enter(&psp->adev->ddev, &idx))
 
        amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0);
        amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0);
 
-       if (!adev->in_pci_err_recovery) {
+       if (!adev->no_hw_access) {
 #ifndef BRING_UP_DEBUG
                if (amdgpu_async_gfx_ring) {
                        r = gfx_v10_0_kiq_disable_kgq(adev);
 
        struct amdgpu_device *adev = smu->adev;
        int ret = 0, index = 0;
 
-       if (smu->adev->in_pci_err_recovery)
+       if (smu->adev->no_hw_access)
                return 0;
 
        index = smu_cmn_to_asic_specific_index(smu,