drm/amd/display: Update efficiency bandwidth for dcn351

Fix 4k240 underflow on dcn351

Acked-by: Rodrigo Siqueira <rodrigo.siqueira@amd.com>
Signed-off-by: Fangzhi Zuo <Jerry.Zuo@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/dml2/dml2_translation_helper.c b/drivers/gpu/drm/amd/display/dc/dml2/dml2_translation_helper.c
index a41812598ce84a716d695ed23fe7f0b19d83bf31..8ecc972dbffdea225acff3bf7df9ca58f73332ec 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dml2/dml2_translation_helper.c
+++ b/drivers/gpu/drm/amd/display/dc/dml2/dml2_translation_helper.c
@@ -234,6 +234,7 @@ void dml2_init_socbb_params(struct dml2_context *dml2, const struct dc *in_dc, s
                out->round_trip_ping_latency_dcfclk_cycles = 106;
                out->smn_latency_us = 2;
                out->dispclk_dppclk_vco_speed_mhz = 3600;
+               out->pct_ideal_dram_bw_after_urgent_pixel_only = 65.0;
                break;
 
        }