.ple_qt47 = {525, 0, 32, 20, 1034, 13, 1199, 0, 1053, 62, 160, 1037,},
        /* PCIE 64 */
        .ple_qt58 = {147, 0, 16, 20, 157, 13, 229, 0, 172, 14, 24, 0,},
+       /* 8852A PCIE WOW */
+       .ple_qt_52a_wow = {264, 0, 32, 20, 64, 13, 1005, 0, 64, 128, 120,},
 };
 EXPORT_SYMBOL(rtw89_mac_size);
 
                SET_QUOTA(tx_rpt, PLE, 11);
 }
 
+int rtw89_mac_resize_ple_rx_quota(struct rtw89_dev *rtwdev, bool wow)
+{
+       const struct rtw89_ple_quota *min_cfg, *max_cfg;
+       const struct rtw89_dle_mem *cfg;
+       u32 val;
+
+       if (rtwdev->chip->chip_id == RTL8852C)
+               return 0;
+
+       if (rtwdev->mac.qta_mode != RTW89_QTA_SCC) {
+               rtw89_err(rtwdev, "[ERR]support SCC mode only\n");
+               return -EINVAL;
+       }
+
+       if (wow)
+               cfg = get_dle_mem_cfg(rtwdev, RTW89_QTA_WOW);
+       else
+               cfg = get_dle_mem_cfg(rtwdev, RTW89_QTA_SCC);
+       if (!cfg) {
+               rtw89_err(rtwdev, "[ERR]get_dle_mem_cfg\n");
+               return -EINVAL;
+       }
+
+       min_cfg = cfg->ple_min_qt;
+       max_cfg = cfg->ple_max_qt;
+       SET_QUOTA(cma0_dma, PLE, 6);
+       SET_QUOTA(cma1_dma, PLE, 7);
+
+       return 0;
+}
 #undef SET_QUOTA
 
 static void dle_quota_cfg(struct rtw89_dev *rtwdev,
 
        const struct rtw89_ple_quota ple_qt46;
        const struct rtw89_ple_quota ple_qt47;
        const struct rtw89_ple_quota ple_qt58;
+       const struct rtw89_ple_quota ple_qt_52a_wow;
 };
 
 extern const struct rtw89_mac_size_set rtw89_mac_size;
 u16 rtw89_mac_dle_buf_req(struct rtw89_dev *rtwdev, u16 buf_len, bool wd);
 int rtw89_mac_set_cpuio(struct rtw89_dev *rtwdev,
                        struct rtw89_cpuio_ctrl *ctrl_para, bool wd);
+int rtw89_mac_resize_ple_rx_quota(struct rtw89_dev *rtwdev, bool wow);
 
 #endif
 
                           &rtw89_mac_size.ple_size0, &rtw89_mac_size.wde_qt0,
                           &rtw89_mac_size.wde_qt0, &rtw89_mac_size.ple_qt4,
                           &rtw89_mac_size.ple_qt5},
+       [RTW89_QTA_WOW] = {RTW89_QTA_WOW, &rtw89_mac_size.wde_size0,
+                          &rtw89_mac_size.ple_size0, &rtw89_mac_size.wde_qt0,
+                          &rtw89_mac_size.wde_qt0, &rtw89_mac_size.ple_qt4,
+                          &rtw89_mac_size.ple_qt_52a_wow},
        [RTW89_QTA_DLFW] = {RTW89_QTA_DLFW, &rtw89_mac_size.wde_size4,
                            &rtw89_mac_size.ple_size4, &rtw89_mac_size.wde_qt4,
                            &rtw89_mac_size.wde_qt4, &rtw89_mac_size.ple_qt13,