if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
                                            (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
                                                continue;
-                                       rdev->pm.power_state[state_index].non_clock_info.pcie_lanes =
+                                       rdev->pm.power_state[state_index].pcie_lanes =
                                                power_info->info.asPowerPlayInfo[i].ucNumPciELanes;
                                        misc = le32_to_cpu(power_info->info.asPowerPlayInfo[i].ulMiscInfo);
                                        if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) {
                                                        power_info->info.asPowerPlayInfo[i].ucVoltageDropIndex;
                                        }
                                        rdev->pm.power_state[state_index].flags = RADEON_PM_SINGLE_DISPLAY_ONLY;
+                                       rdev->pm.power_state[state_index].misc = misc;
                                        /* order matters! */
                                        if (misc & ATOM_PM_MISCINFO_POWER_SAVING_MODE)
                                                rdev->pm.power_state[state_index].type =
                                        if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
                                            (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
                                                continue;
-                                       rdev->pm.power_state[state_index].non_clock_info.pcie_lanes =
+                                       rdev->pm.power_state[state_index].pcie_lanes =
                                                power_info->info_2.asPowerPlayInfo[i].ucNumPciELanes;
                                        misc = le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMiscInfo);
                                        misc2 = le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMiscInfo2);
                                                        power_info->info_2.asPowerPlayInfo[i].ucVoltageDropIndex;
                                        }
                                        rdev->pm.power_state[state_index].flags = RADEON_PM_SINGLE_DISPLAY_ONLY;
+                                       rdev->pm.power_state[state_index].misc = misc;
+                                       rdev->pm.power_state[state_index].misc2 = misc2;
                                        /* order matters! */
                                        if (misc & ATOM_PM_MISCINFO_POWER_SAVING_MODE)
                                                rdev->pm.power_state[state_index].type =
                                        if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
                                            (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
                                                continue;
-                                       rdev->pm.power_state[state_index].non_clock_info.pcie_lanes =
+                                       rdev->pm.power_state[state_index].pcie_lanes =
                                                power_info->info_3.asPowerPlayInfo[i].ucNumPciELanes;
                                        misc = le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMiscInfo);
                                        misc2 = le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMiscInfo2);
                                                }
                                        }
                                        rdev->pm.power_state[state_index].flags = RADEON_PM_SINGLE_DISPLAY_ONLY;
+                                       rdev->pm.power_state[state_index].misc = misc;
+                                       rdev->pm.power_state[state_index].misc2 = misc2;
                                        /* order matters! */
                                        if (misc & ATOM_PM_MISCINFO_POWER_SAVING_MODE)
                                                rdev->pm.power_state[state_index].type =
                                        &rdev->pm.power_state[state_index - 1].clock_info[0];
                                rdev->pm.power_state[state_index].flags &=
                                        ~RADEON_PM_SINGLE_DISPLAY_ONLY;
+                               rdev->pm.power_state[state_index].misc = 0;
+                               rdev->pm.power_state[state_index].misc2 = 0;
                        }
                } else {
                        /* add the i2c bus for thermal/fan chip */
                                if (mode_index) {
                                        misc = le32_to_cpu(non_clock_info->ulCapsAndSettings);
                                        misc2 = le16_to_cpu(non_clock_info->usClassification);
-                                       rdev->pm.power_state[state_index].non_clock_info.pcie_lanes =
+                                       rdev->pm.power_state[state_index].misc = misc;
+                                       rdev->pm.power_state[state_index].misc2 = misc2;
+                                       rdev->pm.power_state[state_index].pcie_lanes =
                                                ((misc & ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >>
                                                ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT) + 1;
                                        switch (misc2 & ATOM_PPLIB_CLASSIFICATION_UI_MASK) {
                rdev->pm.power_state[state_index].default_clock_mode =
                        &rdev->pm.power_state[state_index].clock_info[0];
                rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE;
-               if (rdev->asic->get_pcie_lanes)
-                       rdev->pm.power_state[state_index].non_clock_info.pcie_lanes = radeon_get_pcie_lanes(rdev);
-               else
-                       rdev->pm.power_state[state_index].non_clock_info.pcie_lanes = 16;
+               rdev->pm.power_state[state_index].pcie_lanes = 16;
                rdev->pm.default_power_state_index = state_index;
                rdev->pm.power_state[state_index].flags = 0;
                state_index++;
 
                        if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
                            (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
                                goto default_mode;
-                       /* skip overclock modes for now */
-                       if ((rdev->pm.power_state[state_index].clock_info[0].mclk >
-                            rdev->clock.default_mclk + RADEON_MODE_OVERCLOCK_MARGIN) ||
-                           (rdev->pm.power_state[state_index].clock_info[0].sclk >
-                            rdev->clock.default_sclk + RADEON_MODE_OVERCLOCK_MARGIN))
-                               goto default_mode;
                        rdev->pm.power_state[state_index].type =
                                POWER_STATE_TYPE_BATTERY;
                        misc = RBIOS16(offset + 0x5 + 0x0);
                        if (rev > 4)
                                misc2 = RBIOS16(offset + 0x5 + 0xe);
+                       rdev->pm.power_state[state_index].misc = misc;
+                       rdev->pm.power_state[state_index].misc2 = misc2;
                        if (misc & 0x4) {
                                rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_GPIO;
                                if (misc & 0x8)
                        } else
                                rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE;
                        if (rev > 6)
-                               rdev->pm.power_state[state_index].non_clock_info.pcie_lanes =
+                               rdev->pm.power_state[state_index].pcie_lanes =
                                        RBIOS8(offset + 0x5 + 0x10);
                        rdev->pm.power_state[state_index].flags = RADEON_PM_SINGLE_DISPLAY_ONLY;
                        state_index++;
        rdev->pm.power_state[state_index].clock_info[0].sclk = rdev->clock.default_sclk;
        rdev->pm.power_state[state_index].default_clock_mode = &rdev->pm.power_state[state_index].clock_info[0];
        rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE;
-       if (rdev->asic->get_pcie_lanes)
-               rdev->pm.power_state[state_index].non_clock_info.pcie_lanes = radeon_get_pcie_lanes(rdev);
-       else
-               rdev->pm.power_state[state_index].non_clock_info.pcie_lanes = 16;
+       rdev->pm.power_state[state_index].pcie_lanes = 16;
        rdev->pm.power_state[state_index].flags = 0;
        rdev->pm.default_power_state_index = state_index;
        rdev->pm.num_power_states = state_index + 1;