riscv: dts: microchip: move timebase-frequency to mpfs.dtsi

The timebase-frequency on PolarFire SoC is not set by an oscillator on
the board, but rather by an internal divider, so move the property to
mpfs.dtsi.

This looks to be copy-pasta from the SiFive Unleashed as the comments
in both places were almost identical. In the Unleashed's case this looks
to actually be valid, as the clock is provided by a crystal on the PCB.

Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
---
CC: Conor Dooley <conor.dooley@microchip.com>
CC: Daire McNamara <daire.mcnamara@microchip.com>
CC: Rob Herring <robh+dt@kernel.org>
CC: Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>
CC: Paul Walmsley <paul.walmsley@sifive.com>
CC: Palmer Dabbelt <palmer@dabbelt.com>
CC: linux-riscv@lists.infradead.org
CC: devicetree@vger.kernel.org

diff --git a/arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dts b/arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dts
index 90b261114763753565001398edcb4c86e3631ab1..dce96f27cc89a4af44c61209be59a105c49d05ca 100644 (file)
--- a/arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dts
+++ b/arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dts
@@ -8,9 +8,6 @@
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/leds/common.h>
 
-/* Clock frequency (in Hz) of the rtcclk */
-#define RTCCLK_FREQ            1000000
-
 / {
        model = "Microchip PolarFire-SoC Icicle Kit";
        compatible = "microchip,mpfs-icicle-reference-rtlv2210", "microchip,mpfs-icicle-kit",
@@ -29,10 +26,6 @@
                stdout-path = "serial1:115200n8";
        };
 
-       cpus {
-               timebase-frequency = <RTCCLK_FREQ>;
-       };
-
        leds {
                compatible = "gpio-leds";
 

diff --git a/arch/riscv/boot/dts/microchip/mpfs-m100pfsevp.dts b/arch/riscv/boot/dts/microchip/mpfs-m100pfsevp.dts
index 184cb36a175e40742763510b8b1e7eca6d9c784a..a8d623ee9fa4cedacb177fbe7ebf94a5eb3df3d3 100644 (file)
--- a/arch/riscv/boot/dts/microchip/mpfs-m100pfsevp.dts
+++ b/arch/riscv/boot/dts/microchip/mpfs-m100pfsevp.dts
@@ -10,9 +10,6 @@
 #include "mpfs.dtsi"
 #include "mpfs-m100pfs-fabric.dtsi"
 
-/* Clock frequency (in Hz) of the rtcclk */
-#define MTIMER_FREQ    1000000
-
 / {
        model = "Aries Embedded M100PFEVPS";
        compatible = "aries,m100pfsevp", "microchip,mpfs";
@@ -33,10 +30,6 @@
                stdout-path = "serial1:115200n8";
        };
 
-       cpus {
-               timebase-frequency = <MTIMER_FREQ>;
-       };
-
        ddrc_cache_lo: memory@80000000 {
                device_type = "memory";
                reg = <0x0 0x80000000 0x0 0x40000000>;

diff --git a/arch/riscv/boot/dts/microchip/mpfs-polarberry.dts b/arch/riscv/boot/dts/microchip/mpfs-polarberry.dts
index c87cc2d8fe29fa2174bbedca08c272c7331283b8..ea0808ab104255ea6cfcff1a1bc99adbbdc81905 100644 (file)
--- a/arch/riscv/boot/dts/microchip/mpfs-polarberry.dts
+++ b/arch/riscv/boot/dts/microchip/mpfs-polarberry.dts
@@ -6,9 +6,6 @@
 #include "mpfs.dtsi"
 #include "mpfs-polarberry-fabric.dtsi"
 
-/* Clock frequency (in Hz) of the rtcclk */
-#define MTIMER_FREQ    1000000
-
 / {
        model = "Sundance PolarBerry";
        compatible = "sundance,polarberry", "microchip,mpfs";
@@ -22,10 +19,6 @@
                stdout-path = "serial0:115200n8";
        };
 
-       cpus {
-               timebase-frequency = <MTIMER_FREQ>;
-       };
-
        ddrc_cache_lo: memory@80000000 {
                device_type = "memory";
                reg = <0x0 0x80000000 0x0 0x2e000000>;

diff --git a/arch/riscv/boot/dts/microchip/mpfs-sev-kit.dts b/arch/riscv/boot/dts/microchip/mpfs-sev-kit.dts
index 013cb666c72da8e539a4bfbc8c5ddeb560272160..f9a89057943834766cb60b14a70a855df416566f 100644 (file)
--- a/arch/riscv/boot/dts/microchip/mpfs-sev-kit.dts
+++ b/arch/riscv/boot/dts/microchip/mpfs-sev-kit.dts
@@ -6,9 +6,6 @@
 #include "mpfs.dtsi"
 #include "mpfs-sev-kit-fabric.dtsi"
 
-/* Clock frequency (in Hz) of the rtcclk */
-#define MTIMER_FREQ            1000000
-
 / {
        #address-cells = <2>;
        #size-cells = <2>;
@@ -28,10 +25,6 @@
                stdout-path = "serial1:115200n8";
        };
 
-       cpus {
-               timebase-frequency = <MTIMER_FREQ>;
-       };
-
        reserved-memory {
                #address-cells = <2>;
                #size-cells = <2>;

diff --git a/arch/riscv/boot/dts/microchip/mpfs-tysom-m.dts b/arch/riscv/boot/dts/microchip/mpfs-tysom-m.dts
index e0797c7e1b3553a9f5623f730bb974c2101c6812..d1120f5f2c0153bbc9b967dd360159b6c6ee50e1 100644 (file)
--- a/arch/riscv/boot/dts/microchip/mpfs-tysom-m.dts
+++ b/arch/riscv/boot/dts/microchip/mpfs-tysom-m.dts
@@ -11,9 +11,6 @@
 #include "mpfs.dtsi"
 #include "mpfs-tysom-m-fabric.dtsi"
 
-/* Clock frequency (in Hz) of the rtcclk */
-#define MTIMER_FREQ            1000000
-
 / {
        model = "Aldec TySOM-M-MPFS250T-REV2";
        compatible = "aldec,tysom-m-mpfs250t-rev2", "microchip,mpfs";
@@ -34,10 +31,6 @@
                stdout-path = "serial1:115200n8";
        };
 
-       cpus {
-               timebase-frequency = <MTIMER_FREQ>;
-       };
-
        ddrc_cache_lo: memory@80000000 {
                device_type = "memory";
                reg = <0x0 0x80000000 0x0 0x30000000>;

diff --git a/arch/riscv/boot/dts/microchip/mpfs.dtsi b/arch/riscv/boot/dts/microchip/mpfs.dtsi
index a6faf24f1dbaf659eb9f0df6baadc34fa3246f52..266489d43912fc4457cb2bad3cc8d9d67b8d4dcd 100644 (file)
--- a/arch/riscv/boot/dts/microchip/mpfs.dtsi
+++ b/arch/riscv/boot/dts/microchip/mpfs.dtsi
@@ -13,6 +13,7 @@
        cpus {
                #address-cells = <1>;
                #size-cells = <0>;
+               timebase-frequency = <1000000>;
 
                cpu0: cpu@0 {
                        compatible = "sifive,e51", "sifive,rocket0", "riscv";