RDMA/bnxt_re: Fix a bug while setting up Level-2 PBL pages

Avoid memory corruption while setting up Level-2 PBL pages for the non MR
resources when num_pages > 256K.

There will be a single PDE page address (contiguous pages in the case of >
PAGE_SIZE), but, current logic assumes multiple pages, leading to invalid
memory access after 256K PBL entries in the PDE.

Fixes: 0c4dcd602817 ("RDMA/bnxt_re: Refactor hardware queue memory allocation")
Link: https://patch.msgid.link/r/1728373302-19530-10-git-send-email-selvin.xavier@broadcom.com
Signed-off-by: Bhargava Chenna Marreddy <bhargava.marreddy@broadcom.com>
Signed-off-by: Selvin Xavier <selvin.xavier@broadcom.com>
Signed-off-by: Jason Gunthorpe <jgg@nvidia.com>

diff --git a/drivers/infiniband/hw/bnxt_re/qplib_res.c b/drivers/infiniband/hw/bnxt_re/qplib_res.c
index 1fdffd6a0f4808c941494d92a2ba31d52a7e7822..96ceec1e8199a6ba52792e60ffc9b55cb7fb3624 100644 (file)
--- a/drivers/infiniband/hw/bnxt_re/qplib_res.c
+++ b/drivers/infiniband/hw/bnxt_re/qplib_res.c
@@ -257,22 +257,9 @@ int bnxt_qplib_alloc_init_hwq(struct bnxt_qplib_hwq *hwq,
                        dst_virt_ptr =
                                (dma_addr_t **)hwq->pbl[PBL_LVL_0].pg_arr;
                        src_phys_ptr = hwq->pbl[PBL_LVL_1].pg_map_arr;
-                       if (hwq_attr->type == HWQ_TYPE_MR) {
-                       /* For MR it is expected that we supply only 1 contigous
-                        * page i.e only 1 entry in the PDL that will contain
-                        * all the PBLs for the user supplied memory region
-                        */
-                               for (i = 0; i < hwq->pbl[PBL_LVL_1].pg_count;
-                                    i++)
-                                       dst_virt_ptr[0][i] = src_phys_ptr[i] |
-                                               flag;
-                       } else {
-                               for (i = 0; i < hwq->pbl[PBL_LVL_1].pg_count;
-                                    i++)
-                                       dst_virt_ptr[PTR_PG(i)][PTR_IDX(i)] =
-                                               src_phys_ptr[i] |
-                                               PTU_PDE_VALID;
-                       }
+                       for (i = 0; i < hwq->pbl[PBL_LVL_1].pg_count; i++)
+                               dst_virt_ptr[0][i] = src_phys_ptr[i] | flag;
+
                        /* Alloc or init PTEs */
                        rc = __alloc_pbl(res, &hwq->pbl[PBL_LVL_2],
                                         hwq_attr->sginfo);