{ 0x1000, "A" }, { 0x1001, "Z" },
};
+static const struct stm32l4_rev stm32c05xx_revs[] = {
+ { 0x1000, "A" },
+};
+
static const struct stm32l4_rev stm32c071xx_revs[] = {
{ 0x1001, "Z" },
};
+static const struct stm32l4_rev stm32c09xx_revs[] = {
+ { 0x1000, "A" },
+};
+
static const struct stm32l4_rev stm32g05_g06xx_revs[] = {
{ 0x1000, "A" },
};
.otp_base = 0x1FFF7000,
.otp_size = 1024,
},
+ {
+ .id = DEVID_STM32C05XX,
+ .revs = stm32c05xx_revs,
+ .num_revs = ARRAY_SIZE(stm32c05xx_revs),
+ .device_str = "STM32C05xx",
+ .max_flash_size_kb = 64,
+ .flags = F_NONE,
+ .flash_regs_base = 0x40022000,
+ .fsize_addr = 0x1FFF75A0,
+ .otp_base = 0x1FFF7000,
+ .otp_size = 1024,
+ },
{
.id = DEVID_STM32C071XX,
.revs = stm32c071xx_revs,
.otp_base = 0x1FFF7000,
.otp_size = 1024,
},
+ {
+ .id = DEVID_STM32C09XX,
+ .revs = stm32c09xx_revs,
+ .num_revs = ARRAY_SIZE(stm32c09xx_revs),
+ .device_str = "STM32C09xx",
+ .max_flash_size_kb = 256,
+ .flags = F_NONE,
+ .flash_regs_base = 0x40022000,
+ .fsize_addr = 0x1FFF75A0,
+ .otp_base = 0x1FFF7000,
+ .otp_size = 1024,
+ },
{
.id = DEVID_STM32U53_U54XX,
.revs = stm32u53_u54xx_revs,
case DEVID_STM32L43_L44XX:
case DEVID_STM32C01XX:
case DEVID_STM32C03XX:
+ case DEVID_STM32C05XX:
case DEVID_STM32C071XX:
+ case DEVID_STM32C09XX:
case DEVID_STM32G05_G06XX:
case DEVID_STM32G07_G08XX:
case DEVID_STM32U031XX:
#define DEVID_STM32L47_L48XX 0x415
#define DEVID_STM32L43_L44XX 0x435
#define DEVID_STM32C01XX 0x443
+#define DEVID_STM32C05XX 0x44C
+#define DEVID_STM32C09XX 0x44D
#define DEVID_STM32C03XX 0x453
#define DEVID_STM32U53_U54XX 0x455
#define DEVID_STM32G05_G06XX 0x456