arm64: dts: qcom: sm8350: Fix level triggered PMU interrupt polarity

As per interrupt documentation for SM8350 SoC, the polarity
for level triggered PMU interrupt is low, fix this.

Fixes: b7e8f433a673 ("arm64: dts: qcom: Add basic devicetree support for SM8350 SoC")
Signed-off-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>
Link: https://lore.kernel.org/r/ca57409198477f7815e32a6a7467dcdc9b93dc4f.1613468366.git.saiprakash.ranjan@codeaurora.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>

diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi
index 617bc1993217b9d1b123eecb35b21dc97292edf4..8a40fe48469ea4d3a051b72c4fe3acc2588091db 100644 (file)
--- a/arch/arm64/boot/dts/qcom/sm8350.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi
@@ -153,7 +153,7 @@
 
        pmu {
                compatible = "arm,armv8-pmuv3";
-               interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
+               interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
        };
 
        psci {