]> www.infradead.org Git - users/hch/misc.git/commitdiff
dt-bindings: clock: loongson2: Add Loongson-2K0300 compatible
authorYao Zi <ziyao@disroot.org>
Fri, 19 Sep 2025 14:26:42 +0000 (14:26 +0000)
committerStephen Boyd <sboyd@kernel.org>
Sun, 21 Sep 2025 19:48:30 +0000 (12:48 -0700)
Document the clock controller shipped in Loongson-2K0300 SoC, which
generates various clock signals for SoC peripherals. Differing from
previous generations of SoCs, LS2K0300 requires a 120MHz external clock
input.

Signed-off-by: Yao Zi <ziyao@disroot.org>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Yanteng Si <siyanteng@cqsoftware.com.cn>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Documentation/devicetree/bindings/clock/loongson,ls2k-clk.yaml
include/dt-bindings/clock/loongson,ls2k-clk.h

index 4f79cdb417ab6397509901c4136b9e033815976d..c07ad1f858578d8f1a94e416750430a0e80e7742 100644 (file)
@@ -16,6 +16,7 @@ description: |
 properties:
   compatible:
     enum:
+      - loongson,ls2k0300-clk
       - loongson,ls2k0500-clk
       - loongson,ls2k-clk  # This is for Loongson-2K1000
       - loongson,ls2k2000-clk
@@ -24,8 +25,7 @@ properties:
     maxItems: 1
 
   clocks:
-    items:
-      - description: 100m ref
+    maxItems: 1
 
   clock-names:
     items:
@@ -38,11 +38,23 @@ properties:
       ID in its "clocks" phandle cell. See include/dt-bindings/clock/loongson,ls2k-clk.h
       for the full list of Loongson-2 SoC clock IDs.
 
+allOf:
+  - if:
+      properties:
+        compatible:
+          contains:
+            const: loongson,ls2k0300-clk
+    then:
+      properties:
+        clock-names: false
+    else:
+      required:
+        - clock-names
+
 required:
   - compatible
   - reg
   - clocks
-  - clock-names
   - '#clock-cells'
 
 additionalProperties: false
index 4279ba595f1e0396c21083bb0c5b0eb3f5119311..8cbb86b2cf1ecf62d868b683fa1f1230585ae9ca 100644 (file)
 #define LOONGSON2_I2S_CLK      33
 #define LOONGSON2_MISC_CLK     34
 
+#define LS2K0300_CLK_STABLE            0
+#define LS2K0300_NODE_PLL              1
+#define LS2K0300_DDR_PLL               2
+#define LS2K0300_PIX_PLL               3
+#define LS2K0300_CLK_THSENS            4
+#define LS2K0300_CLK_NODE_DIV          5
+#define LS2K0300_CLK_NODE_PLL_GATE     6
+#define LS2K0300_CLK_NODE_SCALE                7
+#define LS2K0300_CLK_NODE_GATE         8
+#define LS2K0300_CLK_GMAC_DIV          9
+#define LS2K0300_CLK_GMAC_GATE         10
+#define LS2K0300_CLK_I2S_DIV           11
+#define LS2K0300_CLK_I2S_SCALE         12
+#define LS2K0300_CLK_I2S_GATE          13
+#define LS2K0300_CLK_DDR_DIV           14
+#define LS2K0300_CLK_DDR_GATE          15
+#define LS2K0300_CLK_NET_DIV           16
+#define LS2K0300_CLK_NET_GATE          17
+#define LS2K0300_CLK_DEV_DIV           18
+#define LS2K0300_CLK_DEV_GATE          19
+#define LS2K0300_CLK_PIX_DIV           20
+#define LS2K0300_CLK_PIX_PLL_GATE      21
+#define LS2K0300_CLK_PIX_SCALE         22
+#define LS2K0300_CLK_PIX_GATE          23
+#define LS2K0300_CLK_GMACBP_DIV                24
+#define LS2K0300_CLK_GMACBP_GATE       25
+#define LS2K0300_CLK_USB_SCALE         26
+#define LS2K0300_CLK_USB_GATE          27
+#define LS2K0300_CLK_APB_SCALE         28
+#define LS2K0300_CLK_APB_GATE          29
+#define LS2K0300_CLK_BOOT_SCALE                30
+#define LS2K0300_CLK_BOOT_GATE         31
+#define LS2K0300_CLK_SDIO_SCALE                32
+#define LS2K0300_CLK_SDIO_GATE         33
+#define LS2K0300_CLK_GMAC_IN           34
+
 #endif