drm/vc4: dsi: Use snprintf for the PHY clocks instead of an array

[ Upstream commit dc0bf36401e891c853e0a25baeb4e0b4e6f3626d ]

The DSI clocks setup function has been using an array to store the clock
name of either the DSI0 or DSI1 blocks, using the port ID to choose the
proper one.

Let's switch to an snprintf call to do the same thing and simplify the
array a bit.

Reviewed-by: Dave Stevenson <dave.stevenson@raspberrypi.com>
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
Link: https://patchwork.freedesktop.org/patch/msgid/20201203132543.861591-4-maxime@cerno.tech
Signed-off-by: Sasha Levin <sashal@kernel.org>

diff --git a/drivers/gpu/drm/vc4/vc4_dsi.c b/drivers/gpu/drm/vc4/vc4_dsi.c
index 6222e4058c85fb5f9cbc21987e6c5b0afa373ff4..80cd2599c57bd3c38daaf996f4e7d544b0b8bad5 100644 (file)
--- a/drivers/gpu/drm/vc4/vc4_dsi.c
+++ b/drivers/gpu/drm/vc4/vc4_dsi.c
@@ -1388,12 +1388,12 @@ vc4_dsi_init_phy_clocks(struct vc4_dsi *dsi)
        struct device *dev = &dsi->pdev->dev;
        const char *parent_name = __clk_get_name(dsi->pll_phy_clock);
        static const struct {
-               const char *dsi0_name, *dsi1_name;
+               const char *name;
                int div;
        } phy_clocks[] = {
-               { "dsi0_byte", "dsi1_byte", 8 },
-               { "dsi0_ddr2", "dsi1_ddr2", 4 },
-               { "dsi0_ddr", "dsi1_ddr", 2 },
+               { "byte", 8 },
+               { "ddr2", 4 },
+               { "ddr", 2 },
        };
        int i;
 
@@ -1409,8 +1409,12 @@ vc4_dsi_init_phy_clocks(struct vc4_dsi *dsi)
        for (i = 0; i < ARRAY_SIZE(phy_clocks); i++) {
                struct clk_fixed_factor *fix = &dsi->phy_clocks[i];
                struct clk_init_data init;
+               char clk_name[16];
                int ret;
 
+               snprintf(clk_name, sizeof(clk_name),
+                        "dsi%u_%s", dsi->port, phy_clocks[i].name);
+
                /* We just use core fixed factor clock ops for the PHY
                 * clocks.  The clocks are actually gated by the
                 * PHY_AFEC0_DDRCLK_EN bits, which we should be
@@ -1427,10 +1431,7 @@ vc4_dsi_init_phy_clocks(struct vc4_dsi *dsi)
                memset(&init, 0, sizeof(init));
                init.parent_names = &parent_name;
                init.num_parents = 1;
-               if (dsi->port == 1)
-                       init.name = phy_clocks[i].dsi1_name;
-               else
-                       init.name = phy_clocks[i].dsi0_name;
+               init.name = clk_name;
                init.ops = &clk_fixed_factor_ops;
 
                ret = devm_clk_hw_register(dev, &fix->hw);