#define IS_GEMINILAKE(dev_priv)        IS_PLATFORM(dev_priv, INTEL_GEMINILAKE)
 #define IS_COFFEELAKE(dev_priv)        IS_PLATFORM(dev_priv, INTEL_COFFEELAKE)
 #define IS_COMETLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_COMETLAKE)
-#define IS_CANNONLAKE(dev_priv)        IS_PLATFORM(dev_priv, INTEL_CANNONLAKE)
+#define IS_CANNONLAKE(dev_priv)        0
 #define IS_ICELAKE(dev_priv)   IS_PLATFORM(dev_priv, INTEL_ICELAKE)
 #define IS_JSL_EHL(dev_priv)   (IS_PLATFORM(dev_priv, INTEL_JASPERLAKE) || \
                                IS_PLATFORM(dev_priv, INTEL_ELKHARTLAKE))
 #define IS_CML_GT2(dev_priv)   (IS_COMETLAKE(dev_priv) && \
                                 INTEL_INFO(dev_priv)->gt == 2)
 
-#define IS_CNL_WITH_PORT_F(dev_priv) \
-       IS_SUBPLATFORM(dev_priv, INTEL_CANNONLAKE, INTEL_SUBPLATFORM_PORTF)
 #define IS_ICL_WITH_PORT_F(dev_priv) \
        IS_SUBPLATFORM(dev_priv, INTEL_ICELAKE, INTEL_SUBPLATFORM_PORTF)
 
 
 /* WaRsDisableCoarsePowerGating:skl,cnl */
 #define NEEDS_WaRsDisableCoarsePowerGating(dev_priv)                   \
-       (IS_CANNONLAKE(dev_priv) ||                                     \
-        IS_SKL_GT3(dev_priv) ||                                        \
-        IS_SKL_GT4(dev_priv))
+       (IS_SKL_GT3(dev_priv) || IS_SKL_GT4(dev_priv))
 
 #define HAS_GMBUS_IRQ(dev_priv) (GRAPHICS_VER(dev_priv) >= 4)
 #define HAS_GMBUS_BURST_READ(dev_priv) (GRAPHICS_VER(dev_priv) >= 11 || \
 
        .gt = 2,
 };
 
-#define GEN10_FEATURES \
-       GEN9_FEATURES, \
-       GEN(10), \
-       .dbuf.size = 1024 - 4, /* 4 blocks for bypass path allocation */ \
-       .display.has_dsc = 1, \
-       .has_coherent_ggtt = false, \
-       GLK_COLORS
-
-static const struct intel_device_info cnl_info = {
-       GEN10_FEATURES,
-       PLATFORM(INTEL_CANNONLAKE),
-       .gt = 2,
-};
-
 #define GEN11_DEFAULT_PAGE_SIZES \
        .page_sizes = I915_GTT_PAGE_SIZE_4K | \
                      I915_GTT_PAGE_SIZE_64K | \
                      I915_GTT_PAGE_SIZE_2M
 
 #define GEN11_FEATURES \
-       GEN10_FEATURES, \
+       GEN9_FEATURES, \
        GEN11_DEFAULT_PAGE_SIZES, \
        .abox_mask = BIT(0), \
        .cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \
                [TRANSCODER_DSI_1] = TRANSCODER_DSI1_OFFSET, \
        }, \
        GEN(11), \
+       .color = { .degamma_lut_size = 33, .gamma_lut_size = 262145 }, \
        .dbuf.size = 2048, \
        .dbuf.slice_mask = BIT(DBUF_S1) | BIT(DBUF_S2), \
-       .has_logical_ring_elsq = 1, \
-       .color = { .degamma_lut_size = 33, .gamma_lut_size = 262145 }
+       .display.has_dsc = 1, \
+       .has_coherent_ggtt = false, \
+       .has_logical_ring_elsq = 1
 
 static const struct intel_device_info icl_info = {
        GEN11_FEATURES,
        INTEL_CML_GT2_IDS(&cml_gt2_info),
        INTEL_CML_U_GT1_IDS(&cml_gt1_info),
        INTEL_CML_U_GT2_IDS(&cml_gt2_info),
-       INTEL_CNL_IDS(&cnl_info),
        INTEL_ICL_11_IDS(&icl_info),
        INTEL_EHL_IDS(&ehl_info),
        INTEL_JSL_IDS(&jsl_info),
 
        PLATFORM_NAME(GEMINILAKE),
        PLATFORM_NAME(COFFEELAKE),
        PLATFORM_NAME(COMETLAKE),
-       PLATFORM_NAME(CANNONLAKE),
        PLATFORM_NAME(ICELAKE),
        PLATFORM_NAME(ELKHARTLAKE),
        PLATFORM_NAME(JASPERLAKE),
 };
 
 static const u16 subplatform_portf_ids[] = {
-       INTEL_CNL_PORT_F_IDS(0),
        INTEL_ICL_PORT_F_IDS(0),
 };