iommu/vt-d: Prepare for multiple DMA domain types

In preparation for the strict vs. non-strict decision for DMA domains
to be expressed in the domain type, make sure we expose our flush queue
awareness by accepting the new domain type, and test the specific
feature flag where we want to identify DMA domains in general. The DMA
ops reset/setup can simply be made unconditional, since iommu-dma
already knows only to touch DMA domains.

Reviewed-by: Lu Baolu <baolu.lu@linux.intel.com>
Signed-off-by: Robin Murphy <robin.murphy@arm.com>
Link: https://lore.kernel.org/r/31a8ef868d593a2f3826a6a120edee81815375a7.1628682049.git.robin.murphy@arm.com
Signed-off-by: Joerg Roedel <jroedel@suse.de>

diff --git a/drivers/iommu/intel/iommu.c b/drivers/iommu/intel/iommu.c
index 7e168634c433fcc64f1a614e52887c357cdac07c..8fc46c9d6b96c643d9bcce212857ed713740fc66 100644 (file)
--- a/drivers/iommu/intel/iommu.c
+++ b/drivers/iommu/intel/iommu.c
@@ -582,7 +582,7 @@ struct intel_iommu *domain_get_iommu(struct dmar_domain *domain)
        int iommu_id;
 
        /* si_domain and vm domain should not get here. */
-       if (WARN_ON(domain->domain.type != IOMMU_DOMAIN_DMA))
+       if (WARN_ON(!iommu_is_dma_domain(&domain->domain)))
                return NULL;
 
        for_each_domain_iommu(iommu_id, domain)
@@ -1034,7 +1034,7 @@ static struct dma_pte *pfn_to_dma_pte(struct dmar_domain *domain,
                        pteval = ((uint64_t)virt_to_dma_pfn(tmp_page) << VTD_PAGE_SHIFT) | DMA_PTE_READ | DMA_PTE_WRITE;
                        if (domain_use_first_level(domain)) {
                                pteval |= DMA_FL_PTE_XD | DMA_FL_PTE_US;
-                               if (domain->domain.type == IOMMU_DOMAIN_DMA)
+                               if (iommu_is_dma_domain(&domain->domain))
                                        pteval |= DMA_FL_PTE_ACCESS;
                        }
                        if (cmpxchg64(&pte->val, 0ULL, pteval))
@@ -2345,7 +2345,7 @@ __domain_mapping(struct dmar_domain *domain, unsigned long iov_pfn,
        if (domain_use_first_level(domain)) {
                attr |= DMA_FL_PTE_XD | DMA_FL_PTE_US;
 
-               if (domain->domain.type == IOMMU_DOMAIN_DMA) {
+               if (iommu_is_dma_domain(&domain->domain)) {
                        attr |= DMA_FL_PTE_ACCESS;
                        if (prot & DMA_PTE_WRITE)
                                attr |= DMA_FL_PTE_DIRTY;
@@ -4528,6 +4528,7 @@ static struct iommu_domain *intel_iommu_domain_alloc(unsigned type)
 
        switch (type) {
        case IOMMU_DOMAIN_DMA:
+       case IOMMU_DOMAIN_DMA_FQ:
        case IOMMU_DOMAIN_UNMANAGED:
                dmar_domain = alloc_domain(0);
                if (!dmar_domain) {
@@ -5197,12 +5198,8 @@ static void intel_iommu_release_device(struct device *dev)
 
 static void intel_iommu_probe_finalize(struct device *dev)
 {
-       struct iommu_domain *domain = iommu_get_domain_for_dev(dev);
-
-       if (domain && domain->type == IOMMU_DOMAIN_DMA)
-               iommu_setup_dma_ops(dev, 0, U64_MAX);
-       else
-               set_dma_ops(dev, NULL);
+       set_dma_ops(dev, NULL);
+       iommu_setup_dma_ops(dev, 0, U64_MAX);
 }
 
 static void intel_iommu_get_resv_regions(struct device *device,