DPU_REG_WRITE(&ctx->hw, CTL_START, 0x1);
 }
 
+static inline bool dpu_hw_ctl_is_started(struct dpu_hw_ctl *ctx)
+{
+       return !!(DPU_REG_READ(&ctx->hw, CTL_START) & BIT(0));
+}
+
 static inline void dpu_hw_ctl_trigger_pending(struct dpu_hw_ctl *ctx)
 {
        trace_dpu_hw_ctl_trigger_prepare(ctx->pending_flush_mask,
        ops->get_pending_flush = dpu_hw_ctl_get_pending_flush;
        ops->get_flush_register = dpu_hw_ctl_get_flush_register;
        ops->trigger_start = dpu_hw_ctl_trigger_start;
+       ops->is_started = dpu_hw_ctl_is_started;
        ops->trigger_pending = dpu_hw_ctl_trigger_pending;
        ops->reset = dpu_hw_ctl_reset_control;
        ops->wait_reset_status = dpu_hw_ctl_wait_reset_status;
 
         */
        void (*trigger_start)(struct dpu_hw_ctl *ctx);
 
+       /**
+        * check if the ctl is started
+        * @ctx       : ctl path ctx pointer
+        * @Return: true if started, false if stopped
+        */
+       bool (*is_started)(struct dpu_hw_ctl *ctx);
+
        /**
         * kickoff prepare is in progress hw operation for sw
         * controlled interfaces: DSI cmd mode and WB interface