Modifications for 1.2.0:
======================================================================
+* Patch by Scott McNutt / Jun Gu / Stefan Roese, 05 Aug 2002:
+ Support for IBM 440GP Ebony Board (and 440 in general)
+
* Fix unlock_ram_in_cache() problem on PCIPPC2/6 boards
(always invalidate cache after unlocking it)
LIST_4xx=" \
ADCIOP AR405 CANBT CPCI405 \
- CPCI4052 CPCIISER4 CRAYL1 DASA_SIM \
- DU405 ERIC MIP405 OCRTC \
- ORSG PCI405 PIP405 W7OLMC \
- W7OLMG WALNUT405 \
+ CPCI4052 CPCI440 CPCIISER4 CRAYL1 \
+ DASA_SIM DU405 EBONY ERIC \
+ MIP405 OCRTC ORSG PCI405 \
+ PIP405 W7OLMC W7OLMG WALNUT405 \
"
#########################################################################
@./mkconfig $(@:_config=) ppc ppc4xx cpci405 esd
@echo "BOARD_REVISION = $(@:_config=)" >>include/config.mk
+CPCI440_config: unconfig
+ @./mkconfig $(@:_config=) ppc ppc4xx cpci440 esd
+
CPCIISER4_config: unconfig
@./mkconfig $(@:_config=) ppc ppc4xx cpciiser4 esd
DU405_config: unconfig
@./mkconfig $(@:_config=) ppc ppc4xx du405 esd
+EBONY_config:unconfig
+ @./mkconfig $(@:_config=) ppc ppc4xx ebony
+
ERIC_config:unconfig
@./mkconfig $(@:_config=) ppc ppc4xx eric
--- /dev/null
+#
+# (C) Copyright 2002
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = lib$(BOARD).a
+
+OBJS = $(BOARD).o flash.o
+SOBJS = init.o
+
+$(LIB): $(OBJS) $(SOBJS)
+ $(AR) crv $@ $^
+
+clean:
+ rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+ $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################
--- /dev/null
+#
+# (C) Copyright 2002
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# esd ADCIOP boards
+#
+
+#TEXT_BASE = 0xFFFE0000
+
+ifeq ($(ramsym),1)
+TEXT_BASE = 0x07FD0000
+else
+TEXT_BASE = 0xFFF80000
+endif
+
+PLATFORM_CPPFLAGS += -DCONFIG_440=1
+
+ifeq ($(debug),1)
+PLATFORM_CPPFLAGS += -DDEBUG
+endif
+
+ifeq ($(dbcr),1)
+PLATFORM_CPPFLAGS += -DCFG_INIT_DBCR=0x8cff0000
+endif
--- /dev/null
+/*
+ * Copyright (C) 2002 Scott McNutt <smcnutt@artesyncp.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+
+#include <ppcboot.h>
+#include "ebony.h"
+#include <asm/processor.h>
+
+
+long int fixed_sdram( void );
+
+int board_pre_init (void)
+{
+ uint reg;
+
+ /*--------------------------------------------------------------------
+ * Setup the external bus controller/chip selects
+ *-------------------------------------------------------------------*/
+ mtdcr( ebccfga, xbcfg );
+ reg = mfdcr( ebccfgd );
+ mtdcr( ebccfgd, reg | 0x04000000 ); /* Set ATC */
+
+ mtebc( pb0ap, 0x9b015480 ); /* FLASH/SRAM */
+ mtebc( pb0cr, 0xfff18000 ); /* BAS=0xfff 1MB R/W 8-bit */
+ mtebc( pb1ap, 0x02815480 ); /* NVRAM/RTC */
+ mtebc( pb1cr, 0x48018000 ); /* BA=0x480 1MB R/W 8-bit */
+ mtebc( pb2ap, 0x9b015480 ); /* 4MB FLASH */
+ mtebc( pb2cr, 0xff858000 ); /* BAS=0xff8 4MB R/W 8-bit */
+ mtebc( pb7ap, 0x01015280 ); /* FPGA registers */
+ mtebc( pb7cr, 0x48318000 ); /* BA=0x483 1MB R/W 8-bit */
+
+ /*--------------------------------------------------------------------
+ * Setup the interrupt controller polarities, triggers, etc.
+ *-------------------------------------------------------------------*/
+ mtdcr( uic0sr, 0xffffffff ); /* clear all */
+ mtdcr( uic0er, 0x00000000 ); /* disable all */
+ mtdcr( uic0cr, 0x00000009 ); /* SMI & UIC1 crit are critical */
+ mtdcr( uic0pr, 0xfffffe13 ); /* per ref-board manual */
+ mtdcr( uic0tr, 0x01c00008 ); /* per ref-board manual */
+ mtdcr( uic0vr, 0x00000001 ); /* int31 highest, base=0x000 */
+ mtdcr( uic0sr, 0xffffffff ); /* clear all */
+
+ mtdcr( uic1sr, 0xffffffff ); /* clear all */
+ mtdcr( uic1er, 0x00000000 ); /* disable all */
+ mtdcr( uic1cr, 0x00000000 ); /* all non-critical */
+ mtdcr( uic1pr, 0xffffe0ff ); /* per ref-board manual */
+ mtdcr( uic1tr, 0x00ffc000 ); /* per ref-board manual */
+ mtdcr( uic1vr, 0x00000001 ); /* int31 highest, base=0x000 */
+ mtdcr( uic1sr, 0xffffffff ); /* clear all */
+
+ return 0;
+}
+
+
+
+int checkboard (void)
+{
+ sys_info_t sysinfo;
+ get_sys_info(&sysinfo);
+
+ printf("IBM 440GP Evaluation Board (Ebony)\n");
+ printf("\tVCO: %lu MHz\n", sysinfo.freqVCOMhz/1000000);
+ printf("\tCPU: %lu MHz\n", sysinfo.freqProcessor/1000000);
+ printf("\tPLB: %lu MHz\n", sysinfo.freqPLB/1000000);
+ printf("\tOPB: %lu MHz\n", sysinfo.freqOPB/1000000);
+ printf("\tEPB: %lu MHz\n", sysinfo.freqEPB/1000000);
+ return (0);
+}
+
+
+long int initdram (int board_type)
+{
+ long dram_size = 0;
+#if defined(CONFIG_SPD_EEPROM)
+ dram_size = spd_sdram();
+#else
+ dram_size = fixed_sdram();
+#endif
+ return dram_size;
+}
+
+
+#if defined(CFG_DRAM_TEST)
+int testdram(void)
+{
+ uint *pstart = (uint *)0x00000000;
+ uint *pend = (uint *)0x08000000;
+ uint *p;
+
+ for( p = pstart; p < pend; p++ )
+ *p = 0xaaaaaaaa;
+
+ for( p = pstart; p < pend; p++ )
+ {
+ if( *p != 0xaaaaaaaa )
+ {
+ printf("SDRAM test fails at: %08x\n", (uint)p );
+ return 1;
+ }
+ }
+
+ for( p = pstart; p < pend; p++ )
+ *p = 0x55555555;
+
+ for( p = pstart; p < pend; p++ )
+ {
+ if( *p != 0x55555555 )
+ {
+ printf("SDRAM test fails at: %08x\n", (uint)p );
+ return 1;
+ }
+ }
+ return 0;
+}
+#endif
+
+#if !defined(CONFIG_SPD_EEPROM)
+/*************************************************************************
+ * fixed sdram init -- doesn't use serial presence detect.
+ *
+ * Assumes: 128 MB, non-ECC, non-registered
+ * PLB @ 133 MHz
+ *
+ ************************************************************************/
+long int fixed_sdram( void )
+{
+ uint reg;
+ /*--------------------------------------------------------------------
+ * Setup some default
+ *------------------------------------------------------------------*/
+ mtsdram( mem_uabba, 0x00000000 ); /* ubba=0 (default) */
+ mtsdram( mem_slio, 0x00000000 ); /* rdre=0 wrre=0 rarw=0 */
+ mtsdram( mem_devopt,0x00000000 ); /* dll=0 ds=0 (normal) */
+ mtsdram( mem_wddctr,0x00000000 ); /* wrcp=0 dcd=0 */
+ mtsdram( mem_clktr, 0x40000000 ); /* clkp=1 (90 deg wr) dcdt=0 */
+
+ /*--------------------------------------------------------------------
+ * Setup for board-specific specific mem
+ *------------------------------------------------------------------*/
+ /*
+ * Following for CAS Latency = 2.5 @ 133 MHz PLB
+ */
+ mtsdram( mem_b0cr, 0x000a4001 );/* SDBA=0x000 128MB, Mode 3, enabled*/
+ mtsdram( mem_tr0, 0x410a4012 );/* WR=2 WD=1 CL=2.5 PA=3 CP=4 LD=2 */
+ /* RA=10 RD=3 */
+ mtsdram( mem_tr1, 0x8080082f );/* SS=T2 SL=STAGE 3 CD=1 CT=0x02f */
+ mtsdram( mem_rtr, 0x08200000 );/* Rate 15.625 ns @ 133 MHz PLB */
+ mtsdram( mem_cfg1, 0x00000000 );/* Self-refresh exit, disable PM */
+ udelay( 400 ); /* Delay 200 usecs (min) */
+
+ /*--------------------------------------------------------------------
+ * Enable the controller, then wait for DCEN to complete
+ *------------------------------------------------------------------*/
+ mtsdram( mem_cfg0, 0x86000000 );/* DCEN=1, PMUD=1, 64-bit */
+ for(;;)
+ {
+ mfsdram( mem_mcsts, reg );
+ if( reg & 0x80000000 )
+ break;
+ }
+
+ return( 128 * 1024 * 1024 ); /* 128 MB */
+}
+#endif /* !defined(CONFIG_SPD_EEPROM) */
--- /dev/null
+/*
+ * (C) Copyright 2002
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/****************************************************************************
+ * FLASH Memory Map as used by TQ Monitor:
+ *
+ * Start Address Length
+ * +-----------------------+ 0x4000_0000 Start of Flash -----------------
+ * | MON8xx code | 0x4000_0100 Reset Vector
+ * +-----------------------+ 0x400?_????
+ * | (unused) |
+ * +-----------------------+ 0x4001_FF00
+ * | Ethernet Addresses | 0x78
+ * +-----------------------+ 0x4001_FF78
+ * | (Reserved for MON8xx) | 0x44
+ * +-----------------------+ 0x4001_FFBC
+ * | Lock Address | 0x04
+ * +-----------------------+ 0x4001_FFC0 ^
+ * | Hardware Information | 0x40 | MON8xx
+ * +=======================+ 0x4002_0000 (sector border) -----------------
+ * | Autostart Header | | Applications
+ * | ... | v
+ *
+ *****************************************************************************/
--- /dev/null
+/*
+ * (C) Copyright 2002
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2002 Jun Gu <jung@artesyncp.com>
+ * Add support for Am29F016D and dynamic switch setting.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * Modified 4/5/2001
+ * Wait for completion of each sector erase command issued
+ * 4/5/2001
+ * Chris Hallinan - DS4.COM, Inc. - clh@net1plus.com
+ */
+
+#include <ppcboot.h>
+#include <ppc4xx.h>
+#include <asm/processor.h>
+
+#define BOOT_SMALL_FLASH 32 /* 00100000 */
+#define FLASH_ONBD_N 2 /* 00000010 */
+#define FLASH_SRAM_SEL 1 /* 00000001 */
+
+#define BOOT_SMALL_FLASH_VAL 4
+#define FLASH_ONBD_N_VAL 2
+#define FLASH_SRAM_SEL_VAL 1
+
+
+flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
+
+static unsigned long flash_addr_table[8][CFG_MAX_FLASH_BANKS] = {
+ {0xffc00000, 0xffe00000, 0xff880000}, /* 0:000: configuraton 3 */
+ {0xffc00000, 0xffe00000, 0xff800000}, /* 1:001: configuraton 4 */
+ {0xffc00000, 0xffe00000, 0x00000000}, /* 2:010: configuraton 7 */
+ {0xffc00000, 0xffe00000, 0x00000000}, /* 3:011: configuraton 8 */
+ {0xff800000, 0xffa00000, 0xfff80000}, /* 4:100: configuraton 1 */
+ {0xff800000, 0xffa00000, 0xfff00000}, /* 5:101: configuraton 2 */
+ {0xffc00000, 0xffe00000, 0x00000000}, /* 6:110: configuraton 5 */
+ {0xffc00000, 0xffe00000, 0x00000000} /* 7:111: configuraton 6 */
+};
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size (vu_long *addr, flash_info_t *info);
+static int write_word (flash_info_t *info, ulong dest, ulong data);
+static void flash_get_offsets (ulong base, flash_info_t *info);
+
+#ifdef CONFIG_ADCIOP
+#define ADDR0 0x0aa9
+#define ADDR1 0x0556
+#define FLASH_WORD_SIZE unsigned char
+#endif
+
+#ifdef CONFIG_CPCI405
+#define ADDR0 0x5555
+#define ADDR1 0x2aaa
+#define FLASH_WORD_SIZE unsigned short
+#endif
+
+#ifdef CONFIG_WALNUT405
+#define ADDR0 0x5555
+#define ADDR1 0x2aaa
+#define FLASH_WORD_SIZE unsigned char
+#endif
+
+#ifdef CONFIG_EBONY
+#define ADDR0 0x5555
+#define ADDR1 0x2aaa
+#define FLASH_WORD_SIZE unsigned char
+#endif
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init (void) {
+ unsigned long total_b = 0;
+ unsigned long size_b[CFG_MAX_FLASH_BANKS];
+ unsigned char * fpga_base = (unsigned char *)CFG_FPGA_BASE;
+ unsigned char switch_status;
+ unsigned short index = 0;
+ int i;
+
+
+ /* read FPGA base register FPGA_REG0 */
+ switch_status = *fpga_base;
+
+ /* check the bitmap of switch status */
+ if (switch_status & BOOT_SMALL_FLASH) {
+ index += BOOT_SMALL_FLASH_VAL;
+ }
+ if (switch_status & FLASH_ONBD_N) {
+ index += FLASH_ONBD_N_VAL;
+ }
+ if (switch_status & FLASH_SRAM_SEL) {
+ index += FLASH_SRAM_SEL_VAL;
+ }
+
+#if 0
+ printf("Index: %d\n", index);
+#endif
+
+ /* Init: no FLASHes known */
+ for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) {
+ flash_info[i].flash_id = FLASH_UNKNOWN;
+ flash_info[i].sector_count = -1;
+ flash_info[i].size = 0;
+
+ /* check whether the address is 0 */
+ if (flash_addr_table[index][i] == 0) {
+ continue;
+ }
+
+ /* call flash_get_size() to initialize sector address */
+ size_b[i] = flash_get_size(
+ (vu_long *)flash_addr_table[index][i], &flash_info[i]);
+ flash_info[i].size = size_b[i];
+ if (flash_info[i].flash_id == FLASH_UNKNOWN) {
+ printf ("## Unknown FLASH on Bank %d - Size = 0x%08lx = %ld MB\n",
+ i, size_b[i], size_b[i]<<20);
+ flash_info[i].sector_count = -1;
+ flash_info[i].size = 0;
+ }
+
+ total_b += flash_info[i].size;
+ }
+
+ return total_b;
+}
+
+
+
+/*-----------------------------------------------------------------------
+ */
+static void flash_get_offsets (ulong base, flash_info_t *info)
+{
+ int i;
+
+ /* set up sector start address table */
+ if (((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) ||
+ (info->flash_id == FLASH_AM040) ||
+ (info->flash_id == FLASH_AMD016)) {
+ for (i = 0; i < info->sector_count; i++)
+ info->start[i] = base + (i * 0x00010000);
+ } else {
+ if (info->flash_id & FLASH_BTYPE) {
+ /* set sector offsets for bottom boot block type */
+ info->start[0] = base + 0x00000000;
+ info->start[1] = base + 0x00004000;
+ info->start[2] = base + 0x00006000;
+ info->start[3] = base + 0x00008000;
+ for (i = 4; i < info->sector_count; i++) {
+ info->start[i] = base + (i * 0x00010000) - 0x00030000;
+ }
+ } else {
+ /* set sector offsets for top boot block type */
+ i = info->sector_count - 1;
+ info->start[i--] = base + info->size - 0x00004000;
+ info->start[i--] = base + info->size - 0x00006000;
+ info->start[i--] = base + info->size - 0x00008000;
+ for (; i >= 0; i--) {
+ info->start[i] = base + i * 0x00010000;
+ }
+ }
+ }
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info (flash_info_t *info)
+{
+ int i;
+ int k;
+ int size;
+ int erased;
+ volatile unsigned long *flash;
+
+ if (info->flash_id == FLASH_UNKNOWN) {
+ printf ("missing or unknown FLASH type\n");
+ return;
+ }
+
+ switch (info->flash_id & FLASH_VENDMASK) {
+ case FLASH_MAN_AMD: printf ("AMD "); break;
+ case FLASH_MAN_FUJ: printf ("FUJITSU "); break;
+ case FLASH_MAN_SST: printf ("SST "); break;
+ default: printf ("Unknown Vendor "); break;
+ }
+
+ switch (info->flash_id & FLASH_TYPEMASK) {
+ case FLASH_AMD016: printf ("AM29F016D (16 Mbit, uniform sector size)\n");
+ break;
+ case FLASH_AM040: printf ("AM29F040 (512 Kbit, uniform sector size)\n");
+ break;
+ case FLASH_AM400B: printf ("AM29LV400B (4 Mbit, bottom boot sect)\n");
+ break;
+ case FLASH_AM400T: printf ("AM29LV400T (4 Mbit, top boot sector)\n");
+ break;
+ case FLASH_AM800B: printf ("AM29LV800B (8 Mbit, bottom boot sect)\n");
+ break;
+ case FLASH_AM800T: printf ("AM29LV800T (8 Mbit, top boot sector)\n");
+ break;
+ case FLASH_AM160B: printf ("AM29LV160B (16 Mbit, bottom boot sect)\n");
+ break;
+ case FLASH_AM160T: printf ("AM29LV160T (16 Mbit, top boot sector)\n");
+ break;
+ case FLASH_AM320B: printf ("AM29LV320B (32 Mbit, bottom boot sect)\n");
+ break;
+ case FLASH_AM320T: printf ("AM29LV320T (32 Mbit, top boot sector)\n");
+ break;
+ case FLASH_SST800A: printf ("SST39LF/VF800 (8 Mbit, uniform sector size)\n");
+ break;
+ case FLASH_SST160A: printf ("SST39LF/VF160 (16 Mbit, uniform sector size)\n");
+ break;
+ default: printf ("Unknown Chip Type\n");
+ break;
+ }
+
+ printf (" Size: %ld KB in %d Sectors\n",
+ info->size >> 10, info->sector_count);
+
+ printf (" Sector Start Addresses:");
+ for (i=0; i<info->sector_count; ++i) {
+ /*
+ * Check if whole sector is erased
+ */
+ if (i != (info->sector_count-1))
+ size = info->start[i+1] - info->start[i];
+ else
+ size = info->start[0] + info->size - info->start[i];
+ erased = 1;
+ flash = (volatile unsigned long *)info->start[i];
+ size = size >> 2; /* divide by 4 for longword access */
+ for (k=0; k<size; k++)
+ {
+ if (*flash++ != 0xffffffff)
+ {
+ erased = 0;
+ break;
+ }
+ }
+
+ if ((i % 5) == 0)
+ printf ("\n ");
+#if 0 /* test-only */
+ printf (" %08lX%s",
+ info->start[i],
+ info->protect[i] ? " (RO)" : " "
+#else
+ printf (" %08lX%s%s",
+ info->start[i],
+ erased ? " E" : " ",
+ info->protect[i] ? "RO " : " "
+#endif
+ );
+ }
+ printf ("\n");
+ return;
+ }
+
+/*-----------------------------------------------------------------------
+ */
+
+
+/*-----------------------------------------------------------------------
+ */
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+ static ulong flash_get_size (vu_long *addr, flash_info_t *info)
+ {
+ short i;
+ FLASH_WORD_SIZE value;
+ ulong base = (ulong)addr;
+ volatile FLASH_WORD_SIZE *addr2 = (FLASH_WORD_SIZE *)addr;
+
+ /* Write auto select command: read Manufacturer ID */
+ addr2[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA;
+ addr2[ADDR1] = (FLASH_WORD_SIZE)0x00550055;
+ addr2[ADDR0] = (FLASH_WORD_SIZE)0x00900090;
+
+#ifdef CONFIG_ADCIOP
+ value = addr2[2];
+#else
+ value = addr2[0];
+#endif
+
+#if 0
+ printf("\nFLASH MANUFACT: %x\n", value);
+#endif
+ switch (value) {
+ case (FLASH_WORD_SIZE)AMD_MANUFACT:
+ info->flash_id = FLASH_MAN_AMD;
+ break;
+ case (FLASH_WORD_SIZE)FUJ_MANUFACT:
+ info->flash_id = FLASH_MAN_FUJ;
+ break;
+ case (FLASH_WORD_SIZE)SST_MANUFACT:
+ info->flash_id = FLASH_MAN_SST;
+ break;
+ default:
+ info->flash_id = FLASH_UNKNOWN;
+ info->sector_count = 0;
+ info->size = 0;
+ return (0); /* no or unknown flash */
+ }
+
+#ifdef CONFIG_ADCIOP
+ value = addr2[0]; /* device ID */
+ // printf("\ndev_code=%x\n", value);
+#else
+ value = addr2[1]; /* device ID */
+#endif
+
+#if 0
+ printf("\nFLASH DEVICEID: %x\n", value);
+#endif
+ switch (value) {
+ case (FLASH_WORD_SIZE)AMD_ID_F016D:
+ info->flash_id += FLASH_AMD016;
+ info->sector_count = 32;
+ info->size = 0x00200000;
+ break; /* => 2 MB */
+ case (FLASH_WORD_SIZE)AMD_ID_F040B:
+ info->flash_id += FLASH_AM040;
+ info->sector_count = 8;
+ info->size = 0x0080000; /* => 512 ko */
+ break;
+ case (FLASH_WORD_SIZE)AMD_ID_LV400T:
+ info->flash_id += FLASH_AM400T;
+ info->sector_count = 11;
+ info->size = 0x00080000;
+ break; /* => 0.5 MB */
+
+ case (FLASH_WORD_SIZE)AMD_ID_LV400B:
+ info->flash_id += FLASH_AM400B;
+ info->sector_count = 11;
+ info->size = 0x00080000;
+ break; /* => 0.5 MB */
+
+ case (FLASH_WORD_SIZE)AMD_ID_LV800T:
+ info->flash_id += FLASH_AM800T;
+ info->sector_count = 19;
+ info->size = 0x00100000;
+ break; /* => 1 MB */
+
+ case (FLASH_WORD_SIZE)AMD_ID_LV800B:
+ info->flash_id += FLASH_AM800B;
+ info->sector_count = 19;
+ info->size = 0x00100000;
+ break; /* => 1 MB */
+
+ case (FLASH_WORD_SIZE)AMD_ID_LV160T:
+ info->flash_id += FLASH_AM160T;
+ info->sector_count = 35;
+ info->size = 0x00200000;
+ break; /* => 2 MB */
+
+ case (FLASH_WORD_SIZE)AMD_ID_LV160B:
+ info->flash_id += FLASH_AM160B;
+ info->sector_count = 35;
+ info->size = 0x00200000;
+ break; /* => 2 MB */
+#if 0 /* enable when device IDs are available */
+ case (FLASH_WORD_SIZE)AMD_ID_LV320T:
+ info->flash_id += FLASH_AM320T;
+ info->sector_count = 67;
+ info->size = 0x00400000;
+ break; /* => 4 MB */
+
+ case (FLASH_WORD_SIZE)AMD_ID_LV320B:
+ info->flash_id += FLASH_AM320B;
+ info->sector_count = 67;
+ info->size = 0x00400000;
+ break; /* => 4 MB */
+#endif
+ case (FLASH_WORD_SIZE)SST_ID_xF800A:
+ info->flash_id += FLASH_SST800A;
+ info->sector_count = 16;
+ info->size = 0x00100000;
+ break; /* => 1 MB */
+
+ case (FLASH_WORD_SIZE)SST_ID_xF160A:
+ info->flash_id += FLASH_SST160A;
+ info->sector_count = 32;
+ info->size = 0x00200000;
+ break; /* => 2 MB */
+
+ default:
+ info->flash_id = FLASH_UNKNOWN;
+ return (0); /* => no or unknown flash */
+
+ }
+
+ /* set up sector start address table */
+ if (((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) ||
+ (info->flash_id == FLASH_AM040) ||
+ (info->flash_id == FLASH_AMD016)) {
+ for (i = 0; i < info->sector_count; i++)
+ info->start[i] = base + (i * 0x00010000);
+ } else {
+ if (info->flash_id & FLASH_BTYPE) {
+ /* set sector offsets for bottom boot block type */
+ info->start[0] = base + 0x00000000;
+ info->start[1] = base + 0x00004000;
+ info->start[2] = base + 0x00006000;
+ info->start[3] = base + 0x00008000;
+ for (i = 4; i < info->sector_count; i++) {
+ info->start[i] = base + (i * 0x00010000) - 0x00030000;
+ }
+ } else {
+ /* set sector offsets for top boot block type */
+ i = info->sector_count - 1;
+ info->start[i--] = base + info->size - 0x00004000;
+ info->start[i--] = base + info->size - 0x00006000;
+ info->start[i--] = base + info->size - 0x00008000;
+ for (; i >= 0; i--) {
+ info->start[i] = base + i * 0x00010000;
+ }
+ }
+ }
+
+ /* check for protected sectors */
+ for (i = 0; i < info->sector_count; i++) {
+ /* read sector protection at sector address, (A7 .. A0) = 0x02 */
+ /* D0 = 1 if protected */
+#ifdef CONFIG_ADCIOP
+ addr2 = (volatile FLASH_WORD_SIZE *)(info->start[i]);
+ info->protect[i] = addr2[4] & 1;
+#else
+ addr2 = (volatile FLASH_WORD_SIZE *)(info->start[i]);
+ if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST)
+ info->protect[i] = 0;
+ else
+ info->protect[i] = addr2[2] & 1;
+#endif
+ }
+
+ /*
+ * Prevent writes to uninitialized FLASH.
+ */
+ if (info->flash_id != FLASH_UNKNOWN) {
+#if 0 /* test-only */
+#ifdef CONFIG_ADCIOP
+ addr2 = (volatile unsigned char *)info->start[0];
+ addr2[ADDR0] = 0xAA;
+ addr2[ADDR1] = 0x55;
+ addr2[ADDR0] = 0xF0; /* reset bank */
+#else
+ addr2 = (FLASH_WORD_SIZE *)info->start[0];
+ *addr2 = (FLASH_WORD_SIZE)0x00F000F0; /* reset bank */
+#endif
+#else /* test-only */
+ addr2 = (FLASH_WORD_SIZE *)info->start[0];
+ *addr2 = (FLASH_WORD_SIZE)0x00F000F0; /* reset bank */
+#endif /* test-only */
+ }
+
+ return (info->size);
+ }
+
+ int wait_for_DQ7(flash_info_t *info, int sect)
+ {
+ ulong start, now, last;
+ volatile FLASH_WORD_SIZE *addr = (FLASH_WORD_SIZE *)(info->start[sect]);
+
+ start = get_timer (0);
+ last = start;
+ while ((addr[0] & (FLASH_WORD_SIZE)0x00800080) != (FLASH_WORD_SIZE)0x00800080) {
+ if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+ printf ("Timeout\n");
+ return -1;
+ }
+ /* show that we're waiting */
+ if ((now - last) > 1000) { /* every second */
+ putc ('.');
+ last = now;
+ }
+ }
+ return 0;
+ }
+
+/*-----------------------------------------------------------------------
+ */
+
+ int flash_erase (flash_info_t *info, int s_first, int s_last)
+ {
+ volatile FLASH_WORD_SIZE *addr = (FLASH_WORD_SIZE *)(info->start[0]);
+ volatile FLASH_WORD_SIZE *addr2;
+ int flag, prot, sect, l_sect;
+ int i;
+
+ if ((s_first < 0) || (s_first > s_last)) {
+ if (info->flash_id == FLASH_UNKNOWN) {
+ printf ("- missing\n");
+ } else {
+ printf ("- no sectors to erase\n");
+ }
+ return 1;
+ }
+
+ if (info->flash_id == FLASH_UNKNOWN) {
+ printf ("Can't erase unknown flash type - aborted\n");
+ return 1;
+ }
+
+ prot = 0;
+ for (sect=s_first; sect<=s_last; ++sect) {
+ if (info->protect[sect]) {
+ prot++;
+ }
+ }
+
+ if (prot) {
+ printf ("- Warning: %d protected sectors will not be erased!\n",
+ prot);
+ } else {
+ printf ("\n");
+ }
+
+ l_sect = -1;
+
+ /* Disable interrupts which might cause a timeout here */
+ flag = disable_interrupts();
+
+ /* Start erase on unprotected sectors */
+ for (sect = s_first; sect<=s_last; sect++) {
+ if (info->protect[sect] == 0) { /* not protected */
+ addr2 = (FLASH_WORD_SIZE *)(info->start[sect]);
+ printf("Erasing sector %p\n", addr2); // CLH
+
+ if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) {
+ addr[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA;
+ addr[ADDR1] = (FLASH_WORD_SIZE)0x00550055;
+ addr[ADDR0] = (FLASH_WORD_SIZE)0x00800080;
+ addr[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA;
+ addr[ADDR1] = (FLASH_WORD_SIZE)0x00550055;
+ addr2[0] = (FLASH_WORD_SIZE)0x00500050; /* block erase */
+ for (i=0; i<50; i++)
+ udelay(1000); /* wait 1 ms */
+ } else {
+ addr[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA;
+ addr[ADDR1] = (FLASH_WORD_SIZE)0x00550055;
+ addr[ADDR0] = (FLASH_WORD_SIZE)0x00800080;
+ addr[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA;
+ addr[ADDR1] = (FLASH_WORD_SIZE)0x00550055;
+ addr2[0] = (FLASH_WORD_SIZE)0x00300030; /* sector erase */
+ }
+ l_sect = sect;
+ /*
+ * Wait for each sector to complete, it's more
+ * reliable. According to AMD Spec, you must
+ * issue all erase commands within a specified
+ * timeout. This has been seen to fail, especially
+ * if printf()s are included (for debug)!!
+ */
+ wait_for_DQ7(info, sect);
+ }
+ }
+
+ /* re-enable interrupts if necessary */
+ if (flag)
+ enable_interrupts();
+
+ /* wait at least 80us - let's wait 1 ms */
+ udelay (1000);
+
+#if 0
+ /*
+ * We wait for the last triggered sector
+ */
+ if (l_sect < 0)
+ goto DONE;
+ wait_for_DQ7(info, l_sect);
+
+ DONE:
+#endif
+ /* reset to read mode */
+ addr = (FLASH_WORD_SIZE *)info->start[0];
+ addr[0] = (FLASH_WORD_SIZE)0x00F000F0; /* reset bank */
+
+ printf (" done\n");
+ return 0;
+ }
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+
+ int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+ {
+ ulong cp, wp, data;
+ int i, l, rc;
+
+ wp = (addr & ~3); /* get lower word aligned address */
+
+ /*
+ * handle unaligned start bytes
+ */
+ if ((l = addr - wp) != 0) {
+ data = 0;
+ for (i=0, cp=wp; i<l; ++i, ++cp) {
+ data = (data << 8) | (*(uchar *)cp);
+ }
+ for (; i<4 && cnt>0; ++i) {
+ data = (data << 8) | *src++;
+ --cnt;
+ ++cp;
+ }
+ for (; cnt==0 && i<4; ++i, ++cp) {
+ data = (data << 8) | (*(uchar *)cp);
+ }
+
+ if ((rc = write_word(info, wp, data)) != 0) {
+ return (rc);
+ }
+ wp += 4;
+ }
+
+ /*
+ * handle word aligned part
+ */
+ while (cnt >= 4) {
+ data = 0;
+ for (i=0; i<4; ++i) {
+ data = (data << 8) | *src++;
+ }
+ if ((rc = write_word(info, wp, data)) != 0) {
+ return (rc);
+ }
+ wp += 4;
+ cnt -= 4;
+ }
+
+ if (cnt == 0) {
+ return (0);
+ }
+
+ /*
+ * handle unaligned tail bytes
+ */
+ data = 0;
+ for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
+ data = (data << 8) | *src++;
+ --cnt;
+ }
+ for (; i<4; ++i, ++cp) {
+ data = (data << 8) | (*(uchar *)cp);
+ }
+
+ return (write_word(info, wp, data));
+ }
+
+/*-----------------------------------------------------------------------
+ * Write a word to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+ static int write_word (flash_info_t * info, ulong dest, ulong data)
+ {
+ volatile FLASH_WORD_SIZE *addr2 = (FLASH_WORD_SIZE *) (info->start[0]);
+ volatile FLASH_WORD_SIZE *dest2 = (FLASH_WORD_SIZE *) dest;
+ volatile FLASH_WORD_SIZE *data2 = (FLASH_WORD_SIZE *) & data;
+ ulong start;
+ int i;
+
+ /* Check if Flash is (sufficiently) erased */
+ if ((*((volatile FLASH_WORD_SIZE *) dest) &
+ (FLASH_WORD_SIZE) data) != (FLASH_WORD_SIZE) data) {
+ return (2);
+ }
+
+ for (i = 0; i < 4 / sizeof (FLASH_WORD_SIZE); i++) {
+ int flag;
+
+ /* Disable interrupts which might cause a timeout here */
+ flag = disable_interrupts ();
+
+ addr2[ADDR0] = (FLASH_WORD_SIZE) 0x00AA00AA;
+ addr2[ADDR1] = (FLASH_WORD_SIZE) 0x00550055;
+ addr2[ADDR0] = (FLASH_WORD_SIZE) 0x00A000A0;
+
+ dest2[i] = data2[i];
+
+ /* re-enable interrupts if necessary */
+ if (flag)
+ enable_interrupts ();
+
+ /* data polling for D7 */
+ start = get_timer (0);
+ while ((dest2[i] & (FLASH_WORD_SIZE) 0x00800080) !=
+ (data2[i] & (FLASH_WORD_SIZE) 0x00800080)) {
+
+ if (get_timer (start) > CFG_FLASH_WRITE_TOUT) {
+ return (1);
+ }
+ }
+ }
+
+ return (0);
+ }
+
+/*-----------------------------------------------------------------------
+ */
--- /dev/null
+/*
+* Copyright (C) 2002 Scott McNutt <smcnutt@artesyncp.com>
+*
+* See file CREDITS for list of people who contributed to this
+* project.
+*
+* This program is free software; you can redistribute it and/or
+* modify it under the terms of the GNU General Public License as
+* published by the Free Software Foundation; either version 2 of
+* the License, or (at your option) any later version.
+*
+* This program is distributed in the hope that it will be useful,
+* but WITHOUT ANY WARRANTY; without even the implied warranty of
+* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+* GNU General Public License for more details.
+*
+* You should have received a copy of the GNU General Public License
+* along with this program; if not, write to the Free Software
+* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+* MA 02111-1307 USA
+*/
+
+#include <ppc_asm.tmpl>
+#include <config.h>
+
+/* General */
+#define TLB_VALID 0x00000200
+
+/* Supported page sizes */
+
+#define SZ_1K 0x00000000
+#define SZ_4K 0x00000010
+#define SZ_16K 0x00000020
+#define SZ_64K 0x00000030
+#define SZ_256K 0x00000040
+#define SZ_1M 0x00000050
+#define SZ_16M 0x00000070
+#define SZ_256M 0x00000090
+
+/* Storage attributes */
+#define SA_W 0x00000800 /* Write-through */
+#define SA_I 0x00000400 /* Caching inhibited */
+#define SA_M 0x00000200 /* Memory coherence */
+#define SA_G 0x00000100 /* Guarded */
+#define SA_E 0x00000080 /* Endian */
+
+/* Access control */
+#define AC_X 0x00000024 /* Execute */
+#define AC_W 0x00000012 /* Write */
+#define AC_R 0x00000009 /* Read */
+
+/* Some handy macros */
+
+#define EPN(e) ((e) & 0xfffffc00)
+#define TLB0(epn,sz) ( (EPN((epn)) | (sz) | TLB_VALID ) )
+#define TLB1(rpn,erpn) ( ((rpn)&0xfffffc00) | (erpn) )
+#define TLB2(a) ( (a)&0x00000fbf )
+
+#define tlbtab_start\
+ mflr r1 ;\
+ bl 0f ;
+
+#define tlbtab_end\
+ .long 0, 0, 0 ; \
+0: mflr r0 ; \
+ mtlr r1 ; \
+ blr ;
+
+#define tlbentry(epn,sz,rpn,erpn,attr)\
+ .long TLB0(epn,sz),TLB1(rpn,erpn),TLB2(attr)
+
+
+/*************************************************************************/
+/* TLB TABLE
+ *
+ * This table is used by the cpu boot code to setup the initial tlb
+ * entries. Rather than make broad assumptions in the cpu source tree,
+ * this table lets each board set things up however they like.
+ *
+ * Pointer to the table is returned in r1
+ *
+/*************************************************************************/
+
+ .section .bootpg,"ax"
+ .globl tlbtab
+
+tlbtab:
+ tlbtab_start
+ tlbentry( 0xf0000000, SZ_256M, 0xf0000000, 1, AC_R|AC_W|AC_X|SA_G|SA_I)
+ tlbentry( CFG_PERIPHERAL_BASE, SZ_256M, 0x40000000, 1, AC_R|AC_W|SA_G|SA_I)
+ tlbentry( CFG_ISRAM_BASE, SZ_4K, 0x80000000, 0, AC_R|AC_W|AC_X )
+ tlbentry( CFG_ISRAM_BASE + 0x1000, SZ_4K, 0x80001000, 0, AC_R|AC_W|AC_X )
+ tlbentry( CFG_SDRAM_BASE, SZ_256M, 0x00000000, 0, AC_R|AC_W|AC_X )
+ tlbtab_end
+
+
--- /dev/null
+/*
+ * (C) Copyright 2002
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+ __DYNAMIC = 0; */
+SECTIONS
+{
+ .resetvec 0xFFFFFFFC :
+ {
+ *(.resetvec)
+ } = 0xffff
+
+ .bootpg 0xFFFFF000 :
+ {
+ cpu/ppc4xx/start.o (.bootpg)
+ } = 0xffff
+
+ /* Read-only sections, merged into text segment: */
+ . = + SIZEOF_HEADERS;
+ .interp : { *(.interp) }
+ .hash : { *(.hash) }
+ .dynsym : { *(.dynsym) }
+ .dynstr : { *(.dynstr) }
+ .rel.text : { *(.rel.text) }
+ .rela.text : { *(.rela.text) }
+ .rel.data : { *(.rel.data) }
+ .rela.data : { *(.rela.data) }
+ .rel.rodata : { *(.rel.rodata) }
+ .rela.rodata : { *(.rela.rodata) }
+ .rel.got : { *(.rel.got) }
+ .rela.got : { *(.rela.got) }
+ .rel.ctors : { *(.rel.ctors) }
+ .rela.ctors : { *(.rela.ctors) }
+ .rel.dtors : { *(.rel.dtors) }
+ .rela.dtors : { *(.rela.dtors) }
+ .rel.bss : { *(.rel.bss) }
+ .rela.bss : { *(.rela.bss) }
+ .rel.plt : { *(.rel.plt) }
+ .rela.plt : { *(.rela.plt) }
+ .init : { *(.init) }
+ .plt : { *(.plt) }
+ .text :
+ {
+ /* WARNING - the following is hand-optimized to fit within */
+ /* the sector layout of our flash chips! XXX FIXME XXX */
+
+ cpu/ppc4xx/start.o (.text)
+ board/ebony/init.o (.text)
+ cpu/ppc4xx/kgdb.o (.text)
+ cpu/ppc4xx/traps.o (.text)
+ cpu/ppc4xx/interrupts.o (.text)
+ cpu/ppc4xx/serial.o (.text)
+ cpu/ppc4xx/cpu_init.o (.text)
+ cpu/ppc4xx/speed.o (.text)
+ cpu/ppc4xx/405gp_enet.o (.text)
+ common/dlmalloc.o (.text)
+ lib_generic/crc32.o (.text)
+ lib_ppc/extable.o (.text)
+ lib_generic/zlib.o (.text)
+
+/* . = env_offset;*/
+/* common/environment.o(.text)*/
+
+ *(.text)
+ *(.fixup)
+ *(.got1)
+ }
+ _etext = .;
+ PROVIDE (etext = .);
+ .rodata :
+ {
+ *(.rodata)
+ *(.rodata1)
+ }
+ .fini : { *(.fini) } =0
+ .ctors : { *(.ctors) }
+ .dtors : { *(.dtors) }
+
+ /* Read-write section, merged into data segment: */
+ . = (. + 0x00FF) & 0xFFFFFF00;
+ _erotext = .;
+ PROVIDE (erotext = .);
+ .reloc :
+ {
+ *(.got)
+ _GOT2_TABLE_ = .;
+ *(.got2)
+ _FIXUP_TABLE_ = .;
+ *(.fixup)
+ }
+ __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+ __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+ .data :
+ {
+ *(.data)
+ *(.data1)
+ *(.sdata)
+ *(.sdata2)
+ *(.dynamic)
+ CONSTRUCTORS
+ }
+ _edata = .;
+ PROVIDE (edata = .);
+
+ __start___ex_table = .;
+ __ex_table : { *(__ex_table) }
+ __stop___ex_table = .;
+
+ . = ALIGN(256);
+ __init_begin = .;
+ .text.init : { *(.text.init) }
+ .data.init : { *(.data.init) }
+ . = ALIGN(256);
+ __init_end = .;
+
+ __bss_start = .;
+ .bss :
+ {
+ *(.sbss) *(.scommon)
+ *(.dynbss)
+ *(.bss)
+ *(COMMON)
+ }
+ _end = . ;
+ PROVIDE (end = .);
+}
--- /dev/null
+/*
+ * (C) Copyright 2002
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+ __DYNAMIC = 0; */
+SECTIONS
+{
+ /* Read-only sections, merged into text segment: */
+ . = + SIZEOF_HEADERS;
+ .interp : { *(.interp) }
+ .hash : { *(.hash) }
+ .dynsym : { *(.dynsym) }
+ .dynstr : { *(.dynstr) }
+ .rel.text : { *(.rel.text) }
+ .rela.text : { *(.rela.text) }
+ .rel.data : { *(.rel.data) }
+ .rela.data : { *(.rela.data) }
+ .rel.rodata : { *(.rel.rodata) }
+ .rela.rodata : { *(.rela.rodata) }
+ .rel.got : { *(.rel.got) }
+ .rela.got : { *(.rela.got) }
+ .rel.ctors : { *(.rel.ctors) }
+ .rela.ctors : { *(.rela.ctors) }
+ .rel.dtors : { *(.rel.dtors) }
+ .rela.dtors : { *(.rela.dtors) }
+ .rel.bss : { *(.rel.bss) }
+ .rela.bss : { *(.rela.bss) }
+ .rel.plt : { *(.rel.plt) }
+ .rela.plt : { *(.rela.plt) }
+ .init : { *(.init) }
+ .plt : { *(.plt) }
+ .text :
+ {
+ /* WARNING - the following is hand-optimized to fit within */
+ /* the sector layout of our flash chips! XXX FIXME XXX */
+
+ mpc8xx/start.o (.text)
+ common/dlmalloc.o (.text)
+ ppc/vsprintf.o (.text)
+ ppc/crc32.o (.text)
+ ppc/extable.o (.text)
+
+ common/environment.o(.text)
+
+ *(.text)
+ *(.fixup)
+ *(.got1)
+ }
+ _etext = .;
+ PROVIDE (etext = .);
+ .rodata :
+ {
+ *(.rodata)
+ *(.rodata1)
+ }
+ .fini : { *(.fini) } =0
+ .ctors : { *(.ctors) }
+ .dtors : { *(.dtors) }
+
+ /* Read-write section, merged into data segment: */
+ . = (. + 0x0FFF) & 0xFFFFF000;
+ _erotext = .;
+ PROVIDE (erotext = .);
+ .reloc :
+ {
+ *(.got)
+ _GOT2_TABLE_ = .;
+ *(.got2)
+ _FIXUP_TABLE_ = .;
+ *(.fixup)
+ }
+ __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+ __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+ .data :
+ {
+ *(.data)
+ *(.data1)
+ *(.sdata)
+ *(.sdata2)
+ *(.dynamic)
+ CONSTRUCTORS
+ }
+ _edata = .;
+ PROVIDE (edata = .);
+
+ __start___ex_table = .;
+ __ex_table : { *(__ex_table) }
+ __stop___ex_table = .;
+
+ . = ALIGN(4096);
+ __init_begin = .;
+ .text.init : { *(.text.init) }
+ .data.init : { *(.data.init) }
+ . = ALIGN(4096);
+ __init_end = .;
+
+ __bss_start = .;
+ .bss :
+ {
+ *(.sbss) *(.scommon)
+ *(.dynbss)
+ *(.bss)
+ *(COMMON)
+ }
+ _end = . ;
+ PROVIDE (end = .);
+}
+
--- /dev/null
+#
+# (C) Copyright 2002
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = lib$(BOARD).a
+
+OBJS = $(BOARD).o strataflash.o
+SOBJS = init.o
+
+$(LIB): $(OBJS) $(SOBJS)
+ $(AR) crv $@ $^
+
+clean:
+ rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+ $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################
--- /dev/null
+#
+# (C) Copyright 2002
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# esd ADCIOP boards
+#
+
+#TEXT_BASE = 0xFFFE0000
+
+ifeq ($(ramsym),1)
+TEXT_BASE = 0x07FD0000
+else
+TEXT_BASE = 0xFFFC0000
+endif
+
+PLATFORM_CPPFLAGS += -DCONFIG_440=1
+
+ifeq ($(debug),1)
+PLATFORM_CPPFLAGS += -DDEBUG
+endif
+
+ifeq ($(dbcr),1)
+PLATFORM_CPPFLAGS += -DCFG_INIT_DBCR=0x8cff0000
+endif
--- /dev/null
+/*
+ * (C) Copyright 2002
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+
+#include <ppcboot.h>
+#include <asm/processor.h>
+
+
+long int fixed_sdram( void );
+
+int board_pre_init (void)
+{
+ uint reg;
+
+ /*--------------------------------------------------------------------
+ * Setup the external bus controller/chip selects
+ *-------------------------------------------------------------------*/
+ mtdcr( ebccfga, xbcfg );
+ reg = mfdcr( ebccfgd );
+ mtdcr( ebccfgd, reg | 0x04000000 ); /* Set ATC */
+
+ mtebc( pb0ap, 0x92015480 ); /* FLASH/SRAM */
+ mtebc( pb0cr, 0xFF87A000 ); /* BAS=0xff8 8MB R/W 16-bit */
+ /* test-only: other regs still missing... */
+
+ /*--------------------------------------------------------------------
+ * Setup the interrupt controller polarities, triggers, etc.
+ *-------------------------------------------------------------------*/
+ mtdcr( uic0sr, 0xffffffff ); /* clear all */
+ mtdcr( uic0er, 0x00000000 ); /* disable all */
+ mtdcr( uic0cr, 0x00000009 ); /* SMI & UIC1 crit are critical */
+ mtdcr( uic0pr, 0xfffffe13 ); /* per ref-board manual */
+ mtdcr( uic0tr, 0x01c00008 ); /* per ref-board manual */
+ mtdcr( uic0vr, 0x00000001 ); /* int31 highest, base=0x000 */
+ mtdcr( uic0sr, 0xffffffff ); /* clear all */
+
+ mtdcr( uic1sr, 0xffffffff ); /* clear all */
+ mtdcr( uic1er, 0x00000000 ); /* disable all */
+ mtdcr( uic1cr, 0x00000000 ); /* all non-critical */
+ mtdcr( uic1pr, 0xffffe0ff ); /* per ref-board manual */
+ mtdcr( uic1tr, 0x00ffc000 ); /* per ref-board manual */
+ mtdcr( uic1vr, 0x00000001 ); /* int31 highest, base=0x000 */
+ mtdcr( uic1sr, 0xffffffff ); /* clear all */
+
+ return 0;
+}
+
+
+
+int checkboard (void)
+{
+ sys_info_t sysinfo;
+ get_sys_info(&sysinfo);
+
+ printf("esd CPCI-440\n");
+ printf("\tVCO: %lu MHz\n", sysinfo.freqVCOMhz/1000000);
+ printf("\tCPU: %lu MHz\n", sysinfo.freqProcessor/1000000);
+ printf("\tPLB: %lu MHz\n", sysinfo.freqPLB/1000000);
+ printf("\tOPB: %lu MHz\n", sysinfo.freqOPB/1000000);
+ printf("\tEPB: %lu MHz\n", sysinfo.freqEPB/1000000);
+ return (0);
+}
+
+
+long int initdram (int board_type)
+{
+ long dram_size = 0;
+
+ dram_size = fixed_sdram();
+ return dram_size;
+}
+
+
+/*************************************************************************
+ * fixed sdram init -- doesn't use serial presence detect.
+ *
+ * Assumes: 64 MB, non-ECC, non-registered
+ * PLB @ 133 MHz
+ *
+ ************************************************************************/
+long int fixed_sdram( void )
+{
+ uint reg;
+
+ /*--------------------------------------------------------------------
+ * Setup some default
+ *------------------------------------------------------------------*/
+ mtsdram( mem_uabba, 0x00000000 ); /* ubba=0 (default) */
+ mtsdram( mem_slio, 0x00000000 ); /* rdre=0 wrre=0 rarw=0 */
+ mtsdram( mem_devopt,0x00000000 ); /* dll=0 ds=0 (normal) */
+ mtsdram( mem_wddctr,0x40000000 ); /* wrcp=0 dcd=0 */
+ mtsdram( mem_clktr, 0x40000000 ); /* clkp=1 (90 deg wr) dcdt=0 */
+
+ /*--------------------------------------------------------------------
+ * Setup for board-specific specific mem
+ *------------------------------------------------------------------*/
+ /*
+ * Following for CAS Latency = 2.5 @ 133 MHz PLB
+ */
+ mtsdram( mem_b0cr, 0x00082001 );/* SDBA=0x000, 64MB, Mode 2, enabled*/
+ mtsdram( mem_tr0, 0x410a4012 );/* WR=2 WD=1 CL=2.5 PA=3 CP=4 LD=2 */
+ /* RA=10 RD=3 */
+ mtsdram( mem_tr1, 0x8080082f );/* SS=T2 SL=STAGE 3 CD=1 CT=0x02f */
+ mtsdram( mem_rtr, 0x08200000 );/* Rate 15.625 ns @ 133 MHz PLB */
+ mtsdram( mem_cfg1, 0x00000000 );/* Self-refresh exit, disable PM */
+ udelay( 400 ); /* Delay 200 usecs (min) */
+
+ /*--------------------------------------------------------------------
+ * Enable the controller, then wait for DCEN to complete
+ *------------------------------------------------------------------*/
+ mtsdram( mem_cfg0, 0x86000000 );/* DCEN=1, PMUD=1, 64-bit */
+ for(;;)
+ {
+ mfsdram( mem_mcsts, reg );
+ if( reg & 0x80000000 )
+ break;
+ }
+
+ return( 64 * 1024 * 1024 ); /* 64 MB */
+}
--- /dev/null
+/*
+* Copyright (C) 2002 Scott McNutt <smcnutt@artesyncp.com>
+*
+* See file CREDITS for list of people who contributed to this
+* project.
+*
+* This program is free software; you can redistribute it and/or
+* modify it under the terms of the GNU General Public License as
+* published by the Free Software Foundation; either version 2 of
+* the License, or (at your option) any later version.
+*
+* This program is distributed in the hope that it will be useful,
+* but WITHOUT ANY WARRANTY; without even the implied warranty of
+* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+* GNU General Public License for more details.
+*
+* You should have received a copy of the GNU General Public License
+* along with this program; if not, write to the Free Software
+* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+* MA 02111-1307 USA
+*/
+
+#include <ppc_asm.tmpl>
+#include <config.h>
+
+/* General */
+#define TLB_VALID 0x00000200
+
+/* Supported page sizes */
+
+#define SZ_1K 0x00000000
+#define SZ_4K 0x00000010
+#define SZ_16K 0x00000020
+#define SZ_64K 0x00000030
+#define SZ_256K 0x00000040
+#define SZ_1M 0x00000050
+#define SZ_16M 0x00000070
+#define SZ_256M 0x00000090
+
+/* Storage attributes */
+#define SA_W 0x00000800 /* Write-through */
+#define SA_I 0x00000400 /* Caching inhibited */
+#define SA_M 0x00000200 /* Memory coherence */
+#define SA_G 0x00000100 /* Guarded */
+#define SA_E 0x00000080 /* Endian */
+
+/* Access control */
+#define AC_X 0x00000024 /* Execute */
+#define AC_W 0x00000012 /* Write */
+#define AC_R 0x00000009 /* Read */
+
+/* Some handy macros */
+
+#define EPN(e) ((e) & 0xfffffc00)
+#define TLB0(epn,sz) ( (EPN((epn)) | (sz) | TLB_VALID ) )
+#define TLB1(rpn,erpn) ( ((rpn)&0xfffffc00) | (erpn) )
+#define TLB2(a) ( (a)&0x00000fbf )
+
+#define tlbtab_start\
+ mflr r1 ;\
+ bl 0f ;
+
+#define tlbtab_end\
+ .long 0, 0, 0 ; \
+0: mflr r0 ; \
+ mtlr r1 ; \
+ blr ;
+
+#define tlbentry(epn,sz,rpn,erpn,attr)\
+ .long TLB0(epn,sz),TLB1(rpn,erpn),TLB2(attr)
+
+
+/*************************************************************************/
+/* TLB TABLE
+ *
+ * This table is used by the cpu boot code to setup the initial tlb
+ * entries. Rather than make broad assumptions in the cpu source tree,
+ * this table lets each board set things up however they like.
+ *
+ * Pointer to the table is returned in r1
+ *
+/*************************************************************************/
+
+ .section .bootpg,"ax"
+ .globl tlbtab
+
+tlbtab:
+ tlbtab_start
+ tlbentry( 0xf0000000, SZ_256M, 0xf0000000, 1, AC_R|AC_W|AC_X|SA_G|SA_I)
+ tlbentry( CFG_PERIPHERAL_BASE, SZ_256M, 0x40000000, 1, AC_R|AC_W|SA_G|SA_I)
+ tlbentry( CFG_ISRAM_BASE, SZ_4K, 0x80000000, 0, AC_R|AC_W|AC_X )
+ tlbentry( CFG_ISRAM_BASE + 0x1000, SZ_4K, 0x80001000, 0, AC_R|AC_W|AC_X )
+ tlbentry( CFG_SDRAM_BASE, SZ_256M, 0x00000000, 0, AC_R|AC_W|AC_X )
+ tlbtab_end
+
+
--- /dev/null
+/*
+ * (C) Copyright 2002
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+ __DYNAMIC = 0; */
+SECTIONS
+{
+ .resetvec 0xFFFFFFFC :
+ {
+ *(.resetvec)
+ } = 0xffff
+
+ .bootpg 0xFFFFF000 :
+ {
+ cpu/ppc4xx/start.o (.bootpg)
+ } = 0xffff
+
+ /* Read-only sections, merged into text segment: */
+ . = + SIZEOF_HEADERS;
+ .interp : { *(.interp) }
+ .hash : { *(.hash) }
+ .dynsym : { *(.dynsym) }
+ .dynstr : { *(.dynstr) }
+ .rel.text : { *(.rel.text) }
+ .rela.text : { *(.rela.text) }
+ .rel.data : { *(.rel.data) }
+ .rela.data : { *(.rela.data) }
+ .rel.rodata : { *(.rel.rodata) }
+ .rela.rodata : { *(.rela.rodata) }
+ .rel.got : { *(.rel.got) }
+ .rela.got : { *(.rela.got) }
+ .rel.ctors : { *(.rel.ctors) }
+ .rela.ctors : { *(.rela.ctors) }
+ .rel.dtors : { *(.rel.dtors) }
+ .rela.dtors : { *(.rela.dtors) }
+ .rel.bss : { *(.rel.bss) }
+ .rela.bss : { *(.rela.bss) }
+ .rel.plt : { *(.rel.plt) }
+ .rela.plt : { *(.rela.plt) }
+ .init : { *(.init) }
+ .plt : { *(.plt) }
+ .text :
+ {
+ /* WARNING - the following is hand-optimized to fit within */
+ /* the sector layout of our flash chips! XXX FIXME XXX */
+
+ cpu/ppc4xx/start.o (.text)
+ board/esd/cpci440/init.o (.text)
+ cpu/ppc4xx/kgdb.o (.text)
+ cpu/ppc4xx/traps.o (.text)
+ cpu/ppc4xx/interrupts.o (.text)
+ cpu/ppc4xx/serial.o (.text)
+ cpu/ppc4xx/cpu_init.o (.text)
+ cpu/ppc4xx/speed.o (.text)
+ cpu/ppc4xx/405gp_enet.o (.text)
+ common/dlmalloc.o (.text)
+ lib_generic/crc32.o (.text)
+ lib_ppc/extable.o (.text)
+ lib_generic/zlib.o (.text)
+
+/* . = env_offset;*/
+/* common/environment.o(.text)*/
+
+ *(.text)
+ *(.fixup)
+ *(.got1)
+ }
+ _etext = .;
+ PROVIDE (etext = .);
+ .rodata :
+ {
+ *(.rodata)
+ *(.rodata1)
+ }
+ .fini : { *(.fini) } =0
+ .ctors : { *(.ctors) }
+ .dtors : { *(.dtors) }
+
+ /* Read-write section, merged into data segment: */
+ . = (. + 0x00FF) & 0xFFFFFF00;
+ _erotext = .;
+ PROVIDE (erotext = .);
+ .reloc :
+ {
+ *(.got)
+ _GOT2_TABLE_ = .;
+ *(.got2)
+ _FIXUP_TABLE_ = .;
+ *(.fixup)
+ }
+ __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+ __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+ .data :
+ {
+ *(.data)
+ *(.data1)
+ *(.sdata)
+ *(.sdata2)
+ *(.dynamic)
+ CONSTRUCTORS
+ }
+ _edata = .;
+ PROVIDE (edata = .);
+
+ __start___ex_table = .;
+ __ex_table : { *(__ex_table) }
+ __stop___ex_table = .;
+
+ . = ALIGN(256);
+ __init_begin = .;
+ .text.init : { *(.text.init) }
+ .data.init : { *(.data.init) }
+ . = ALIGN(256);
+ __init_end = .;
+
+ __bss_start = .;
+ .bss :
+ {
+ *(.sbss) *(.scommon)
+ *(.dynbss)
+ *(.bss)
+ *(COMMON)
+ }
+ _end = . ;
+ PROVIDE (end = .);
+}
--- /dev/null
+/*
+ * (C) Copyright 2002
+ * Brad Kemp, Seranoa Networks, Brad.Kemp@seranoa.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <ppcboot.h>
+#include <asm/processor.h>
+
+#undef DEBUG_FLASH
+/*
+ * This file implements a Common Flash Interface (CFI) driver for ppcboot.
+ * The width of the port and the width of the chips are determined at initialization.
+ * These widths are used to calculate the address for access CFI data structures.
+ * It has been tested on an Intel Strataflash implementation.
+ *
+ * References
+ * JEDEC Standard JESD68 - Common Flash Interface (CFI)
+ * JEDEC Standard JEP137-A Common Flash Interface (CFI) ID Codes
+ * Intel Application Note 646 Common Flash Interface (CFI) and Command Sets
+ * Intel 290667-008 3 Volt Intel StrataFlash Memory datasheet
+ *
+ * TODO
+ * Use Primary Extended Query table (PRI) and Alternate Algorithm Query Table (ALT) to determine if protection is available
+ * Add support for other command sets Use the PRI and ALT to determine command set
+ * Verify erase and program timeouts.
+ */
+
+#define FLASH_CMD_CFI 0x98
+#define FLASH_CMD_READ_ID 0x90
+#define FLASH_CMD_RESET 0xff
+#define FLASH_CMD_BLOCK_ERASE 0x20
+#define FLASH_CMD_ERASE_CONFIRM 0xD0
+#define FLASH_CMD_WRITE 0x40
+#define FLASH_CMD_PROTECT 0x60
+#define FLASH_CMD_PROTECT_SET 0x01
+#define FLASH_CMD_PROTECT_CLEAR 0xD0
+#define FLASH_CMD_CLEAR_STATUS 0x50
+#define FLASH_CMD_WRITE_TO_BUFFER 0xE8
+#define FLASH_CMD_WRITE_BUFFER_CONFIRM 0xD0
+
+#define FLASH_STATUS_DONE 0x80
+#define FLASH_STATUS_ESS 0x40
+#define FLASH_STATUS_ECLBS 0x20
+#define FLASH_STATUS_PSLBS 0x10
+#define FLASH_STATUS_VPENS 0x08
+#define FLASH_STATUS_PSS 0x04
+#define FLASH_STATUS_DPS 0x02
+#define FLASH_STATUS_R 0x01
+#define FLASH_STATUS_PROTECT 0x01
+
+#define FLASH_OFFSET_CFI 0x55
+#define FLASH_OFFSET_CFI_RESP 0x10
+#define FLASH_OFFSET_WTOUT 0x1F
+#define FLASH_OFFSET_WBTOUT 0x20
+#define FLASH_OFFSET_ETOUT 0x21
+#define FLASH_OFFSET_CETOUT 0x22
+#define FLASH_OFFSET_WMAX_TOUT 0x23
+#define FLASH_OFFSET_WBMAX_TOUT 0x24
+#define FLASH_OFFSET_EMAX_TOUT 0x25
+#define FLASH_OFFSET_CEMAX_TOUT 0x26
+#define FLASH_OFFSET_SIZE 0x27
+#define FLASH_OFFSET_INTERFACE 0x28
+#define FLASH_OFFSET_BUFFER_SIZE 0x2A
+#define FLASH_OFFSET_NUM_ERASE_REGIONS 0x2C
+#define FLASH_OFFSET_ERASE_REGIONS 0x2D
+#define FLASH_OFFSET_PROTECT 0x02
+#define FLASH_OFFSET_USER_PROTECTION 0x85
+#define FLASH_OFFSET_INTEL_PROTECTION 0x81
+
+
+#define FLASH_MAN_CFI 0x01000000
+
+
+
+
+typedef union {
+ unsigned char c;
+ unsigned short w;
+ unsigned long l;
+} cfiword_t;
+
+typedef union {
+ unsigned char * cp;
+ unsigned short *wp;
+ unsigned long *lp;
+} cfiptr_t;
+
+#define NUM_ERASE_REGIONS 4
+
+flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
+
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+
+
+
+static void flash_add_byte(flash_info_t *info, cfiword_t * cword, uchar c);
+static void flash_make_cmd(flash_info_t * info, uchar cmd, void * cmdbuf);
+static void flash_write_cmd(flash_info_t * info, int sect, uchar offset, uchar cmd);
+static int flash_isequal(flash_info_t * info, int sect, uchar offset, uchar cmd);
+static int flash_isset(flash_info_t * info, int sect, uchar offset, uchar cmd);
+static int flash_detect_cfi(flash_info_t * info);
+static ulong flash_get_size (ulong base, int banknum);
+static int flash_write_cfiword (flash_info_t *info, ulong dest, cfiword_t cword);
+static int flash_full_status_check(flash_info_t * info, ulong sector, ulong tout, char * prompt);
+#ifdef CFG_FLASH_USE_BUFFER_WRITE
+static int flash_write_cfibuffer(flash_info_t * info, ulong dest, uchar * cp, int len);
+#endif
+/*-----------------------------------------------------------------------
+ * create an address based on the offset and the port width
+ */
+inline uchar * flash_make_addr(flash_info_t * info, int sect, int offset)
+{
+ return ((uchar *)(info->start[sect] + (offset * info->portwidth)));
+}
+/*-----------------------------------------------------------------------
+ * read a character at a port width address
+ */
+inline uchar flash_read_uchar(flash_info_t * info, uchar offset)
+{
+ uchar *cp;
+ cp = flash_make_addr(info, 0, offset);
+ return (cp[info->portwidth - 1]);
+}
+
+/*-----------------------------------------------------------------------
+ * read a short word by swapping for ppc format.
+ */
+ushort flash_read_ushort(flash_info_t * info, int sect, uchar offset)
+{
+ uchar * addr;
+
+ addr = flash_make_addr(info, sect, offset);
+ return ((addr[(2*info->portwidth) - 1] << 8) | addr[info->portwidth - 1]);
+
+}
+
+/*-----------------------------------------------------------------------
+ * read a long word by picking the least significant byte of each maiximum
+ * port size word. Swap for ppc format.
+ */
+ulong flash_read_long(flash_info_t * info, int sect, uchar offset)
+{
+ uchar * addr;
+
+ addr = flash_make_addr(info, sect, offset);
+ return ( (addr[(2*info->portwidth) - 1] << 24 ) | (addr[(info->portwidth) -1] << 16) |
+ (addr[(4*info->portwidth) - 1] << 8) | addr[(3*info->portwidth) - 1]);
+
+}
+
+/*-----------------------------------------------------------------------
+ */
+unsigned long flash_init (void)
+{
+ unsigned long size;
+ int i;
+ unsigned long address;
+
+
+ /* The flash is positioned back to back, with the demultiplexing of the chip
+ * based on the A24 address line.
+ *
+ */
+
+ address = CFG_FLASH_BASE;
+ size = 0;
+
+ /* Init: no FLASHes known */
+ for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) {
+ flash_info[i].flash_id = FLASH_UNKNOWN;
+ size += flash_info[i].size = flash_get_size(address, i);
+ address += CFG_FLASH_INCREMENT;
+ if (flash_info[0].flash_id == FLASH_UNKNOWN) {
+ printf ("## Unknown FLASH on Bank %d - Size = 0x%08lx = %ld MB\n",i,
+ flash_info[0].size, flash_info[i].size<<20);
+ }
+ }
+
+#if 0 /* test-only */
+ /* Monitor protection ON by default */
+#if (CFG_MONITOR_BASE >= CFG_FLASH_BASE)
+ for(i=0; flash_info[0].start[i] < CFG_MONITOR_BASE+CFG_MONITOR_LEN-1; i++)
+ (void)flash_real_protect(&flash_info[0], i, 1);
+#endif
+#endif
+
+ return (size);
+}
+
+/*-----------------------------------------------------------------------
+ */
+int flash_erase (flash_info_t *info, int s_first, int s_last)
+{
+ int rcode = 0;
+ int prot;
+ int sect;
+
+ if( info->flash_id != FLASH_MAN_CFI) {
+ printf ("Can't erase unknown flash type - aborted\n");
+ return 1;
+ }
+ if ((s_first < 0) || (s_first > s_last)) {
+ printf ("- no sectors to erase\n");
+ return 1;
+ }
+
+ prot = 0;
+ for (sect=s_first; sect<=s_last; ++sect) {
+ if (info->protect[sect]) {
+ prot++;
+ }
+ }
+ if (prot) {
+ printf ("- Warning: %d protected sectors will not be erased!\n",
+ prot);
+ } else {
+ printf ("\n");
+ }
+
+
+ for (sect = s_first; sect<=s_last; sect++) {
+ if (info->protect[sect] == 0) { /* not protected */
+ flash_write_cmd(info, sect, 0, FLASH_CMD_CLEAR_STATUS);
+ flash_write_cmd(info, sect, 0, FLASH_CMD_BLOCK_ERASE);
+ flash_write_cmd(info, sect, 0, FLASH_CMD_ERASE_CONFIRM);
+
+ if(flash_full_status_check(info, sect, info->erase_blk_tout, "erase")) {
+ rcode = 1;
+ } else
+ printf(".");
+ }
+ }
+ printf (" done\n");
+ return rcode;
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info (flash_info_t *info)
+{
+ int i;
+
+ if (info->flash_id != FLASH_MAN_CFI) {
+ printf ("missing or unknown FLASH type\n");
+ return;
+ }
+
+ printf("CFI conformant FLASH (%d x %d)",
+ (info->portwidth << 3 ), (info->chipwidth << 3 ));
+ printf (" Size: %ld MB in %d Sectors\n",
+ info->size >> 20, info->sector_count);
+ printf(" Erase timeout %ld ms, write timeout %ld ms, buffer write timeout %ld ms, buffer size %d\n",
+ info->erase_blk_tout, info->write_tout, info->buffer_write_tout, info->buffer_size);
+
+ printf (" Sector Start Addresses:");
+ for (i=0; i<info->sector_count; ++i) {
+ if ((i % 5) == 0)
+ printf ("\n");
+ printf (" %08lX%5s",
+ info->start[i],
+ info->protect[i] ? " (RO)" : " "
+ );
+ }
+ printf ("\n");
+ return;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+{
+ ulong wp;
+ ulong cp;
+ int aln;
+ cfiword_t cword;
+ int i, rc;
+
+ /* get lower aligned address */
+ wp = (addr & ~(info->portwidth - 1));
+
+ /* handle unaligned start */
+ if((aln = addr - wp) != 0) {
+ cword.l = 0;
+ cp = wp;
+ for(i=0;i<aln; ++i, ++cp)
+ flash_add_byte(info, &cword, (*(uchar *)cp));
+
+ for(; (i< info->portwidth) && (cnt > 0) ; i++) {
+ flash_add_byte(info, &cword, *src++);
+ cnt--;
+ cp++;
+ }
+ for(; (cnt == 0) && (i < info->portwidth); ++i, ++cp)
+ flash_add_byte(info, &cword, (*(uchar *)cp));
+ if((rc = flash_write_cfiword(info, wp, cword)) != 0)
+ return rc;
+ wp = cp;
+ }
+
+#ifdef CFG_FLASH_USE_BUFFER_WRITE
+ while(cnt >= info->portwidth) {
+ i = info->buffer_size > cnt? cnt: info->buffer_size;
+ if((rc = flash_write_cfibuffer(info, wp, src,i)) != ERR_OK)
+ return rc;
+ wp += i;
+ src += i;
+ cnt -=i;
+ }
+#else
+ /* handle the aligned part */
+ while(cnt >= info->portwidth) {
+ cword.l = 0;
+ for(i = 0; i < info->portwidth; i++) {
+ flash_add_byte(info, &cword, *src++);
+ }
+ if((rc = flash_write_cfiword(info, wp, cword)) != 0)
+ return rc;
+ wp += info->portwidth;
+ cnt -= info->portwidth;
+ }
+#endif /* CFG_FLASH_USE_BUFFER_WRITE */
+ if (cnt == 0) {
+ return (0);
+ }
+
+ /*
+ * handle unaligned tail bytes
+ */
+ cword.l = 0;
+ for (i=0, cp=wp; (i<info->portwidth) && (cnt>0); ++i, ++cp) {
+ flash_add_byte(info, &cword, *src++);
+ --cnt;
+ }
+ for (; i<info->portwidth; ++i, ++cp) {
+ flash_add_byte(info, & cword, (*(uchar *)cp));
+ }
+
+ return flash_write_cfiword(info, wp, cword);
+}
+
+/*-----------------------------------------------------------------------
+ */
+int flash_real_protect(flash_info_t *info, long sector, int prot)
+{
+ int retcode = 0;
+
+ flash_write_cmd(info, sector, 0, FLASH_CMD_CLEAR_STATUS);
+ flash_write_cmd(info, sector, 0, FLASH_CMD_PROTECT);
+ if(prot)
+ flash_write_cmd(info, sector, 0, FLASH_CMD_PROTECT_SET);
+ else
+ flash_write_cmd(info, sector, 0, FLASH_CMD_PROTECT_CLEAR);
+
+ if((retcode = flash_full_status_check(info, sector, info->erase_blk_tout,
+ prot?"protect":"unprotect")) == 0) {
+
+ info->protect[sector] = prot;
+ /* Intel's unprotect unprotects all locking */
+ if(prot == 0) {
+ int i;
+ for(i = 0 ; i<info->sector_count; i++) {
+ if(info->protect[i])
+ flash_real_protect(info, i, 1);
+ }
+ }
+ }
+
+ return retcode;
+}
+/*-----------------------------------------------------------------------
+ * wait for XSR.7 to be set. Time out with an error if it does not.
+ * This routine does not set the flash to read-array mode.
+ */
+static int flash_status_check(flash_info_t * info, ulong sector, ulong tout, char * prompt)
+{
+ ulong start;
+
+ /* Wait for command completion */
+ start = get_timer (0);
+ while(!flash_isset(info, sector, 0, FLASH_STATUS_DONE)) {
+ if (get_timer(start) > info->erase_blk_tout) {
+ printf("Flash %s timeout at address %lx\n", prompt, info->start[sector]);
+ flash_write_cmd(info, sector, 0, FLASH_CMD_RESET);
+ return ERR_TIMOUT;
+ }
+ }
+ return ERR_OK;
+}
+/*-----------------------------------------------------------------------
+ * Wait for XSR.7 to be set, if it times out print an error, otherwise do a full status check.
+ * This routine sets the flash to read-array mode.
+ */
+static int flash_full_status_check(flash_info_t * info, ulong sector, ulong tout, char * prompt)
+{
+ int retcode;
+ retcode = flash_status_check(info, sector, tout, prompt);
+ if((retcode == ERR_OK) && !flash_isequal(info,sector, 0, FLASH_STATUS_DONE)) {
+ retcode = ERR_INVAL;
+ printf("Flash %s error at address %lx\n", prompt,info->start[sector]);
+ if(flash_isset(info, sector, 0, FLASH_STATUS_ECLBS | FLASH_STATUS_PSLBS)){
+ printf("Command Sequence Error.\n");
+ } else if(flash_isset(info, sector, 0, FLASH_STATUS_ECLBS)){
+ printf("Block Erase Error.\n");
+ retcode = ERR_NOT_ERASED;
+ } else if (flash_isset(info, sector, 0, FLASH_STATUS_PSLBS)) {
+ printf("Locking Error\n");
+ }
+ if(flash_isset(info, sector, 0, FLASH_STATUS_DPS)){
+ printf("Block locked.\n");
+ retcode = ERR_PROTECTED;
+ }
+ if(flash_isset(info, sector, 0, FLASH_STATUS_VPENS))
+ printf("Vpp Low Error.\n");
+ }
+ flash_write_cmd(info, sector, 0, FLASH_CMD_RESET);
+ return retcode;
+}
+/*-----------------------------------------------------------------------
+ */
+static void flash_add_byte(flash_info_t *info, cfiword_t * cword, uchar c)
+{
+ switch(info->portwidth) {
+ case FLASH_CFI_8BIT:
+ cword->c = c;
+ break;
+ case FLASH_CFI_16BIT:
+ cword->w = (cword->w << 8) | c;
+ break;
+ case FLASH_CFI_32BIT:
+ cword->l = (cword->l << 8) | c;
+ }
+}
+
+
+/*-----------------------------------------------------------------------
+ * make a proper sized command based on the port and chip widths
+ */
+static void flash_make_cmd(flash_info_t * info, uchar cmd, void * cmdbuf)
+{
+ int i;
+ uchar *cp = (uchar *)cmdbuf;
+ for(i=0; i< info->portwidth; i++)
+ *cp++ = ((i+1) % info->chipwidth) ? '\0':cmd;
+}
+
+/*
+ * Write a proper sized command to the correct address
+ */
+static void flash_write_cmd(flash_info_t * info, int sect, uchar offset, uchar cmd)
+{
+
+ volatile cfiptr_t addr;
+ cfiword_t cword;
+ addr.cp = flash_make_addr(info, sect, offset);
+ flash_make_cmd(info, cmd, &cword);
+ switch(info->portwidth) {
+ case FLASH_CFI_8BIT:
+ *addr.cp = cword.c;
+ break;
+ case FLASH_CFI_16BIT:
+ *addr.wp = cword.w;
+ break;
+ case FLASH_CFI_32BIT:
+ *addr.lp = cword.l;
+ break;
+ }
+}
+
+/*-----------------------------------------------------------------------
+ */
+static int flash_isequal(flash_info_t * info, int sect, uchar offset, uchar cmd)
+{
+ cfiptr_t cptr;
+ cfiword_t cword;
+ int retval;
+ cptr.cp = flash_make_addr(info, sect, offset);
+ flash_make_cmd(info, cmd, &cword);
+ switch(info->portwidth) {
+ case FLASH_CFI_8BIT:
+ retval = (cptr.cp[0] == cword.c);
+ break;
+ case FLASH_CFI_16BIT:
+ retval = (cptr.wp[0] == cword.w);
+ break;
+ case FLASH_CFI_32BIT:
+ retval = (cptr.lp[0] == cword.l);
+ break;
+ default:
+ retval = 0;
+ break;
+ }
+ return retval;
+}
+/*-----------------------------------------------------------------------
+ */
+static int flash_isset(flash_info_t * info, int sect, uchar offset, uchar cmd)
+{
+ cfiptr_t cptr;
+ cfiword_t cword;
+ int retval;
+ cptr.cp = flash_make_addr(info, sect, offset);
+ flash_make_cmd(info, cmd, &cword);
+ switch(info->portwidth) {
+ case FLASH_CFI_8BIT:
+ retval = ((cptr.cp[0] & cword.c) == cword.c);
+ break;
+ case FLASH_CFI_16BIT:
+ retval = ((cptr.wp[0] & cword.w) == cword.w);
+ break;
+ case FLASH_CFI_32BIT:
+ retval = ((cptr.lp[0] & cword.l) == cword.l);
+ break;
+ default:
+ retval = 0;
+ break;
+ }
+ return retval;
+}
+
+/*-----------------------------------------------------------------------
+ * detect if flash is compatible with the Common Flash Interface (CFI)
+ * http://www.jedec.org/download/search/jesd68.pdf
+ *
+*/
+static int flash_detect_cfi(flash_info_t * info)
+{
+
+ for(info->portwidth=FLASH_CFI_8BIT; info->portwidth <= FLASH_CFI_32BIT;
+ info->portwidth <<= 1) {
+ for(info->chipwidth =FLASH_CFI_BY8;
+ info->chipwidth <= info->portwidth;
+ info->chipwidth <<= 1) {
+ flash_write_cmd(info, 0, 0, FLASH_CMD_RESET);
+ flash_write_cmd(info, 0, FLASH_OFFSET_CFI, FLASH_CMD_CFI);
+ if(flash_isequal(info, 0, FLASH_OFFSET_CFI_RESP,'Q') &&
+ flash_isequal(info, 0, FLASH_OFFSET_CFI_RESP + 1, 'R') &&
+ flash_isequal(info, 0, FLASH_OFFSET_CFI_RESP + 2, 'Y'))
+ return 1;
+ }
+ }
+ return 0;
+}
+/*
+ * The following code cannot be run from FLASH!
+ *
+ */
+static ulong flash_get_size (ulong base, int banknum)
+{
+ flash_info_t * info = &flash_info[banknum];
+ int i, j;
+ int sect_cnt;
+ unsigned long sector;
+ unsigned long tmp;
+ int size_ratio;
+ uchar num_erase_regions;
+ int erase_region_size;
+ int erase_region_count;
+
+ info->start[0] = base;
+
+ if(flash_detect_cfi(info)){
+#ifdef DEBUG_FLASH
+ printf("portwidth=%d chipwidth=%d\n", info->portwidth, info->chipwidth); /* test-only */
+#endif
+ size_ratio = info->portwidth / info->chipwidth;
+ num_erase_regions = flash_read_uchar(info, FLASH_OFFSET_NUM_ERASE_REGIONS);
+#ifdef DEBUG_FLASH
+ printf("found %d erase regions\n", num_erase_regions);
+#endif
+ sect_cnt = 0;
+ sector = base;
+ for(i = 0 ; i < num_erase_regions; i++) {
+ if(i > NUM_ERASE_REGIONS) {
+ printf("%d erase regions found, only %d used\n",
+ num_erase_regions, NUM_ERASE_REGIONS);
+ break;
+ }
+ tmp = flash_read_long(info, 0, FLASH_OFFSET_ERASE_REGIONS);
+ erase_region_size = (tmp & 0xffff)? ((tmp & 0xffff) * 256): 128;
+ tmp >>= 16;
+ erase_region_count = (tmp & 0xffff) +1;
+ for(j = 0; j< erase_region_count; j++) {
+ info->start[sect_cnt] = sector;
+ sector += (erase_region_size * size_ratio);
+ info->protect[sect_cnt] = flash_isset(info, sect_cnt, FLASH_OFFSET_PROTECT, FLASH_STATUS_PROTECT);
+ sect_cnt++;
+ }
+ }
+
+ info->sector_count = sect_cnt;
+ /* multiply the size by the number of chips */
+ info->size = (1 << flash_read_uchar(info, FLASH_OFFSET_SIZE)) * size_ratio;
+ info->buffer_size = (1 << flash_read_ushort(info, 0, FLASH_OFFSET_BUFFER_SIZE));
+ tmp = 1 << flash_read_uchar(info, FLASH_OFFSET_ETOUT);
+ info->erase_blk_tout = (tmp * (1 << flash_read_uchar(info, FLASH_OFFSET_EMAX_TOUT)));
+ tmp = 1 << flash_read_uchar(info, FLASH_OFFSET_WBTOUT);
+ info->buffer_write_tout = (tmp * (1 << flash_read_uchar(info, FLASH_OFFSET_WBMAX_TOUT)));
+ tmp = 1 << flash_read_uchar(info, FLASH_OFFSET_WTOUT);
+ info->write_tout = (tmp * (1 << flash_read_uchar(info, FLASH_OFFSET_WMAX_TOUT)))/ 1000;
+ info->flash_id = FLASH_MAN_CFI;
+ }
+
+ flash_write_cmd(info, 0, 0, FLASH_CMD_RESET);
+ return(info->size);
+}
+
+
+/*-----------------------------------------------------------------------
+ */
+static int flash_write_cfiword (flash_info_t *info, ulong dest, cfiword_t cword)
+{
+
+ cfiptr_t ctladdr;
+ cfiptr_t cptr;
+ int flag;
+
+ ctladdr.cp = flash_make_addr(info, 0, 0);
+ cptr.cp = (uchar *)dest;
+
+
+ /* Check if Flash is (sufficiently) erased */
+ switch(info->portwidth) {
+ case FLASH_CFI_8BIT:
+ flag = ((cptr.cp[0] & cword.c) == cword.c);
+ break;
+ case FLASH_CFI_16BIT:
+ flag = ((cptr.wp[0] & cword.w) == cword.w);
+ break;
+ case FLASH_CFI_32BIT:
+ flag = ((cptr.lp[0] & cword.l) == cword.l);
+ break;
+ default:
+ return 2;
+ }
+ if(!flag)
+ return 2;
+
+ /* Disable interrupts which might cause a timeout here */
+ flag = disable_interrupts();
+
+ flash_write_cmd(info, 0, 0, FLASH_CMD_CLEAR_STATUS);
+ flash_write_cmd(info, 0, 0, FLASH_CMD_WRITE);
+
+ switch(info->portwidth) {
+ case FLASH_CFI_8BIT:
+ cptr.cp[0] = cword.c;
+ break;
+ case FLASH_CFI_16BIT:
+ cptr.wp[0] = cword.w;
+ break;
+ case FLASH_CFI_32BIT:
+ cptr.lp[0] = cword.l;
+ break;
+ }
+
+ /* re-enable interrupts if necessary */
+ if(flag)
+ enable_interrupts();
+
+ return flash_full_status_check(info, 0, info->write_tout, "write");
+}
+
+#ifdef CFG_FLASH_USE_BUFFER_WRITE
+
+/* loop through the sectors from the highest address
+ * when the passed address is greater or equal to the sector address
+ * we have a match
+ */
+static int find_sector(flash_info_t *info, ulong addr)
+{
+ int sector;
+ for(sector = info->sector_count - 1; sector >= 0; sector--) {
+ if(addr >= info->start[sector])
+ break;
+ }
+ return sector;
+}
+
+static int flash_write_cfibuffer(flash_info_t * info, ulong dest, uchar * cp, int len)
+{
+
+ int sector;
+ int cnt;
+ int retcode;
+ volatile cfiptr_t src;
+ volatile cfiptr_t dst;
+
+ src.cp = cp;
+ dst.cp = (uchar *)dest;
+ sector = find_sector(info, dest);
+ flash_write_cmd(info, sector, 0, FLASH_CMD_CLEAR_STATUS);
+ flash_write_cmd(info, sector, 0, FLASH_CMD_WRITE_TO_BUFFER);
+ if((retcode = flash_status_check(info, sector, info->buffer_write_tout,
+ "write to buffer")) == ERR_OK) {
+ switch(info->portwidth) {
+ case FLASH_CFI_8BIT:
+ cnt = len;
+ break;
+ case FLASH_CFI_16BIT:
+ cnt = len >> 1;
+ break;
+ case FLASH_CFI_32BIT:
+ cnt = len >> 2;
+ break;
+ default:
+ return ERR_INVAL;
+ break;
+ }
+ flash_write_cmd(info, sector, 0, (uchar)cnt-1);
+ while(cnt-- > 0) {
+ switch(info->portwidth) {
+ case FLASH_CFI_8BIT:
+ *dst.cp++ = *src.cp++;
+ break;
+ case FLASH_CFI_16BIT:
+ *dst.wp++ = *src.wp++;
+ break;
+ case FLASH_CFI_32BIT:
+ *dst.lp++ = *src.lp++;
+ break;
+ default:
+ return ERR_INVAL;
+ break;
+ }
+ }
+ flash_write_cmd(info, sector, 0, FLASH_CMD_WRITE_BUFFER_CONFIRM);
+ retcode = flash_full_status_check(info, sector, info->buffer_write_tout,
+ "buffer write");
+ }
+ flash_write_cmd(info, sector, 0, FLASH_CMD_CLEAR_STATUS);
+ return retcode;
+}
+#endif /* CFG_USE_FLASH_BUFFER_WRITE */
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
- cpu/mpc8xx/start.o (.text)
- common/dlmalloc.o (.text)
- lib_ppc/ppcstring.o (.text)
- lib_generic/vsprintf.o (.text)
- lib_generic/crc32.o (.text)
- lib_generic/zlib.o (.text)
+ cpu/mpc8xx/start.o (.text)
+ common/dlmalloc.o (.text)
+ lib_ppc/ppcstring.o (.text)
+ lib_generic/vsprintf.o (.text)
+ lib_generic/crc32.o (.text)
+ lib_generic/zlib.o (.text)
+ /* lib_generic/display_options.o (.text)
+ lib_generic/ldiv.o (.text)
+ */
+ lib_generic/string.o (.text)
+ lib_ppc/cache.o (.text)
+ lib_ppc/extable.o (.text)
+ lib_ppc/time.o (.text)
+ lib_ppc/ticks.o (.text)
. = env_offset;
common/environment.o(.text)
baudrate = (i > 0) ? (int)simple_strtoul(tmp, NULL, 10) : CONFIG_BAUDRATE;
/* set up serial port */
+#if defined(CONFIG_440)
+ serial_init (get_bus_freq(0), baudrate);
+#else
serial_init (idata->cpu_clk, baudrate);
+#endif
idata->have_console = 1;
/*-----------------------------------------------------------------------------+
- |
- | This source code has been made available to you by IBM on an AS-IS
- | basis. Anyone receiving this source is licensed under IBM
- | copyrights to use it in any way he or she deems fit, including
- | copying it, modifying it, compiling it, and redistributing it either
- | with or without modifications. No license under IBM patents or
- | patent applications is to be implied by the copyright license.
- |
- | Any user of this software should understand that IBM cannot provide
- | technical support for this software and will not be responsible for
- | any consequences resulting from the use of this software.
- |
- | Any person who transfers this source code or any derivative work
- | must include the IBM copyright notice, this paragraph, and the
- | preceding two paragraphs in the transferred software.
- |
- | COPYRIGHT I B M CORPORATION 1995
- | LICENSED MATERIAL - PROGRAM PROPERTY OF I B M
- +-----------------------------------------------------------------------------*/
+ *
+ * This source code has been made available to you by IBM on an AS-IS
+ * basis. Anyone receiving this source is licensed under IBM
+ * copyrights to use it in any way he or she deems fit, including
+ * copying it, modifying it, compiling it, and redistributing it either
+ * with or without modifications. No license under IBM patents or
+ * patent applications is to be implied by the copyright license.
+ *
+ * Any user of this software should understand that IBM cannot provide
+ * technical support for this software and will not be responsible for
+ * any consequences resulting from the use of this software.
+ *
+ * Any person who transfers this source code or any derivative work
+ * must include the IBM copyright notice, this paragraph, and the
+ * preceding two paragraphs in the transferred software.
+ *
+ * COPYRIGHT I B M CORPORATION 1995
+ * LICENSED MATERIAL - PROGRAM PROPERTY OF I B M
+ *-----------------------------------------------------------------------------*/
/*-----------------------------------------------------------------------------+
- |
- | File Name: enetemac.c
- |
- | Function: Device driver for the ethernet EMAC3 macro on the 405GP.
- |
- | Author: Mark Wisner
- |
- | Change Activity-
- |
- | Date Description of Change BY
- | --------- --------------------- ---
- | 05-May-99 Created MKW
- | 27-Jun-99 Clean up JWB
- | 16-Jul-99 Added MAL error recovery and better IP packet handling MKW
- | 29-Jul-99 Added Full duplex support MKW
- | 06-Aug-99 Changed names for Mal CR reg MKW
- | 23-Aug-99 Turned off SYE when running at 10Mbs MKW
- | 24-Aug-99 Marked descriptor empty after call_xlc MKW
- | 07-Sep-99 Set MAL RX buffer size reg to ENET_MAX_MTU_ALIGNED / 16 MCG
- | to avoid chaining maximum sized packets. Push starting
- | RX descriptor address up to the next cache line boundary.
- | 16-Jan-00 Added support for booting with IP of 0x0 MKW
- | 15-Mar-00 Updated enetInit() to enable broadcast addresses in the
- | EMAC_RXM register. JWB
- | 12-Mar-01 anne-sophie.harnois@nextream.fr
- | - Variables are compatible with those already defined in
- | include/net.h
- | - Receive buffer descriptor ring is used to send buffers
- | to the user
- | - Info print about send/received/handled packet number if
- | INFO_405_ENET is set
- | 17-Apr-01 stefan.roese@esd-electronics.com
- | - MAL reset in "eth_halt" included
- | - Enet speed and duplex output now in one line
- | 08-May-01 stefan.roese@esd-electronics.com
- | - MAL error handling added (eth_init called again)
- | 13-Nov-01 stefan.roese@esd-electronics.com
- | - Set IST bit in EMAC_M1 reg upon 100MBit or full duplex
- | 04-Jan-02 stefan.roese@esd-electronics.com
- | - Wait for PHY auto negotiation to complete added
- | 06-Feb-02 stefan.roese@esd-electronics.com
- | - Bug fixed in waiting for auto negotiation to complete
- | 26-Feb-02 stefan.roese@esd-electronics.com
- | - rx and tx buffer descriptors now allocated (no fixed address
- | used anymore)
- | 17-Jun-02 stefan.roese@esd-electronics.com
- | - MAL error debug printf 'M' removed (rx de interrupt may
- | occur upon many incoming packets with only 4 rx buffers).
- +-----------------------------------------------------------------------------*/
+ *
+ * File Name: enetemac.c
+ *
+ * Function: Device driver for the ethernet EMAC3 macro on the 405GP.
+ *
+ * Author: Mark Wisner
+ *
+ * Change Activity-
+ *
+ * Date Description of Change BY
+ * --------- --------------------- ---
+ * 05-May-99 Created MKW
+ * 27-Jun-99 Clean up JWB
+ * 16-Jul-99 Added MAL error recovery and better IP packet handling MKW
+ * 29-Jul-99 Added Full duplex support MKW
+ * 06-Aug-99 Changed names for Mal CR reg MKW
+ * 23-Aug-99 Turned off SYE when running at 10Mbs MKW
+ * 24-Aug-99 Marked descriptor empty after call_xlc MKW
+ * 07-Sep-99 Set MAL RX buffer size reg to ENET_MAX_MTU_ALIGNED / 16 MCG
+ * to avoid chaining maximum sized packets. Push starting
+ * RX descriptor address up to the next cache line boundary.
+ * 16-Jan-00 Added support for booting with IP of 0x0 MKW
+ * 15-Mar-00 Updated enetInit() to enable broadcast addresses in the
+ * EMAC_RXM register. JWB
+ * 12-Mar-01 anne-sophie.harnois@nextream.fr
+ * - Variables are compatible with those already defined in
+ * include/net.h
+ * - Receive buffer descriptor ring is used to send buffers
+ * to the user
+ * - Info print about send/received/handled packet number if
+ * INFO_405_ENET is set
+ * 17-Apr-01 stefan.roese@esd-electronics.com
+ * - MAL reset in "eth_halt" included
+ * - Enet speed and duplex output now in one line
+ * 08-May-01 stefan.roese@esd-electronics.com
+ * - MAL error handling added (eth_init called again)
+ * 13-Nov-01 stefan.roese@esd-electronics.com
+ * - Set IST bit in EMAC_M1 reg upon 100MBit or full duplex
+ * 04-Jan-02 stefan.roese@esd-electronics.com
+ * - Wait for PHY auto negotiation to complete added
+ * 06-Feb-02 stefan.roese@esd-electronics.com
+ * - Bug fixed in waiting for auto negotiation to complete
+ * 26-Feb-02 stefan.roese@esd-electronics.com
+ * - rx and tx buffer descriptors now allocated (no fixed address
+ * used anymore)
+ * 17-Jun-02 stefan.roese@esd-electronics.com
+ * - MAL error debug printf 'M' removed (rx de interrupt may
+ * occur upon many incoming packets with only 4 rx buffers).
+ *-----------------------------------------------------------------------------*/
#include <ppcboot.h>
#include <asm/processor.h>
#include <miiphy.h>
#include <net.h>
#include <malloc.h>
+#include "vecnum.h"
-#ifdef CONFIG_405GP
+#if defined(CONFIG_405GP) || defined(CONFIG_440)
#define EMAC_RESET_TIMEOUT 1000 /* 1000 ms reset timeout */
#define PHY_AUTONEGOTIATE_TIMEOUT 2000 /* 2000 ms autonegotiate timeout */
#define EMAC_TXCHL 1
/*-----------------------------------------------------------------------------+
-| Defines for MAL/EMAC interrupt conditions as reported in the UIC (Universal
-| Interrupt Controller).
-+-----------------------------------------------------------------------------*/
+ * Defines for MAL/EMAC interrupt conditions as reported in the UIC (Universal
+ * Interrupt Controller).
+ *-----------------------------------------------------------------------------*/
#define MAL_UIC_ERR ( UIC_MAL_SERR | UIC_MAL_TXDE | UIC_MAL_RXDE)
#define MAL_UIC_DEF (UIC_MAL_RXEOB | MAL_UIC_ERR)
#define EMAC_UIC_DEF UIC_ENET
/*-----------------------------------------------------------------------------+
-| Global variables. TX and RX descriptors and buffers.
-+-----------------------------------------------------------------------------*/
+ * Global variables. TX and RX descriptors and buffers.
+ *-----------------------------------------------------------------------------*/
static volatile mal_desc_t *tx;
static volatile mal_desc_t *rx;
static mal_desc_t *alloc_tx_buf = NULL;
static void enet_rcv (unsigned long malisr);
/*-----------------------------------------------------------------------------+
-| Prototypes and externals.
-+-----------------------------------------------------------------------------*/
+ * Prototypes and externals.
+ *-----------------------------------------------------------------------------*/
void mal_err (unsigned long isr, unsigned long uic, unsigned long mal_def,
- unsigned long mal_errr);
+ unsigned long mal_errr);
void emac_err (unsigned long isr);
}
-/*-----------------------------------------------------------------------------+
-+----------------------------------------------------------------------------*/
int eth_init (bd_t * bis)
{
int i;
* and doesn't cross cache block boundaries.
*/
alloc_tx_buf = (mal_desc_t *)malloc((sizeof(mal_desc_t) * NUM_TX_BUFF) +
- ((2 * CFG_CACHELINE_SIZE) - 2));
+ ((2 * CFG_CACHELINE_SIZE) - 2));
if (((int)alloc_tx_buf & CACHELINE_MASK) != 0) {
tx = (mal_desc_t *)((int)alloc_tx_buf + CFG_CACHELINE_SIZE -
- ((int)alloc_tx_buf & CACHELINE_MASK));
+ ((int)alloc_tx_buf & CACHELINE_MASK));
} else {
tx = alloc_tx_buf;
}
alloc_rx_buf = (mal_desc_t *)malloc((sizeof(mal_desc_t) * NUM_RX_BUFF) +
- ((2 * CFG_CACHELINE_SIZE) - 2));
+ ((2 * CFG_CACHELINE_SIZE) - 2));
if (((int)alloc_rx_buf & CACHELINE_MASK) != 0) {
rx = (mal_desc_t *)((int)alloc_rx_buf + CFG_CACHELINE_SIZE -
- ((int)alloc_rx_buf & CACHELINE_MASK));
+ ((int)alloc_rx_buf & CACHELINE_MASK));
} else {
rx = alloc_rx_buf;
}
/* Enable broadcast and indvidual address */
out32 (EMAC_RXM, EMAC_RMR_BAE | EMAC_RMR_IAE
- /*| EMAC_RMR_ARRP| EMAC_RMR_SFCS | EMAC_RMR_SP */ );
+ /*| EMAC_RMR_ARRP| EMAC_RMR_SFCS | EMAC_RMR_SP */ );
/* we probably need to set the tx mode1 reg? maybe at tx time */
/*
* Connect interrupt service routines
*/
- irq_install_handler ( 9, (interrupt_handler_t *) enetInt, NULL);
- irq_install_handler (10, (interrupt_handler_t *) enetInt, NULL);
- irq_install_handler (11, (interrupt_handler_t *) enetInt, NULL);
- irq_install_handler (12, (interrupt_handler_t *) enetInt, NULL);
- irq_install_handler (13, (interrupt_handler_t *) enetInt, NULL);
- irq_install_handler (14, (interrupt_handler_t *) enetInt, NULL);
- irq_install_handler (15, (interrupt_handler_t *) enetInt, NULL);
+ irq_install_handler (VECNUM_EWU0, (interrupt_handler_t *) enetInt, NULL);
+ irq_install_handler (VECNUM_MS, (interrupt_handler_t *) enetInt, NULL);
+ irq_install_handler (VECNUM_MTE, (interrupt_handler_t *) enetInt, NULL);
+ irq_install_handler (VECNUM_MRE, (interrupt_handler_t *) enetInt, NULL);
+ irq_install_handler (VECNUM_TXDE, (interrupt_handler_t *) enetInt, NULL);
+ irq_install_handler (VECNUM_RXDE, (interrupt_handler_t *) enetInt, NULL);
+ irq_install_handler (VECNUM_ETH0, (interrupt_handler_t *) enetInt, NULL);
}
/* set up interrupt handler */
/* set the MAL IER ??? names may change with new spec ??? */
mal_ier = MAL_IER_DE | MAL_IER_NE | MAL_IER_TE | MAL_IER_OPBE |
- MAL_IER_PLBE;
+ MAL_IER_PLBE;
mtdcr (malesr, 0xffffffff); /* clear pending interrupts */
mtdcr (maltxdeir, 0xffffffff); /* clear pending interrupts */
mtdcr (malrxdeir, 0xffffffff); /* clear pending interrupts */
/* Set EMAC IER */
emac_ier = EMAC_ISR_PTLE | EMAC_ISR_BFCS |
- EMAC_ISR_PTLE | EMAC_ISR_ORE | EMAC_ISR_IRE;
+ EMAC_ISR_PTLE | EMAC_ISR_ORE | EMAC_ISR_IRE;
if (speed == _100BASET)
emac_ier = emac_ier | EMAC_ISR_SYE;
}
-/*-----------------------------------------------------------------------------+
-+-----------------------------------------------------------------------------*/
int eth_send (volatile void *ptr, int len)
{
struct enet_frame *ef_ptr;
ef_ptr = (struct enet_frame *) ptr;
- /*-----------------------------------------------------------------------+
- | Copy in our address into the frame.
- +-----------------------------------------------------------------------*/
+ /*-----------------------------------------------------------------------+
+ * Copy in our address into the frame.
+ *-----------------------------------------------------------------------*/
(void) memcpy (ef_ptr->source_addr, emac_hwd_addr, ENET_ADDR_LENGTH);
- /*-----------------------------------------------------------------------+
- | If frame is too long or too short, modify length.
- +-----------------------------------------------------------------------*/
+ /*-----------------------------------------------------------------------+
+ * If frame is too long or too short, modify length.
+ *-----------------------------------------------------------------------*/
if (len > ENET_MAX_MTU)
len = ENET_MAX_MTU;
/* memcpy ((void *) &tx_buff[tx_slot], (const void *) ptr, len); */
memcpy ((void *) txbuf_ptr, (const void *) ptr, len);
- /*-----------------------------------------------------------------------+
- | set TX Buffer busy, and send it
- +-----------------------------------------------------------------------*/
+ /*-----------------------------------------------------------------------+
+ * set TX Buffer busy, and send it
+ *-----------------------------------------------------------------------*/
tx[tx_slot].ctrl = (MAL_TX_CTRL_LAST |
- EMAC_TX_CTRL_GFCS | EMAC_TX_CTRL_GP) &
- ~(EMAC_TX_CTRL_ISA | EMAC_TX_CTRL_RSA);
+ EMAC_TX_CTRL_GFCS | EMAC_TX_CTRL_GP) &
+ ~(EMAC_TX_CTRL_ISA | EMAC_TX_CTRL_RSA);
if ((NUM_TX_BUFF - 1) == tx_slot)
tx[tx_slot].ctrl |= MAL_TX_CTRL_WRAP;
packetSent++;
#endif
- /*-----------------------------------------------------------------------+
- | poll unitl the packet is sent and then make sure it is OK
- +-----------------------------------------------------------------------*/
+ /*-----------------------------------------------------------------------+
+ * poll unitl the packet is sent and then make sure it is OK
+ *-----------------------------------------------------------------------*/
time_start = get_timer (0);
while (1) {
temp_txm0 = in32 (EMAC_TXM0);
/*-----------------------------------------------------------------------------+
-| EnetInt.
-| EnetInt is the interrupt handler. It will determine the
-| cause of the interrupt and call the apporpriate servive
-| routine.
-+-----------------------------------------------------------------------------*/
+ * EnetInt.
+ * EnetInt is the interrupt handler. It will determine the
+ * cause of the interrupt and call the apporpriate servive
+ * routine.
+ *-----------------------------------------------------------------------------*/
int enetInt ()
{
int serviced;
}
/*-----------------------------------------------------------------------------+
-| MAL Error Routine
-+-----------------------------------------------------------------------------*/
+ * MAL Error Routine
+ *-----------------------------------------------------------------------------*/
void mal_err (unsigned long isr, unsigned long uic, unsigned long maldef,
- unsigned long mal_errr)
+ unsigned long mal_errr)
{
mtdcr (malesr, isr); /* clear interrupt */
}
/*-----------------------------------------------------------------------------+
-| EMAC Error Routine
-+-----------------------------------------------------------------------------*/
+ * EMAC Error Routine
+ *-----------------------------------------------------------------------------*/
void emac_err (unsigned long isr)
{
printf ("EMAC error occured.... ISR = %lx\n", isr);
}
/*-----------------------------------------------------------------------------+
-| enet_rcv() handles the ethernet receive data
-+-----------------------------------------------------------------------------*/
+ * enet_rcv() handles the ethernet receive data
+ *-----------------------------------------------------------------------------*/
static void enet_rcv (unsigned long malisr)
{
struct enet_frame *ef_ptr;
i = rx_slot;
if ((MAL_RX_CTRL_EMPTY & rx[i].ctrl)
- || (loop_count >= NUM_RX_BUFF))
+ || (loop_count >= NUM_RX_BUFF))
break;
loop_count++;
rx_slot++;
* free receive buffer only when
* buffer has been handled (eth_rx)
rx[i].ctrl |= MAL_RX_CTRL_EMPTY;
- */
+ */
} /* if data_len */
} /* while */
} /* if EMACK_RXCHL */
/*-----------------------------------------------------------------------------+
-|
-| This source code has been made available to you by IBM on an AS-IS
-| basis. Anyone receiving this source is licensed under IBM
-| copyrights to use it in any way he or she deems fit, including
-| copying it, modifying it, compiling it, and redistributing it either
-| with or without modifications. No license under IBM patents or
-| patent applications is to be implied by the copyright license.
-|
-| Any user of this software should understand that IBM cannot provide
-| technical support for this software and will not be responsible for
-| any consequences resulting from the use of this software.
-|
-| Any person who transfers this source code or any derivative work
-| must include the IBM copyright notice, this paragraph, and the
-| preceding two paragraphs in the transferred software.
-|
-| COPYRIGHT I B M CORPORATION 1995
-| LICENSED MATERIAL - PROGRAM PROPERTY OF I B M
-+-----------------------------------------------------------------------------*/
+ *
+ * This source code has been made available to you by IBM on an AS-IS
+ * basis. Anyone receiving this source is licensed under IBM
+ * copyrights to use it in any way he or she deems fit, including
+ * copying it, modifying it, compiling it, and redistributing it either
+ * with or without modifications. No license under IBM patents or
+ * patent applications is to be implied by the copyright license.
+ *
+ * Any user of this software should understand that IBM cannot provide
+ * technical support for this software and will not be responsible for
+ * any consequences resulting from the use of this software.
+ *
+ * Any person who transfers this source code or any derivative work
+ * must include the IBM copyright notice, this paragraph, and the
+ * preceding two paragraphs in the transferred software.
+ *
+ * COPYRIGHT I B M CORPORATION 1995
+ * LICENSED MATERIAL - PROGRAM PROPERTY OF I B M
+ *-----------------------------------------------------------------------------*/
/*----------------------------------------------------------------------------+
-|
-| File Name: 405gp_pci.c
-|
-| Function: Initialization code for the 405GP PCI Configuration regs.
-|
-| Author: Mark Game
-|
-| Change Activity-
-|
-| Date Description of Change BY
-| --------- --------------------- ---
-| 09-Sep-98 Created MCG
-| 02-Nov-98 Removed External arbiter selected message JWB
-| 27-Nov-98 Zero out PTMBAR2 and disable in PTM2MS JWB
-| 04-Jan-99 Zero out other unused PMM and PTM regs. Change bus scan MCG
-| from (0 to n) to (1 to n).
-| 17-May-99 Port to Walnut JWB
-| 17-Jun-99 Updated for VGA support JWB
-| 21-Jun-99 Updated to allow SRAM region to be a target from PCI bus JWB
-| 19-Jul-99 Updated for 405GP pass 1 errata #26 (Low PCI subsequent MCG
-| target latency timer values are not supported).
-| Should be fixed in pass 2.
-| 09-Sep-99 Removed use of PTM2 since the SRAM region no longer needs JWB
-| to be a PCI target. Zero out PTMBAR2 and disable in PTM2MS.
-| 10-Dec-99 Updated PCI_Write_CFG_Reg for pass2 errata #6 JWB
-| 11-Jan-00 Ensure PMMxMAs disabled before setting PMMxLAs. This is not
-| really required after a reset since PMMxMAs are already
-| disabled but is a good practice nonetheless. JWB
-| 12-Jun-01 stefan.roese@esd-electronics.com
-| - PCI host/adapter handling reworked
-| 09-Jul-01 stefan.roese@esd-electronics.com
-| - PCI host now configures from device 0 (not 1) to max_dev,
-| (host configures itself)
-| - On CPCI-405 pci base address and size is generated from
-| SDRAM and FLASH size (CFG regs not used anymore)
-| - Some minor changes for CPCI-405-A (adapter version)
-| 14-Sep-01 stefan.roese@esd-electronics.com
-| - CONFIG_PCI_SCAN_SHOW added to print pci devices upon startup
-| 28-Sep-01 stefan.roese@esd-electronics.com
-| - Changed pci master configuration for linux compatibility
-| (no need for bios_fixup() anymore)
-| 26-Feb-02 stefan.roese@esd-electronics.com
-| - Bug fixed in pci configuration (Andrew May)
-| - Removed pci class code init for CPCI405 board
-| 15-May-02 stefan.roese@esd-electronics.com
-| - New vga device handling
-| 29-May-02 stefan.roese@esd-electronics.com
-| - PCI class code init added (if defined)
-+----------------------------------------------------------------------------*/
+ *
+ * File Name: 405gp_pci.c
+ *
+ * Function: Initialization code for the 405GP PCI Configuration regs.
+ *
+ * Author: Mark Game
+ *
+ * Change Activity-
+ *
+ * Date Description of Change BY
+ * --------- --------------------- ---
+ * 09-Sep-98 Created MCG
+ * 02-Nov-98 Removed External arbiter selected message JWB
+ * 27-Nov-98 Zero out PTMBAR2 and disable in PTM2MS JWB
+ * 04-Jan-99 Zero out other unused PMM and PTM regs. Change bus scan MCG
+ * from (0 to n) to (1 to n).
+ * 17-May-99 Port to Walnut JWB
+ * 17-Jun-99 Updated for VGA support JWB
+ * 21-Jun-99 Updated to allow SRAM region to be a target from PCI bus JWB
+ * 19-Jul-99 Updated for 405GP pass 1 errata #26 (Low PCI subsequent MCG
+ * target latency timer values are not supported).
+ * Should be fixed in pass 2.
+ * 09-Sep-99 Removed use of PTM2 since the SRAM region no longer needs JWB
+ * to be a PCI target. Zero out PTMBAR2 and disable in PTM2MS.
+ * 10-Dec-99 Updated PCI_Write_CFG_Reg for pass2 errata #6 JWB
+ * 11-Jan-00 Ensure PMMxMAs disabled before setting PMMxLAs. This is not
+ * really required after a reset since PMMxMAs are already
+ * disabled but is a good practice nonetheless. JWB
+ * 12-Jun-01 stefan.roese@esd-electronics.com
+ * - PCI host/adapter handling reworked
+ * 09-Jul-01 stefan.roese@esd-electronics.com
+ * - PCI host now configures from device 0 (not 1) to max_dev,
+ * (host configures itself)
+ * - On CPCI-405 pci base address and size is generated from
+ * SDRAM and FLASH size (CFG regs not used anymore)
+ * - Some minor changes for CPCI-405-A (adapter version)
+ * 14-Sep-01 stefan.roese@esd-electronics.com
+ * - CONFIG_PCI_SCAN_SHOW added to print pci devices upon startup
+ * 28-Sep-01 stefan.roese@esd-electronics.com
+ * - Changed pci master configuration for linux compatibility
+ * (no need for bios_fixup() anymore)
+ * 26-Feb-02 stefan.roese@esd-electronics.com
+ * - Bug fixed in pci configuration (Andrew May)
+ * - Removed pci class code init for CPCI405 board
+ * 15-May-02 stefan.roese@esd-electronics.com
+ * - New vga device handling
+ * 29-May-02 stefan.roese@esd-electronics.com
+ * - PCI class code init added (if defined)
+ *----------------------------------------------------------------------------*/
#include <ppcboot.h>
#include <command.h>
#include <asm/processor.h>
#include <pci.h>
-#ifdef CONFIG_405GP
+#if defined(CONFIG_405GP) || defined(CONFIG_440)
#ifdef CONFIG_PCI
/*#define DEBUG*/
/*-----------------------------------------------------------------------------+
-| pci_init. Initializes the 405GP PCI Configuration regs.
-+-----------------------------------------------------------------------------*/
+ * pci_init. Initializes the 405GP PCI Configuration regs.
+ *-----------------------------------------------------------------------------*/
void pci_405gp_init(bd_t *bd, struct pci_controller *hose)
{
- int i, reg_num = 0;
- unsigned short temp_short;
- unsigned long ptmpcila[2] = {CFG_PCI_PTM1PCI, CFG_PCI_PTM2PCI};
+ int i, reg_num = 0;
+ unsigned short temp_short;
+ unsigned long ptmpcila[2] = {CFG_PCI_PTM1PCI, CFG_PCI_PTM2PCI};
#if defined(CONFIG_CPCI405)
- unsigned long ptmla[2] = {bd->bi_memstart, bd->bi_flashstart};
- unsigned long ptmms[2] = {~(bd->bi_memsize - 1) | 1, ~(bd->bi_flashsize - 1) | 1};
+ unsigned long ptmla[2] = {bd->bi_memstart, bd->bi_flashstart};
+ unsigned long ptmms[2] = {~(bd->bi_memsize - 1) | 1, ~(bd->bi_flashsize - 1) | 1};
#else
- unsigned long ptmla[2] = {CFG_PCI_PTM1LA, CFG_PCI_PTM2LA};
- unsigned long ptmms[2] = {CFG_PCI_PTM1MS, CFG_PCI_PTM2MS};
+ unsigned long ptmla[2] = {CFG_PCI_PTM1LA, CFG_PCI_PTM2LA};
+ unsigned long ptmms[2] = {CFG_PCI_PTM1MS, CFG_PCI_PTM2MS};
#endif
#if defined(CONFIG_PIP405) || defined (CONFIG_MIP405)
- unsigned long pmmla[3] = {0x80000000, 0xA0000000, 0};
- unsigned long pmmma[3] = {0xE0000001, 0xE0000001, 0};
- unsigned long pmmpcila[3] = {0x80000000, 0x00000000, 0};
- unsigned long pmmpciha[3] = {0x00000000, 0x00000000, 0};
+ unsigned long pmmla[3] = {0x80000000, 0xA0000000, 0};
+ unsigned long pmmma[3] = {0xE0000001, 0xE0000001, 0};
+ unsigned long pmmpcila[3] = {0x80000000, 0x00000000, 0};
+ unsigned long pmmpciha[3] = {0x00000000, 0x00000000, 0};
#else
- unsigned long pmmla[3] = {0x80000000, 0,0};
- unsigned long pmmma[3] = {0xC0000001, 0,0};
- unsigned long pmmpcila[3] = {0x80000000, 0,0};
- unsigned long pmmpciha[3] = {0x00000000, 0,0};
+ unsigned long pmmla[3] = {0x80000000, 0,0};
+ unsigned long pmmma[3] = {0xC0000001, 0,0};
+ unsigned long pmmpcila[3] = {0x80000000, 0,0};
+ unsigned long pmmpciha[3] = {0x00000000, 0,0};
#endif
- /*
- * Register the hose
- */
- hose->first_busno = 0;
- hose->last_busno = 0xff;
-
- /* ISA/PCI I/O space */
- pci_set_region(hose->regions + reg_num++,
- MIN_PCI_PCI_IOADDR,
- MIN_PLB_PCI_IOADDR,
- 0x10000,
- PCI_REGION_IO);
-
- /* PCI I/O space */
- pci_set_region(hose->regions + reg_num++,
- 0x00800000,
- 0xe8800000,
- 0x03800000,
- PCI_REGION_IO);
-
- reg_num = 2;
-
- /* Memory spaces */
- for (i=0; i<2; i++)
- if (ptmms[i] & 1)
- {
- if (!i) hose->pci_fb = hose->regions + reg_num;
+ /*
+ * Register the hose
+ */
+ hose->first_busno = 0;
+ hose->last_busno = 0xff;
+ /* ISA/PCI I/O space */
pci_set_region(hose->regions + reg_num++,
- ptmpcila[i], ptmla[i],
- ~(ptmms[i] & 0xfffff000) + 1,
- PCI_REGION_MEM |
- PCI_REGION_MEMORY);
- }
-
- /* PCI memory spaces */
- for (i=0; i<3; i++)
- if (pmmma[i] & 1)
- {
+ MIN_PCI_PCI_IOADDR,
+ MIN_PLB_PCI_IOADDR,
+ 0x10000,
+ PCI_REGION_IO);
+
+ /* PCI I/O space */
pci_set_region(hose->regions + reg_num++,
- pmmpcila[i], pmmla[i],
- ~(pmmma[i] & 0xfffff000) + 1,
- PCI_REGION_MEM);
- }
-
- hose->region_count = reg_num;
-
- pci_setup_indirect(hose,
- PCICFGADR,
- PCICFGDATA);
-
- if (hose->pci_fb)
- pciauto_region_init(hose->pci_fb);
-
- pci_register_hose(hose);
-
- /*--------------------------------------------------------------------------+
- | 405GP PCI Master configuration.
- | Map one 512 MB range of PLB/processor addresses to PCI memory space.
- | PLB address 0x80000000-0xBFFFFFFF ==> PCI address 0x80000000-0xBFFFFFFF
- | Use byte reversed out routines to handle endianess.
- +--------------------------------------------------------------------------*/
- out32r(PMM0MA, pmmma[0]); /* ensure disabled b4 setting PMM0LA */
- out32r(PMM0LA, pmmla[0]);
- out32r(PMM0PCILA, pmmpcila[0]);
- out32r(PMM0PCIHA, pmmpciha[0]);
- out32r(PMM0MA, pmmma[0]);
-
- /*--------------------------------------------------------------------------+
- | PMM1 is not used. Initialize them to zero.
- +--------------------------------------------------------------------------*/
- out32r(PMM1MA, pmmma[1]); /* ensure disabled b4 setting PMM2LA */
- out32r(PMM1LA, pmmla[1]);
- out32r(PMM1PCILA, pmmpcila[1]);
- out32r(PMM1PCIHA, pmmpciha[1]);
- out32r(PMM1MA, pmmma[1]);
-
- /*--------------------------------------------------------------------------+
- | PMM2 is not used. Initialize them to zero.
- +--------------------------------------------------------------------------*/
- out32r(PMM2MA, pmmma[2]); /* ensure disabled b4 setting PMM2LA */
- out32r(PMM2LA, pmmla[2]);
- out32r(PMM2PCILA, pmmpcila[2]);
- out32r(PMM2PCIHA, pmmpciha[2]);
- out32r(PMM2MA, pmmma[2]);
-
- /*--------------------------------------------------------------------------+
- | 405GP PCI Target configuration. (PTM1)
- | Note: PTM1MS is hardwire enabled but we set the enable bit anyway.
- +--------------------------------------------------------------------------*/
- out32r(PTM1LA, ptmla[0]); /* insert address */
- out32r(PTM1MS, ptmms[0]); /* insert size, enable bit is 1 */
-
- /*--------------------------------------------------------------------------+
- | 405GP PCI Target configuration. (PTM2)
- +--------------------------------------------------------------------------*/
- out32r(PTM2LA, ptmla[1]); /* insert address */
- if (ptmms[1] == 0)
- {
- out32r(PTM2MS, 0x00000001); /* set enable bit */
- pci_write_config_dword(PCIDEVID_405GP, PCI_BASE_ADDRESS_2, 0x00000000);
- out32r(PTM2MS, 0x00000000); /* disable */
- }
- else
- {
- out32r(PTM2MS, ptmms[1]); /* insert size, enable bit is 1 */
- }
-
- /*
- * Insert Subsystem Vendor and Device ID
- */
- pci_write_config_word(PCIDEVID_405GP, PCI_SUBSYSTEM_VENDOR_ID, CFG_PCI_SUBSYS_VENDORID);
+ 0x00800000,
+ 0xe8800000,
+ 0x03800000,
+ PCI_REGION_IO);
+
+ reg_num = 2;
+
+ /* Memory spaces */
+ for (i=0; i<2; i++)
+ if (ptmms[i] & 1)
+ {
+ if (!i) hose->pci_fb = hose->regions + reg_num;
+
+ pci_set_region(hose->regions + reg_num++,
+ ptmpcila[i], ptmla[i],
+ ~(ptmms[i] & 0xfffff000) + 1,
+ PCI_REGION_MEM |
+ PCI_REGION_MEMORY);
+ }
+
+ /* PCI memory spaces */
+ for (i=0; i<3; i++)
+ if (pmmma[i] & 1)
+ {
+ pci_set_region(hose->regions + reg_num++,
+ pmmpcila[i], pmmla[i],
+ ~(pmmma[i] & 0xfffff000) + 1,
+ PCI_REGION_MEM);
+ }
+
+ hose->region_count = reg_num;
+
+ pci_setup_indirect(hose,
+ PCICFGADR,
+ PCICFGDATA);
+
+ if (hose->pci_fb)
+ pciauto_region_init(hose->pci_fb);
+
+ pci_register_hose(hose);
+
+ /*--------------------------------------------------------------------------+
+ * 405GP PCI Master configuration.
+ * Map one 512 MB range of PLB/processor addresses to PCI memory space.
+ * PLB address 0x80000000-0xBFFFFFFF ==> PCI address 0x80000000-0xBFFFFFFF
+ * Use byte reversed out routines to handle endianess.
+ *--------------------------------------------------------------------------*/
+ out32r(PMM0MA, pmmma[0]); /* ensure disabled b4 setting PMM0LA */
+ out32r(PMM0LA, pmmla[0]);
+ out32r(PMM0PCILA, pmmpcila[0]);
+ out32r(PMM0PCIHA, pmmpciha[0]);
+ out32r(PMM0MA, pmmma[0]);
+
+ /*--------------------------------------------------------------------------+
+ * PMM1 is not used. Initialize them to zero.
+ *--------------------------------------------------------------------------*/
+ out32r(PMM1MA, pmmma[1]); /* ensure disabled b4 setting PMM2LA */
+ out32r(PMM1LA, pmmla[1]);
+ out32r(PMM1PCILA, pmmpcila[1]);
+ out32r(PMM1PCIHA, pmmpciha[1]);
+ out32r(PMM1MA, pmmma[1]);
+
+ /*--------------------------------------------------------------------------+
+ * PMM2 is not used. Initialize them to zero.
+ *--------------------------------------------------------------------------*/
+ out32r(PMM2MA, pmmma[2]); /* ensure disabled b4 setting PMM2LA */
+ out32r(PMM2LA, pmmla[2]);
+ out32r(PMM2PCILA, pmmpcila[2]);
+ out32r(PMM2PCIHA, pmmpciha[2]);
+ out32r(PMM2MA, pmmma[2]);
+
+ /*--------------------------------------------------------------------------+
+ * 405GP PCI Target configuration. (PTM1)
+ * Note: PTM1MS is hardwire enabled but we set the enable bit anyway.
+ *--------------------------------------------------------------------------*/
+ out32r(PTM1LA, ptmla[0]); /* insert address */
+ out32r(PTM1MS, ptmms[0]); /* insert size, enable bit is 1 */
+
+ /*--------------------------------------------------------------------------+
+ * 405GP PCI Target configuration. (PTM2)
+ *--------------------------------------------------------------------------*/
+ out32r(PTM2LA, ptmla[1]); /* insert address */
+ if (ptmms[1] == 0)
+ {
+ out32r(PTM2MS, 0x00000001); /* set enable bit */
+ pci_write_config_dword(PCIDEVID_405GP, PCI_BASE_ADDRESS_2, 0x00000000);
+ out32r(PTM2MS, 0x00000000); /* disable */
+ }
+ else
+ {
+ out32r(PTM2MS, ptmms[1]); /* insert size, enable bit is 1 */
+ }
+
+ /*
+ * Insert Subsystem Vendor and Device ID
+ */
+ pci_write_config_word(PCIDEVID_405GP, PCI_SUBSYSTEM_VENDOR_ID, CFG_PCI_SUBSYS_VENDORID);
#ifdef CONFIG_CPCI405
- if (mfdcr(strap) & PSR_PCI_ARBIT_EN)
- pci_write_config_word(PCIDEVID_405GP, PCI_SUBSYSTEM_ID, CFG_PCI_SUBSYS_DEVICEID);
- else
- pci_write_config_word(PCIDEVID_405GP, PCI_SUBSYSTEM_ID, CFG_PCI_SUBSYS_DEVICEID2);
+ if (mfdcr(strap) & PSR_PCI_ARBIT_EN)
+ pci_write_config_word(PCIDEVID_405GP, PCI_SUBSYSTEM_ID, CFG_PCI_SUBSYS_DEVICEID);
+ else
+ pci_write_config_word(PCIDEVID_405GP, PCI_SUBSYSTEM_ID, CFG_PCI_SUBSYS_DEVICEID2);
#else
- pci_write_config_word(PCIDEVID_405GP, PCI_SUBSYSTEM_ID, CFG_PCI_SUBSYS_DEVICEID);
+ pci_write_config_word(PCIDEVID_405GP, PCI_SUBSYSTEM_ID, CFG_PCI_SUBSYS_DEVICEID);
#endif
- /*
- * Insert Class-code
- */
+ /*
+ * Insert Class-code
+ */
#ifdef CFG_PCI_CLASSCODE
- pci_write_config_word(PCIDEVID_405GP, PCI_CLASS_SUB_CODE, CFG_PCI_CLASSCODE);
+ pci_write_config_word(PCIDEVID_405GP, PCI_CLASS_SUB_CODE, CFG_PCI_CLASSCODE);
#endif /* CFG_PCI_CLASSCODE */
- /*--------------------------------------------------------------------------+
- | If PCI speed = 66Mhz, set 66Mhz capable bit.
- +--------------------------------------------------------------------------*/
- if (bd->bi_pci_busfreq >= 66000000) {
- pci_read_config_word(PCIDEVID_405GP, PCI_STATUS, &temp_short);
- pci_write_config_word(PCIDEVID_405GP,PCI_STATUS,(temp_short|PCI_STATUS_66MHZ));
- }
+ /*--------------------------------------------------------------------------+
+ * If PCI speed = 66Mhz, set 66Mhz capable bit.
+ *--------------------------------------------------------------------------*/
+ if (bd->bi_pci_busfreq >= 66000000) {
+ pci_read_config_word(PCIDEVID_405GP, PCI_STATUS, &temp_short);
+ pci_write_config_word(PCIDEVID_405GP,PCI_STATUS,(temp_short|PCI_STATUS_66MHZ));
+ }
#if (CONFIG_PCI_HOST != PCI_HOST_ADAPTER)
#if (CONFIG_PCI_HOSE == PCI_HOST_AUTO)
- if (mfdcr(strap) & PSR_PCI_ARBIT_EN)
+ if (mfdcr(strap) & PSR_PCI_ARBIT_EN)
#endif
- {
- /*--------------------------------------------------------------------------+
- | Write the 405GP PCI Configuration regs.
- | Enable 405GP to be a master on the PCI bus (PMM).
- | Enable 405GP to act as a PCI memory target (PTM).
- +--------------------------------------------------------------------------*/
- pci_read_config_word(PCIDEVID_405GP, PCI_COMMAND, &temp_short);
- pci_write_config_word(PCIDEVID_405GP, PCI_COMMAND, temp_short |
- PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY);
- }
+ {
+ /*--------------------------------------------------------------------------+
+ * Write the 405GP PCI Configuration regs.
+ * Enable 405GP to be a master on the PCI bus (PMM).
+ * Enable 405GP to act as a PCI memory target (PTM).
+ *--------------------------------------------------------------------------*/
+ pci_read_config_word(PCIDEVID_405GP, PCI_COMMAND, &temp_short);
+ pci_write_config_word(PCIDEVID_405GP, PCI_COMMAND, temp_short |
+ PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY);
+ }
#endif
- /*
- * Set HCE bit (Host Configuration Enabled)
- */
- pci_read_config_word(PCIDEVID_405GP, PCIBRDGOPT2, &temp_short);
- pci_write_config_word(PCIDEVID_405GP, PCIBRDGOPT2, (temp_short | 0x0001));
+ /*
+ * Set HCE bit (Host Configuration Enabled)
+ */
+ pci_read_config_word(PCIDEVID_405GP, PCIBRDGOPT2, &temp_short);
+ pci_write_config_word(PCIDEVID_405GP, PCIBRDGOPT2, (temp_short | 0x0001));
#ifdef CONFIG_PCI_PNP
- /*--------------------------------------------------------------------------+
- | Scan the PCI bus and configure devices found.
- +--------------------------------------------------------------------------*/
+ /*--------------------------------------------------------------------------+
+ * Scan the PCI bus and configure devices found.
+ *--------------------------------------------------------------------------*/
#if (CONFIG_PCI_HOST == PCI_HOST_AUTO)
- if (mfdcr(strap) & PSR_PCI_ARBIT_EN)
+ if (mfdcr(strap) & PSR_PCI_ARBIT_EN)
#endif
- {
+ {
#ifdef CONFIG_PCI_SCAN_SHOW
- printf("PCI: Bus Dev VenId DevId Class Int\n");
+ printf("PCI: Bus Dev VenId DevId Class Int\n");
#endif
- hose->last_busno = pci_hose_scan(hose);
- }
+ hose->last_busno = pci_hose_scan(hose);
+ }
#endif /* CONFIG_PCI_PNP */
}
* as has happened before.
*/
void pci_405gp_setup_bridge(struct pci_controller *hose, pci_dev_t dev,
- struct pci_config_table *entry)
+ struct pci_config_table *entry)
{
#ifdef DEBUG
printf("405gp_setup_bridge\n");
void pci_405gp_fixup_irq(struct pci_controller *hose, pci_dev_t dev)
{
- unsigned char int_line = 0xff;
-
- /*
- * Write pci interrupt line register (cpci405 specific)
- */
- switch (PCI_DEV(dev) & 0x03)
- {
- case 0:
- int_line = 27 + 2;
- break;
- case 1:
- int_line = 27 + 3;
- break;
- case 2:
- int_line = 27 + 0;
- break;
- case 3:
- int_line = 27 + 1;
- break;
- }
-
- pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, int_line);
+ unsigned char int_line = 0xff;
+
+ /*
+ * Write pci interrupt line register (cpci405 specific)
+ */
+ switch (PCI_DEV(dev) & 0x03)
+ {
+ case 0:
+ int_line = 27 + 2;
+ break;
+ case 1:
+ int_line = 27 + 3;
+ break;
+ case 2:
+ int_line = 27 + 0;
+ break;
+ case 3:
+ int_line = 27 + 1;
+ break;
+ }
+
+ pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, int_line);
}
void pci_405gp_setup_vga(struct pci_controller *hose, pci_dev_t dev,
struct pci_config_table *entry)
{
- unsigned int cmdstat = 0;
+ unsigned int cmdstat = 0;
- pciauto_setup_device(hose, dev, 6, hose->pci_mem, hose->pci_io);
+ pciauto_setup_device(hose, dev, 6, hose->pci_mem, hose->pci_io);
- /* always enable io space on vga boards */
- pci_hose_read_config_dword(hose, dev, PCI_COMMAND, &cmdstat);
- cmdstat |= PCI_COMMAND_IO;
- pci_hose_write_config_dword(hose, dev, PCI_COMMAND, cmdstat);
+ /* always enable io space on vga boards */
+ pci_hose_read_config_dword(hose, dev, PCI_COMMAND, &cmdstat);
+ cmdstat |= PCI_COMMAND_IO;
+ pci_hose_write_config_dword(hose, dev, PCI_COMMAND, cmdstat);
}
#if !(defined(CONFIG_PIP405) || defined (CONFIG_MIP405))
/*
*As is these functs get called out of flash Not a horrible
*thing, but something to keep in mind. (no statics?)
-*/
+ */
static struct pci_config_table pci_405gp_config_table[] = {
/*if VendID is 0 it terminates the table search (ie Walnut)*/
#if CFG_PCI_SUBSYS_VENDORID
- {CFG_PCI_SUBSYS_VENDORID, PCI_ANY_ID, PCI_CLASS_BRIDGE_HOST,
- PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, pci_405gp_setup_bridge},
+ {CFG_PCI_SUBSYS_VENDORID, PCI_ANY_ID, PCI_CLASS_BRIDGE_HOST,
+ PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, pci_405gp_setup_bridge},
#endif
- {PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_DISPLAY_VGA,
- PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, pci_405gp_setup_vga},
+ {PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_DISPLAY_VGA,
+ PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, pci_405gp_setup_vga},
- {PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_NOT_DEFINED_VGA,
- PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, pci_405gp_setup_vga},
+ {PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_NOT_DEFINED_VGA,
+ PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, pci_405gp_setup_vga},
- { }
+ { }
};
static struct pci_controller hose = {
- fixup_irq: pci_405gp_fixup_irq,
- config_table: pci_405gp_config_table,
+ fixup_irq: pci_405gp_fixup_irq,
+ config_table: pci_405gp_config_table,
};
void pci_init(bd_t *bd)
{
- /*we want the ptrs to RAM not flash (ie don't use init list)*/
- hose.fixup_irq = pci_405gp_fixup_irq;
- hose.config_table = pci_405gp_config_table;
- pci_405gp_init(bd, &hose);
+ /*we want the ptrs to RAM not flash (ie don't use init list)*/
+ hose.fixup_irq = pci_405gp_fixup_irq;
+ hose.config_table = pci_405gp_config_table;
+ pci_405gp_init(bd, &hose);
}
#endif
#endif
#if CONFIG_405CR
puts("IBM PowerPC 405CR Rev. ");
-#endif
-#if CONFIG_440GP
- puts("IBM PowerPC 440GP Rev. ");
#endif
switch (pvr) {
case PVR_405GP_RB:
printf(" %u kB D-Cache", 2);
#endif
+#if defined(CONFIG_440)
+ puts("IBM PowerPC 440 Rev. ");
+ switch(pvr)
+ {
+ case PVR_440GP_RB:
+ putc('B');
+ break;
+ case PVR_440GP_RC:
+ putc('C');
+ break;
+ default:
+ printf("UNKNOWN (PVR=%08x)", pvr);
+ break;
+ }
+#endif
+
printf("\n");
return 0;
*/
unsigned long get_tbclk (void)
{
+#if defined(CONFIG_440)
+ /* FIXME: This should be done like 405GP */
+ return(400 * 1000 * 1000 ); /* Assume 400 MHz for now */
+#endif
+
#if defined(CONFIG_405GP) || defined(CONFIG_405CR)
PPC405_SYS_INFO sys_info;
#ifdef CONFIG_IOP480
return (66000000);
#endif /* CONFIG_IOP480 */
+
}
void
cpu_init_f (void)
{
- /*
- * External Bus Controller (EBC) Setup
- */
+ /*
+ * External Bus Controller (EBC) Setup
+ */
#if (defined(CFG_EBC_PB0AP) && defined(CFG_EBC_PB0CR))
- /*
- * Move the next instructions into icache, since these modify the flash
- * we are running from!
- */
- asm volatile(" bl 0f" ::: "lr");
- asm volatile("0: mflr 3" ::: "r3");
- asm volatile(" addi 4, 0, 14" ::: "r4");
- asm volatile(" mtctr 4" ::: "ctr");
- asm volatile("1: icbt 0, 3");
- asm volatile(" addi 3, 3, 32" ::: "r3");
- asm volatile(" bdnz 1b" ::: "ctr", "cr0");
- asm volatile(" addis 3, 0, 0x0" ::: "r3");
- asm volatile(" ori 3, 3, 0xA000" ::: "r3");
- asm volatile(" mtctr 3" ::: "ctr");
- asm volatile("2: bdnz 2b" ::: "ctr", "cr0");
-
- mtebc(pb0ap, CFG_EBC_PB0AP);
- mtebc(pb0cr, CFG_EBC_PB0CR);
+ /*
+ * Move the next instructions into icache, since these modify the flash
+ * we are running from!
+ */
+ asm volatile(" bl 0f" ::: "lr");
+ asm volatile("0: mflr 3" ::: "r3");
+ asm volatile(" addi 4, 0, 14" ::: "r4");
+ asm volatile(" mtctr 4" ::: "ctr");
+ asm volatile("1: icbt 0, 3");
+ asm volatile(" addi 3, 3, 32" ::: "r3");
+ asm volatile(" bdnz 1b" ::: "ctr", "cr0");
+ asm volatile(" addis 3, 0, 0x0" ::: "r3");
+ asm volatile(" ori 3, 3, 0xA000" ::: "r3");
+ asm volatile(" mtctr 3" ::: "ctr");
+ asm volatile("2: bdnz 2b" ::: "ctr", "cr0");
+
+ mtebc(pb0ap, CFG_EBC_PB0AP);
+ mtebc(pb0cr, CFG_EBC_PB0CR);
#endif
#if (defined(CFG_EBC_PB1AP) && defined(CFG_EBC_PB1CR))
- mtebc(pb1ap, CFG_EBC_PB1AP);
- mtebc(pb1cr, CFG_EBC_PB1CR);
+ mtebc(pb1ap, CFG_EBC_PB1AP);
+ mtebc(pb1cr, CFG_EBC_PB1CR);
#endif
#if (defined(CFG_EBC_PB2AP) && defined(CFG_EBC_PB2CR))
- mtebc(pb2ap, CFG_EBC_PB2AP);
- mtebc(pb2cr, CFG_EBC_PB2CR);
+ mtebc(pb2ap, CFG_EBC_PB2AP);
+ mtebc(pb2cr, CFG_EBC_PB2CR);
#endif
#if (defined(CFG_EBC_PB3AP) && defined(CFG_EBC_PB3CR))
- mtebc(pb3ap, CFG_EBC_PB3AP);
- mtebc(pb3cr, CFG_EBC_PB3CR);
+ mtebc(pb3ap, CFG_EBC_PB3AP);
+ mtebc(pb3cr, CFG_EBC_PB3CR);
#endif
#if (defined(CFG_EBC_PB4AP) && defined(CFG_EBC_PB4CR))
- mtebc(pb4ap, CFG_EBC_PB4AP);
- mtebc(pb4cr, CFG_EBC_PB4CR);
+ mtebc(pb4ap, CFG_EBC_PB4AP);
+ mtebc(pb4cr, CFG_EBC_PB4CR);
#endif
#if (defined(CFG_EBC_PB5AP) && defined(CFG_EBC_PB5CR))
- mtebc(pb5ap, CFG_EBC_PB5AP);
- mtebc(pb5cr, CFG_EBC_PB5CR);
+ mtebc(pb5ap, CFG_EBC_PB5AP);
+ mtebc(pb5cr, CFG_EBC_PB5CR);
#endif
#if (defined(CFG_EBC_PB6AP) && defined(CFG_EBC_PB6CR))
- mtebc(pb6ap, CFG_EBC_PB6AP);
- mtebc(pb6cr, CFG_EBC_PB6CR);
+ mtebc(pb6ap, CFG_EBC_PB6AP);
+ mtebc(pb6cr, CFG_EBC_PB6CR);
#endif
#if (defined(CFG_EBC_PB7AP) && defined(CFG_EBC_PB7CR))
- mtebc(pb7ap, CFG_EBC_PB7AP);
- mtebc(pb7cr, CFG_EBC_PB7CR);
+ mtebc(pb7ap, CFG_EBC_PB7AP);
+ mtebc(pb7cr, CFG_EBC_PB7CR);
#endif
#if defined(CONFIG_WATCHDOG)
- unsigned long val;
+ unsigned long val;
- val = mfspr(tcr);
- val |= 0xf0000000; /* generate system reset after 2.684 seconds */
- mtspr(tcr, val);
+ val = mfspr(tcr);
+ val |= 0xf0000000; /* generate system reset after 2.684 seconds */
+ mtspr(tcr, val);
- val = mfspr(tsr);
- val |= 0x80000000; /* enable watchdog timer */
- mtspr(tsr, val);
+ val = mfspr(tsr);
+ val |= 0x80000000; /* enable watchdog timer */
+ mtspr(tsr, val);
- reset_4xx_watchdog();
+ reset_4xx_watchdog();
#endif /* CONFIG_WATCHDOG */
}
cpu_init_r (bd_t *bd)
{
#ifdef CONFIG_405GP
- unsigned long reg;
-
- /*
- * Write Ethernetaddress into on-chip register
- */
- reg = 0x00000000;
- reg |= bd->bi_enetaddr[0]; /* set high address */
- reg = reg << 8;
- reg |= bd->bi_enetaddr[1];
- out32 (EMAC_IAH, reg);
-
- reg = 0x00000000;
- reg |= bd->bi_enetaddr[2]; /* set low address */
- reg = reg << 8;
- reg |= bd->bi_enetaddr[3];
- reg = reg << 8;
- reg |= bd->bi_enetaddr[4];
- reg = reg << 8;
- reg |= bd->bi_enetaddr[5];
- out32 (EMAC_IAL, reg);
+ unsigned long reg;
+
+ /*
+ * Write Ethernetaddress into on-chip register
+ */
+ reg = 0x00000000;
+ reg |= bd->bi_enetaddr[0]; /* set high address */
+ reg = reg << 8;
+ reg |= bd->bi_enetaddr[1];
+ out32 (EMAC_IAH, reg);
+
+ reg = 0x00000000;
+ reg |= bd->bi_enetaddr[2]; /* set low address */
+ reg = reg << 8;
+ reg |= bd->bi_enetaddr[3];
+ reg = reg << 8;
+ reg |= bd->bi_enetaddr[4];
+ reg = reg << 8;
+ reg |= bd->bi_enetaddr[5];
+ out32 (EMAC_IAL, reg);
#endif /* CONFIG_405GP */
}
#include <ppcboot.h>
#include <ppc4xx.h>
-#include <405gp_i2c.h>
+#if defined(CONFIG_440)
+# include <440_i2c.h>
+#else
+# include <405gp_i2c.h>
+#endif
#include <i2c.h>
#ifdef CONFIG_HARD_I2C
void i2c_init (int speed, int slaveadd)
{
- PPC405_SYS_INFO sysInfo;
+ sys_info_t sysInfo;
unsigned long freqOPB;
int val, divisor;
of data.
udelay(10) is 1 bit time at 100khz
Doubled for slop. 20 is too small.
- */
+ */
i=2*5*8;
do {
/* Get status */
udelay (10);
i--;
} while ((status & IIC_STS_PT) && !(status & IIC_STS_ERR)
- && (i>0));
+ && (i>0));
if (status & IIC_STS_ERR) {
result = IIC_NOK;
for it to hit the front of the FIFO, after that
we can just read. We should check XFCNT here and
if the FIFO is full there is no need to wait.
- */
+ */
udelay (1);
for(j=0;j<bc;j++) {
ptr[tran+j] = in8(IIC_MDBUF);
* (C) Copyright 2000
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
+ * (C) Copyright 2002 (440 port)
+ * Scott McNutt, Artesyn Communication Producs, smcnutt@artsyncp.com
+ *
* See file CREDITS for list of people who contributed to this
* project.
*
#include <ppc4xx.h>
#include <ppc_asm.tmpl>
#include <commproc.h>
+#include "vecnum.h"
/****************************************************************************/
* CPM interrupt vector functions.
*/
struct irq_action {
- interrupt_handler_t *handler;
- void *arg;
- int count;
+ interrupt_handler_t *handler;
+ void *arg;
+ int count;
};
static struct irq_action irq_vecs[32];
+#if defined(CONFIG_440)
+static struct irq_action irq_vecs1[32]; /* For UIC1 */
+
+void uic1_interrupt( void * parms); /* UIC1 handler */
+#endif
+
/****************************************************************************/
static __inline__ unsigned long get_msr(void)
{
- unsigned long msr;
+ unsigned long msr;
- asm volatile("mfmsr %0" : "=r" (msr) :);
- return msr;
+ asm volatile("mfmsr %0" : "=r" (msr) :);
+ return msr;
}
static __inline__ void set_msr(unsigned long msr)
{
- asm volatile("mtmsr %0" : : "r" (msr));
+ asm volatile("mtmsr %0" : : "r" (msr));
}
+#if defined(CONFIG_440)
+
+/* SPRN changed in 440 */
+static __inline__ void set_evpr(unsigned long val)
+{
+ asm volatile("mtspr 0x03f,%0" : : "r" (val));
+}
+
+#else /* !defined(CONFIG_440) */
+
static __inline__ unsigned long get_dec(void)
{
- unsigned long val;
+ unsigned long val;
- asm volatile("mfdec %0" : "=r" (val) :);
- return val;
+ asm volatile("mfdec %0" : "=r" (val) :);
+ return val;
}
static __inline__ void set_dec(unsigned long val)
{
- asm volatile("mtdec %0" : : "r" (val));
+ asm volatile("mtdec %0" : : "r" (val));
}
static __inline__ void set_pit(unsigned long val)
{
- asm volatile("mtpit %0" : : "r" (val));
+ asm volatile("mtpit %0" : : "r" (val));
}
static __inline__ void set_tcr(unsigned long val)
{
- asm volatile("mttcr %0" : : "r" (val));
+ asm volatile("mttcr %0" : : "r" (val));
}
static __inline__ void set_evpr(unsigned long val)
{
- asm volatile("mtevpr %0" : : "r" (val));
+ asm volatile("mtevpr %0" : : "r" (val));
}
+#endif /* defined(CONFIG_440 */
void enable_interrupts (void)
void
interrupt_init (bd_t *bd)
{
- int vec;
- unsigned long val;
-
- /*
- * Mark all irqs as free
- */
- for (vec=0; vec<32; vec++)
- {
- irq_vecs[vec].handler = NULL;
- irq_vecs[vec].arg = NULL;
- irq_vecs[vec].count = 0;
- }
+ int vec;
+ unsigned long val;
+
+ /*
+ * Mark all irqs as free
+ */
+ for (vec=0; vec<32; vec++)
+ {
+ irq_vecs[vec].handler = NULL;
+ irq_vecs[vec].arg = NULL;
+ irq_vecs[vec].count = 0;
+#if defined(CONFIG_440)
+ irq_vecs1[vec].handler = NULL;
+ irq_vecs1[vec].arg = NULL;
+ irq_vecs1[vec].count = 0;
+#endif
+ }
#ifdef CONFIG_4xx
- /*
- * Init PIT
- */
- set_pit(bd->bi_intfreq / 1000);
+ /*
+ * Init PIT
+ */
+#if defined(CONFIG_440)
+ val = mfspr( tcr );
+ val &= (~0x04400000); /* clear DIS & ARE */
+ mtspr( tcr, val );
+ mtspr( dec, 0 ); /* Prevent exception after TSR clear*/
+ mtspr( decar, 0 ); /* clear reload */
+ mtspr( tsr, 0x08000000 ); /* clear DEC status */
+ val = bd->bi_intfreq/1000;
+ mtspr( decar, val ); /* Set auto-reload value */
+ mtspr( dec, val ); /* Set inital val */
+#else
+ set_pit(bd->bi_intfreq / 1000);
+#endif
#endif /* CONFIG_4xx */
#ifdef CONFIG_ADCIOP
- /*
- * Init PIT
- */
- set_pit(66000);
+ /*
+ * Init PIT
+ */
+ set_pit(66000);
#endif
- /*
- * Enable PIT
- */
- val = mfspr(tcr);
- val |= 0x04400000;
- mtspr(tcr, val);
-
- /*
- * Set EVPR to 0
- */
- set_evpr(0x00000000);
-
- /*
- * Enable external interrupts (including PIT)
- */
- set_msr (get_msr() | MSR_EE);
+ /*
+ * Enable PIT
+ */
+#if !defined(CONFIG_440)
+ val = mfspr(tcr);
+ val |= 0x04400000;
+ mtspr(tcr, val);
+#endif
+
+ /*
+ * Set EVPR to 0
+ */
+ set_evpr(0x00000000);
+
+#if defined(CONFIG_440)
+ /* Install the UIC1 handlers */
+ irq_install_handler(VECNUM_UIC1NC, uic1_interrupt, 0);
+ irq_install_handler(VECNUM_UIC1C, uic1_interrupt, 0);
+#endif
+ /*
+ * Enable external interrupts (including PIT)
+ */
+ set_msr (get_msr() | MSR_EE);
}
/****************************************************************************/
*/
void external_interrupt(struct pt_regs *regs)
{
- ulong uic_msr;
- ulong msr_shift;
- int vec;
-
- /*
- * Read masked interrupt status register to determine interrupt source
- */
- uic_msr = mfdcr(uicmsr);
- msr_shift = uic_msr;
- vec = 0;
-
- while (msr_shift != 0)
- {
- if (msr_shift & 0x80000000)
- {
- /*
- * Increment irq counter (for debug purpose only)
- */
- irq_vecs[vec].count++;
-
- if (irq_vecs[vec].handler != NULL)
- (*irq_vecs[vec].handler)(irq_vecs[vec].arg); /* call isr */
- else
- {
- mtdcr(uicer, mfdcr(uicer) & ~(0x80000000 >> vec));
- printf ("Masking bogus interrupt vector 0x%x\n", vec);
- }
-
- /*
- * After servicing the interrupt, we have to remove the status indicator.
- */
- mtdcr(uicsr, (0x80000000 >> vec));
- }
-
- /*
- * Shift msr to next position and increment vector
- */
- msr_shift <<= 1;
- vec++;
- }
+ ulong uic_msr;
+ ulong msr_shift;
+ int vec;
+
+ /*
+ * Read masked interrupt status register to determine interrupt source
+ */
+ uic_msr = mfdcr(uicmsr);
+ msr_shift = uic_msr;
+ vec = 0;
+
+ while (msr_shift != 0)
+ {
+ if (msr_shift & 0x80000000)
+ {
+ /*
+ * Increment irq counter (for debug purpose only)
+ */
+ irq_vecs[vec].count++;
+
+ if (irq_vecs[vec].handler != NULL)
+ (*irq_vecs[vec].handler)(irq_vecs[vec].arg); /* call isr */
+ else
+ {
+ mtdcr(uicer, mfdcr(uicer) & ~(0x80000000 >> vec));
+ printf ("Masking bogus interrupt vector 0x%x\n", vec);
+ }
+
+ /*
+ * After servicing the interrupt, we have to remove the status indicator.
+ */
+ mtdcr(uicsr, (0x80000000 >> vec));
+ }
+
+ /*
+ * Shift msr to next position and increment vector
+ */
+ msr_shift <<= 1;
+ vec++;
+ }
}
+#if defined(CONFIG_440)
+/* Handler for UIC1 interrupt */
+void uic1_interrupt( void * parms)
+{
+ ulong uic1_msr;
+ ulong msr_shift;
+ int vec;
+
+ /*
+ * Read masked interrupt status register to determine interrupt source
+ */
+ uic1_msr = mfdcr(uic1msr);
+ msr_shift = uic1_msr;
+ vec = 0;
+
+ while (msr_shift != 0)
+ {
+ if (msr_shift & 0x80000000)
+ {
+ /*
+ * Increment irq counter (for debug purpose only)
+ */
+ irq_vecs1[vec].count++;
+
+ if (irq_vecs1[vec].handler != NULL)
+ (*irq_vecs1[vec].handler)(irq_vecs1[vec].arg); /* call isr */
+ else
+ {
+ mtdcr(uic1er, mfdcr(uic1er) & ~(0x80000000 >> vec));
+ printf ("Masking bogus interrupt vector (uic1) 0x%x\n", vec);
+ }
+
+ /*
+ * After servicing the interrupt, we have to remove the status indicator.
+ */
+ mtdcr(uic1sr, (0x80000000 >> vec));
+ }
+
+ /*
+ * Shift msr to next position and increment vector
+ */
+ msr_shift <<= 1;
+ vec++;
+ }
+}
+#endif /* defined(CONFIG_440) */
/****************************************************************************/
void
irq_install_handler(int vec, interrupt_handler_t *handler, void *arg)
{
- if (irq_vecs[vec].handler != NULL) {
- printf ("Interrupt vector %d: handler 0x%x replacing 0x%x\n",
- vec, (uint)handler, (uint)irq_vecs[vec].handler);
- }
- irq_vecs[vec].handler = handler;
- irq_vecs[vec].arg = arg;
- mtdcr(uicer, mfdcr(uicer) | (0x80000000 >> vec));
+ struct irq_action *irqa = irq_vecs;
+ int i = vec;
+
+#if defined(CONFIG_440)
+ if (vec > 31) {
+ i = vec - 32;
+ irqa = irq_vecs1;
+ }
+#endif
+
+ if (irqa[i].handler != NULL) {
+ printf ("Interrupt vector %d: handler 0x%x replacing 0x%x\n",
+ vec, (uint)handler, (uint)irqa[i].handler);
+ }
+ irqa[i].handler = handler;
+ irqa[i].arg = arg;
+
+#if defined(CONFIG_440)
+ if( vec > 31 )
+ mtdcr(uic1er, mfdcr(uic1er) | (0x80000000 >> i));
+ else
+#endif
+ mtdcr(uicer, mfdcr(uicer) | (0x80000000 >> i));
#if 0
- printf ("Install interrupt for vector %d ==> %p\n", vec, handler);
+ printf ("Install interrupt for vector %d ==> %p\n", vec, handler);
#endif
}
void
irq_free_handler(int vec)
{
+ struct irq_action *irqa = irq_vecs;
+ int i = vec;
+
+#if defined(CONFIG_440)
+ if (vec > 31) {
+ irqa = irq_vecs1;
+ i = vec - 32;
+ }
+#endif
+
#if 0
- printf ("Free interrupt for vector %d ==> %p\n",
- vec, irq_vecs[vec].handler);
+ printf ("Free interrupt for vector %d ==> %p\n",
+ vec, irq_vecs[vec].handler);
#endif
- mtdcr(uicer, mfdcr(uicer) & ~(0x80000000 >> vec));
- irq_vecs[vec].handler = NULL;
- irq_vecs[vec].arg = NULL;
+
+#if defined(CONFIG_440)
+ if (vec > 31)
+ mtdcr(uic1er, mfdcr(uic1er) & ~(0x80000000 >> i));
+ else
+#endif
+ mtdcr(uicer, mfdcr(uicer) & ~(0x80000000 >> i));
+
+ irqa[i].handler = NULL;
+ irqa[i].arg = NULL;
}
/****************************************************************************/
#if (CONFIG_COMMANDS & CFG_CMD_IRQ)
/*******************************************************************************
-*
-* irqinfo - print information about PCI devices
-*
-*/
+ *
+ * irqinfo - print information about PCI devices
+ *
+ */
int
do_irqinfo(cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[])
{
- int vec;
-
- printf ("\nInterrupt-Information:\n");
- printf ("Nr Routine Arg Count\n");
-
- for (vec=0; vec<32; vec++)
- {
- if (irq_vecs[vec].handler != NULL)
- printf("%02d %08lx %08lx %d\n",
- vec, (ulong)irq_vecs[vec].handler, (ulong)irq_vecs[vec].arg,
- irq_vecs[vec].count);
- }
- return 0;
+ int vec;
+
+ printf ("\nInterrupt-Information:\n");
+#if defined(CONFIG_440)
+ printf ("\nUIC 0\n");
+#endif
+ printf ("Nr Routine Arg Count\n");
+
+ for (vec=0; vec<32; vec++)
+ {
+ if (irq_vecs[vec].handler != NULL)
+ printf("%02d %08lx %08lx %d\n",
+ vec, (ulong)irq_vecs[vec].handler, (ulong)irq_vecs[vec].arg,
+ irq_vecs[vec].count);
+ }
+
+#if defined(CONFIG_440)
+ printf ("\nUIC 1\n");
+ printf ("Nr Routine Arg Count\n");
+
+ for (vec=0; vec<32; vec++)
+ {
+ if (irq_vecs1[vec].handler != NULL)
+ printf("%02d %08lx %08lx %d\n",
+ vec+31, (ulong)irq_vecs1[vec].handler,
+ (ulong)irq_vecs1[vec].arg, irq_vecs1[vec].count);
+ }
+ printf("\n");
+#endif
+ return 0;
}
#include <405_mal.h>
#include <miiphy.h>
-#ifdef CONFIG_405GP
+#if defined(CONFIG_405GP) || defined(CONFIG_440)
/***********************************************************/
// Copyright MontaVista Software Incorporated, 2000
+
.section .resetvec,"ax"
+#if defined(CONFIG_440)
+ b _start_440
+#else
b _start
+#endif
+
#include <commproc.h>
#include <asm/processor.h>
#include <watchdog.h>
+#include "vecnum.h"
#if CONFIG_SERIAL_SOFTWARE_FIFO
#include <malloc.h>
#define spu_TxBuff 0x24 /* Tx data buffer */
/*-----------------------------------------------------------------------------+
-| Line Status Register.
-+-----------------------------------------------------------------------------*/
+ | Line Status Register.
+ +-----------------------------------------------------------------------------*/
#define asyncLSRport1 0x40000000
#define asyncLSRport1set 0x40000004
#define asyncLSRDataReady 0x80
#define asyncLSRTxShiftEmpty 0x02
/*-----------------------------------------------------------------------------+
-| Handshake Status Register.
-+-----------------------------------------------------------------------------*/
+ | Handshake Status Register.
+ +-----------------------------------------------------------------------------*/
#define asyncHSRport1 0x40000008
#define asyncHSRport1set 0x4000000c
#define asyncHSRDsr 0x80
#define asyncLSRCts 0x40
/*-----------------------------------------------------------------------------+
-| Control Register.
-+-----------------------------------------------------------------------------*/
+ | Control Register.
+ +-----------------------------------------------------------------------------*/
#define asyncCRport1 0x40000018
#define asyncCRNormal 0x00
#define asyncCRLoopback 0x40
#define asyncCRDisableDtrRts 0x00
/*-----------------------------------------------------------------------------+
-| Receiver Command Register.
-+-----------------------------------------------------------------------------*/
+ | Receiver Command Register.
+ +-----------------------------------------------------------------------------*/
#define asyncRCRport1 0x4000001c
#define asyncRCRDisable 0x00
#define asyncRCREnable 0x80
#define asyncRCRPauseEnable 0x08
/*-----------------------------------------------------------------------------+
-| Transmitter Command Register.
-+-----------------------------------------------------------------------------*/
+ | Transmitter Command Register.
+ +-----------------------------------------------------------------------------*/
#define asyncTCRport1 0x40000020
#define asyncTCRDisable 0x00
#define asyncTCREnable 0x80
#define asyncTCRBreakGen 0x02
/*-----------------------------------------------------------------------------+
-| Miscellanies defines.
-+-----------------------------------------------------------------------------*/
+ | Miscellanies defines.
+ +-----------------------------------------------------------------------------*/
#define asyncTxBufferport1 0x40000024
#define asyncRxBufferport1 0x40000024
#define asyncDLABLsbport1 0x40000014
/*****************************************************************************/
-#if defined(CONFIG_405GP) || defined(CONFIG_405CR)
-
+#if defined(CONFIG_405GP) || defined(CONFIG_405CR) || defined(CONFIG_440)
+
+#if defined(CONFIG_440)
+#define UART0_BASE CFG_PERIPHERAL_BASE + 0x00000200
+#define UART1_BASE CFG_PERIPHERAL_BASE + 0x00000300
+#define CR0_MASK 0x3fff0000
+#define CR0_EXTCLK_ENA 0x00600000
+#define CR0_UDIV_POS 16
+#else
#define UART_BASE_PTR 0xF800FFFC; /* pointer to uart base */
-
-#define UART0_BASE 0xef600300
-#define UART1_BASE 0xef600400
+#define UART0_BASE 0xef600300
+#define UART1_BASE 0xef600400
+#define CR0_MASK 0x00001fff
+#define CR0_EXTCLK_ENA 0x00000c00
+#define CR0_UDIV_POS 1
+#endif
#define UART_RBR 0x00
#define UART_THR 0x00
#define UART_DLM 0x01
/*-----------------------------------------------------------------------------+
-| Line Status Register.
-+-----------------------------------------------------------------------------*/
+ | Line Status Register.
+ +-----------------------------------------------------------------------------*/
/*#define asyncLSRport1 UART0_BASE+0x05 */
#define asyncLSRDataReady1 0x01
#define asyncLSROverrunError1 0x02
#define asyncLSRRxFifoError1 0x80
/*-----------------------------------------------------------------------------+
-| Miscellanies defines.
-+-----------------------------------------------------------------------------*/
+ | Miscellanies defines.
+ +-----------------------------------------------------------------------------*/
/*#define asyncTxBufferport1 UART0_BASE+0x00 */
/*#define asyncRxBufferport1 UART0_BASE+0x00 */
#if CONFIG_SERIAL_SOFTWARE_FIFO
/*-----------------------------------------------------------------------------+
-| Fifo
-+-----------------------------------------------------------------------------*/
+ | Fifo
+ +-----------------------------------------------------------------------------*/
typedef struct {
char *rx_buffer;
ulong rx_put;
#endif
+#if defined(CONFIG_440) && !defined(CFG_EXT_SERIAL_CLOCK)
+static void serial_divs (int baudrate, unsigned long *pudiv,
+ unsigned short *pbdiv )
+{
+ sys_info_t sysinfo;
+ unsigned long div; /* total divisor udiv * bdiv */
+ unsigned long umin; /* minimum udiv */
+ unsigned short diff; /* smallest diff */
+ unsigned long udiv; /* best udiv */
+
+ unsigned short idiff; /* current diff */
+ unsigned short ibdiv; /* current bdiv */
+ unsigned long i;
+ unsigned long est; /* current estimate */
+
+ get_sys_info( &sysinfo );
+
+ udiv = 32; /* Assume lowest possible serial clk */
+ div = sysinfo.freqPLB/(16*baudrate); /* total divisor */
+ umin = sysinfo.pllOpbDiv<<1; /* 2 x OPB divisor */
+ diff = 32; /* highest possible */
+
+ /* i is the test udiv value -- start with the largest
+ * possible (32) to minimize serial clock and constrain
+ * search to umin.
+ */
+ for( i = 32; i > umin; i-- ){
+ ibdiv = div/i;
+ est = i * ibdiv;
+ idiff = (est > div) ? (est-div) : (div-est);
+ if( idiff == 0 ){
+ udiv = i;
+ break; /* can't do better */
+ }
+ else if( idiff < diff ){
+ udiv = i; /* best so far */
+ diff = idiff; /* update lowest diff*/
+ }
+ }
+
+ *pudiv = udiv;
+ *pbdiv = div/udiv;
+
+}
+#endif /* defined(CONFIG_440) && !defined(CFG_EXT_SERIAL_CLK */
+
+
/*
* Minimal serial functions needed to use one of the SMC ports
* as serial console interface.
*/
+#if defined(CONFIG_440)
+void serial_init (ulong cpu_clock, int baudrate)
+{
+ unsigned long reg;
+ unsigned long tmp;
+ unsigned long udiv;
+ unsigned short bdiv;
+ volatile char val;
+
+ reg = mfdcr(cntrl0) & ~CR0_MASK;
+#ifdef CFG_EXT_SERIAL_CLOCK
+ reg |= CR0_EXTCLK_ENA;
+ udiv = 1;
+ tmp = baudrate * 16;
+ bdiv = (CFG_EXT_SERIAL_CLOCK + tmp / 2) / tmp;
+#else
+ /* For 440, the cpu clock is on divider chain A, UART on divider
+ * chain B ... so cpu clock is irrelevant. Get the "optimized"
+ * values that are subject to the 1/2 opb clock constraint
+ */
+ serial_divs( baudrate, &udiv, &bdiv );
+#endif
+
+ reg |= (udiv - 1) << CR0_UDIV_POS; /* set the UART divisor */
+ mtdcr (cntrl0, reg);
+
+ out8 (UART0_BASE + UART_LCR, 0x80); /* set DLAB bit */
+ out8 (UART0_BASE + UART_DLL, bdiv); /* set baudrate divisor */
+ out8 (UART0_BASE + UART_DLM, bdiv >> 8);/* set baudrate divisor */
+ out8 (UART0_BASE + UART_LCR, 0x03); /* clear DLAB; set 8 bits, no parity */
+ out8 (UART0_BASE + UART_FCR, 0x00); /* disable FIFO */
+ out8 (UART0_BASE + UART_MCR, 0x00); /* no modem control DTR RTS */
+ val = in8 (UART0_BASE + UART_LSR); /* clear line status */
+ val = in8 (UART0_BASE + UART_RBR); /* read receive buffer */
+ out8 (UART0_BASE + UART_SCR, 0x00); /* set scratchpad */
+ out8 (UART0_BASE + UART_IER, 0x00); /* set interrupt enable reg */
+}
+
+#else /* !defined(CONFIG_440) */
+
void serial_init (ulong cpu_clock, int baudrate)
{
unsigned long reg;
unsigned short bdiv;
volatile char val;
- reg = mfdcr (cntrl0) & ~0x1fffUL;
+ reg = mfdcr(cntrl0) & ~CR0_MASK;
#ifdef CFG_EXT_SERIAL_CLOCK
clk = CFG_EXT_SERIAL_CLOCK;
udiv = 1;
- reg |= 0x10c0;
+ reg |= CR0_EXTCLK_ENA;
#else
clk = cpu_clock;
#ifdef CFG_405_UART_ERRATA_59
udiv = (clk + tmp / 2) / tmp;
#endif
#endif
- reg |= (udiv - 1) << 1; /* set the UART divisor */
+
+ reg |= (udiv - 1) << CR0_UDIV_POS; /* set the UART divisor */
mtdcr (cntrl0, reg);
tmp = baudrate * udiv * 16;
out8 (UART0_BASE + UART_IER, 0x00); /* set interrupt enable reg */
}
+#endif /* if defined(CONFIG_440) */
void serial_setbrg (ulong cpu_clock, int baudrate)
{
serial_puts ("WARNING: CTS signal not present on serial port.\n");
}
- irq_install_handler (0 /*UART0 *//*int vec */ ,
- serial_isr /*interrupt_handler_t *handler */ ,
- (void *) &buf_info /*void *arg */ );
+ irq_install_handler ( VECNUM_U0 /*UART0 *//*int vec */ ,
+ serial_isr /*interrupt_handler_t *handler */ ,
+ (void *) &buf_info /*void *arg */ );
/* Enable "RX Data Available" Interrupt on UART */
/* out8(UART0_BASE + UART_IER, in8(UART0_BASE + UART_IER) |0x01); */
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
/*
- AS HARNOIS : according to CONFIG_KGDB_SER_INDEX kgdb uses serial port
- number 0 or number 1
- - if CONFIG_KGDB_SER_INDEX = 1 => serial port number 0 :
- configuration has been already done
- - if CONFIG_KGDB_SER_INDEX = 2 => serial port number 1 :
- configure port 1 for serial I/O with rate = CONFIG_KGDB_BAUDRATE
+ AS HARNOIS : according to CONFIG_KGDB_SER_INDEX kgdb uses serial port
+ number 0 or number 1
+ - if CONFIG_KGDB_SER_INDEX = 1 => serial port number 0 :
+ configuration has been already done
+ - if CONFIG_KGDB_SER_INDEX = 2 => serial port number 1 :
+ configure port 1 for serial I/O with rate = CONFIG_KGDB_BAUDRATE
*/
#if (CONFIG_KGDB_SER_INDEX & 2)
void kgdb_serial_init (void)
cpu_clk = get_gclk_freq ();
br_reg = (((((cpu_clk / 16) / 18) * 10) / CONFIG_KGDB_BAUDRATE) +
- 5) / 10;
+ 5) / 10;
/*
* Init onboard 16550 UART
*/
#include <ppc_asm.tmpl>
#include <ppc4xx.h>
#include <asm/processor.h>
-#include "speed.h"
/* ------------------------------------------------------------------------- */
/********************************************
* get_OPB_freq
* return OPB bus freq in Hz
-*********************************************/
+ *********************************************/
ulong get_OPB_freq (void)
{
ulong val = 0;
/********************************************
* get_PCI_freq
* return PCI bus freq in Hz
-*********************************************/
+ *********************************************/
ulong get_PCI_freq (void)
{
ulong val;
val = sys_info.freqPLB / sys_info.pllPciDiv;
return val;
}
-#endif /* defined(CONFIG_405GP) || defined(CONFIG_405CR) */
+
+
+#elif defined(CONFIG_440)
+void get_sys_info (sys_info_t * sysInfo)
+{
+ unsigned long sys0;
+ unsigned long temp;
+ unsigned long m;
+
+ /* Extract configured divisors */
+ sys0 = mfdcr( cpc0_sys0 );
+ sysInfo->pllFwdDivA = 8 - ((sys0 & PLLSYS0_FWD_DIV_A_MASK) >> 15);
+ sysInfo->pllFwdDivB = 8 - ((sys0 & PLLSYS0_FWD_DIV_B_MASK) >> 12);
+ temp = (sys0 & PLLSYS0_FB_DIV_MASK) >> 18;
+ sysInfo->pllFbkDiv = temp ? temp : 16;
+ sysInfo->pllOpbDiv = 1 + ((sys0 & PLLSYS0_OPB_DIV_MASK) >> 10);
+ sysInfo->pllExtBusDiv = 1 + ((sys0 & PLLSYS0_EPB_DIV_MASK) >> 8);
+
+ /* Calculate 'M' based on feedback source */
+ if( sys0 & PLLSYS0_EXTSL_MASK )
+ m = sysInfo->pllExtBusDiv * sysInfo->pllOpbDiv * sysInfo->pllFwdDivB;
+ else
+ m = sysInfo->pllFbkDiv * sysInfo->pllFwdDivA;
+
+ /* Now calculate the individual clocks */
+ sysInfo->freqVCOMhz = (m * CONFIG_SYS_CLK_FREQ) + (m>>1);
+ sysInfo->freqProcessor = sysInfo->freqVCOMhz/sysInfo->pllFwdDivA;
+ sysInfo->freqPLB = sysInfo->freqVCOMhz/sysInfo->pllFwdDivB;
+ sysInfo->freqOPB = sysInfo->freqPLB/sysInfo->pllOpbDiv;
+ sysInfo->freqEPB = sysInfo->freqOPB/sysInfo->pllExtBusDiv;
+
+}
+
+ulong get_OPB_freq (void)
+{
+
+ sys_info_t sys_info;
+ get_sys_info (&sys_info);
+ return sys_info.freqOPB;
+}
+#endif
ulong get_gclk_freq (void)
{
ulong val;
-#if defined(CONFIG_405GP) || defined(CONFIG_405CR)
- PPC405_SYS_INFO sys_info;
+#if defined(CONFIG_405GP) || defined(CONFIG_405CR) || defined(CONFIG_440)
+ sys_info_t sys_info;
get_sys_info (&sys_info);
val = sys_info.freqProcessor;
/********************************************
* get_bus_freq
* return PLB bus freq in Hz
-*********************************************/
+ *********************************************/
ulong get_bus_freq (ulong gclk_freq)
{
ulong val;
-#if defined(CONFIG_405GP) || defined(CONFIG_405CR)
- PPC405_SYS_INFO sys_info;
+#if defined(CONFIG_405GP) || defined(CONFIG_405CR) || defined(CONFIG_440)
+ sys_info_t sys_info;
get_sys_info (&sys_info);
val = sys_info.freqPLB;
-#endif /* defined(CONFIG_405GP) || defined(CONFIG_405CR) */
+#endif /* defined(CONFIG_405GP) || defined(CONFIG_405CR) || defined(CONFIG_440)*/
#ifdef CONFIG_IOP480
val = 66;
+++ /dev/null
-/*
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/*-----------------------------------------------------------------------
- * Timer value for timer 2, ICLK = 10
- *
- * SPEED_FCOUNT2 = GCLK / (16 * (TIMER_TMR_PS + 1))
- * SPEED_TMR3_PS = (GCLK / (16 * SPEED_FCOUNT3)) - 1
- *
- * SPEED_FCOUNT2 timer 2 counting frequency
- * GCLK CPU clock
- * SPEED_TMR2_PS prescaler
- */
-#define SPEED_TMR2_PS (250 - 1) /* divide by 250 */
-
-/*-----------------------------------------------------------------------
- * Timer value for PIT
- *
- * PIT_TIME = SPEED_PITC / PITRTCLK
- * PITRTCLK = 8192
- */
-#define SPEED_PITC (82 << 16) /* start counting from 82 */
-
-/*
- * The new value for PTA is calculated from
- *
- * PTA = (gclk * Trefresh) / (2 ^ (2 * DFBRG) * PTP * NCS)
- *
- * gclk CPU clock (not bus clock !)
- * Trefresh Refresh cycle * 4 (four word bursts used)
- * DFBRG For normal mode (no clock reduction) always 0
- * PTP Prescaler (already adjusted for no. of banks and 4K / 8K refresh)
- * NCS Number of SDRAM banks (chip selects) on this UPM.
- */
GOT_ENTRY(.bss)
END_GOT
+/*
+ * 440 Startup -- on reset only the top 4k of the effective
+ * address space is mapped in by an entry in the instruction
+ * and data shadow TLB. The .bootpg section is located in the
+ * top 4k & does only what's necessary to map in the the rest
+ * of the boot rom. Once the boot rom is mapped in we can
+ * proceed with normal startup.
+ *
+ * NOTE: CS0 only covers the top 2MB of the effective address
+ * space after reset.
+ */
+
+#if defined(CONFIG_440)
+ .section .bootpg,"ax"
+ .globl _start_440
+
+/**************************************************************************/
+_start_440:
+ /*----------------------------------------------------------------*/
+ /* Clear and set up some registers. */
+ /*----------------------------------------------------------------*/
+ iccci r0,r0 /* NOTE: operands not used for 440 */
+ dccci r0,r0 /* NOTE: operands not used for 440 */
+ sync
+ li r0,0
+ mtspr srr0,r0
+ mtspr srr1,r0
+ mtspr csrr0,r0
+ mtspr csrr1,r0
+
+ /*----------------------------------------------------------------*/
+ /* Initialize debug */
+ /*----------------------------------------------------------------*/
+ mtspr dbcr0,r0
+ mtspr dbcr1,r0
+ mtspr dbcr2,r0
+ mtspr iac1,r0
+ mtspr iac2,r0
+ mtspr iac3,r0
+ mtspr dac1,r0
+ mtspr dac2,r0
+ mtspr dvc1,r0
+ mtspr dvc2,r0
+
+ mfspr r1,dbsr
+ mtspr dbsr,r1 /* Clear all valid bits */
+
+ /*----------------------------------------------------------------*/
+ /* CCR0 init */
+ /*----------------------------------------------------------------*/
+ /* Disable store gathering & broadcast, guarantee inst/data
+ * cache block touch, force load/store alignment
+ * (see errata 1.12: 440_33)
+ */
+ lis r1,0x0030 /* store gathering & broadcast disable */
+ ori r1,r1,0x6100 /* cache touch & force load/store align */
+ mtspr ccr0,r1
+
+ /*----------------------------------------------------------------*/
+ /* Configure cache regions */
+ /*----------------------------------------------------------------*/
+ mtspr inv0,r0
+ mtspr inv1,r0
+ mtspr inv2,r0
+ mtspr inv3,r0
+ mtspr dnv0,r0
+ mtspr dnv1,r0
+ mtspr dnv2,r0
+ mtspr dnv3,r0
+ mtspr itv0,r0
+ mtspr itv1,r0
+ mtspr itv2,r0
+ mtspr itv3,r0
+ mtspr dtv0,r0
+ mtspr dtv1,r0
+ mtspr dtv2,r0
+ mtspr dtv3,r0
+
+ /*----------------------------------------------------------------*/
+ /* Cache victim limits */
+ /*----------------------------------------------------------------*/
+ /* floors 0, ceiling max to use the entire cache -- nothing locked
+ */
+ lis r1,0x0001
+ ori r1,r1,0xf800
+ mtspr ivlim,r1
+ mtspr dvlim,r1
+
+ /*----------------------------------------------------------------*/
+ /* Clear all TLB entries -- TID = 0, TS = 0 */
+ /*----------------------------------------------------------------*/
+ mtspr mmucr,r0
+ li r1,0x003f /* 64 TLB entries */
+ mtctr r1
+0: tlbwe r0,r1,0x0000 /* Invalidate all entries (V=0)*/
+ subi r1,r1,0x0001
+ bdnz 0b
+
+ /*----------------------------------------------------------------*/
+ /* TLB entry setup -- step thru tlbtab */
+ /*----------------------------------------------------------------*/
+ bl tlbtab /* Get tlbtab pointer */
+ mr r5,r0
+ li r1,0x003f /* 64 TLB entries max */
+ mtctr r1
+ li r4,0 /* TLB # */
+
+ addi r5,r5,-4
+1: lwzu r0,4(r5)
+ cmpwi r0,0
+ beq 2f /* 0 marks end */
+ lwzu r1,4(r5)
+ lwzu r2,4(r5)
+ tlbwe r0,r4,0 /* TLB Word 0 */
+ tlbwe r1,r4,1 /* TLB Word 1 */
+ tlbwe r2,r4,2 /* TLB Word 2 */
+ addi r4,r4,1 /* Next TLB */
+ bdnz 1b
+
+ /*----------------------------------------------------------------*/
+ /* Continue from 'normal' start */
+ /*----------------------------------------------------------------*/
+2: bl 3f
+ b _start
+
+3: li r0,0
+ mtspr srr1,r0 /* Keep things disabled for now */
+ mflr r1
+ mtspr srr0,r1
+ rfi
+#endif
+
/*
* r3 - 1st arg to board_init(): IMMP pointer
* r4 - 2nd arg to board_init(): boot flag
.globl _start
_start:
+/*****************************************************************************/
+#if defined(CONFIG_440)
+
+ /*----------------------------------------------------------------*/
+ /* Clear and set up some registers. */
+ /*----------------------------------------------------------------*/
+ li r0,0x0000
+ lis r1,0xffff
+ mtspr dec,r0 /* prevent dec exceptions */
+ mtspr tbl,r0 /* prevent fit & wdt exceptions */
+ mtspr tbu,r0
+ mtspr tsr,r1 /* clear all timer exception status */
+ mtspr tcr,r0 /* disable all */
+ mtspr esr,r0 /* clear exception syndrome register */
+ mtxer r0 /* clear integer exception register */
+ lis r1,0x0002 /* set CE bit (Critical Exceptions) */
+ ori r1,r1,0x1000 /* set ME bit (Machine Exceptions) */
+ mtmsr r1 /* change MSR */
+
+ /*----------------------------------------------------------------*/
+ /* Debug setup -- some (not very good) ice's need an event*/
+ /* to establish control :-( Define CFG_INIT_DBCR to the dbsr */
+ /* value you need in this case 0x8cff 0000 should do the trick */
+ /*----------------------------------------------------------------*/
+#if defined(CFG_INIT_DBCR)
+ lis r1,0xffff
+ ori r1,r1,0xffff
+ mtspr dbsr,r1 /* Clear all status bits */
+ lis r0,CFG_INIT_DBCR@h
+ ori r0,r0,CFG_INIT_DBCR@l
+ mtspr dbcr0,r0
+ isync
+#endif
+
+ /*----------------------------------------------------------------*/
+ /* Setup the internal SRAM */
+ /*----------------------------------------------------------------*/
+ li r0,0
+ mtdcr isram0_sb1cr,r0 /* Disable bank 1 */
+
+ li r2,0x7fff
+ ori r2,r2,0xffff
+ mfdcr r1,isram0_dpc
+ and r1,r1,r2 /* Disable parity check */
+ mtdcr isram0_dpc,r1
+ mfdcr r1,isram0_pmeg
+ andis. r1,r1,r2 /* Disable pwr mgmt */
+ mtdcr isram0_pmeg,r1
+
+ lis r1,0x8000 /* BAS = 8000_0000 */
+ ori r1,r1,0x0380 /* 8k rw */
+ mtdcr isram0_sb0cr,r1
+
+ /*----------------------------------------------------------------*/
+ /* Setup the stack in internal SRAM */
+ /*----------------------------------------------------------------*/
+ lis r1,CFG_INIT_RAM_ADDR@h
+ ori r1,r1,CFG_INIT_SP_OFFSET@l
+
+ li r0,0
+ stwu r0,-4(r1)
+ stwu r0,-4(r1) /* Terminate call chain */
+
+ stwu r1,-8(r1) /* Save back chain and move SP */
+ lis r0,RESET_VECTOR@h /* Address of reset vector */
+ ori r0,r0, RESET_VECTOR@l
+ stwu r1,-8(r1) /* Save back chain and move SP */
+ stw r0,+12(r1) /* Save return addr (underflow vect) */
+
+ GET_GOT
+ bl board_init_f
+
+#endif /* CONFIG_440 */
+
/*****************************************************************************/
#ifdef CONFIG_IOP480
/*----------------------------------------------------------------------- */
mfspr r3, PVR
blr
+#if !defined(CONFIG_440)
.globl wr_pit
wr_pit:
mtspr pit, r3
blr
+#endif
.globl wr_tcr
wr_tcr:
stw r0, 4(r7)
blr
-
-
extern unsigned long search_exception_table(unsigned long);
/* THIS NEEDS CHANGING to use the board info structure.
-*/
+ */
#define END_OF_MEM 0x00400000
static __inline__ void set_tsr(unsigned long val)
{
- asm volatile("mttsr %0" : : "r" (val));
+#if defined(CONFIG_440)
+ asm volatile("mtspr 0x150, %0" : : "r" (val));
+#else
+ asm volatile("mttsr %0" : : "r" (val));
+#endif
}
static __inline__ unsigned long get_esr(void)
{
- unsigned long val;
+ unsigned long val;
- asm volatile("mfesr %0" : "=r" (val) :);
- return val;
+#if defined(CONFIG_440)
+ asm volatile("mfspr %0, 0x03e" : "=r" (val) :);
+#else
+ asm volatile("mfesr %0" : "=r" (val) :);
+#endif
+ return val;
}
#define ESR_MCI 0x80000000
{
case (1<<12) :
printf("Machine check signal - probably due to mm fault\n"
- "with mmu off\n");
+ "with mmu off\n");
break;
case (1<<13) :
printf("Transfer error ack signal\n");
esr_val = get_esr();
if( esr_val & ESR_PIL )
- printf( "** Illegal Instruction **\n" );
+ printf( "** Illegal Instruction **\n" );
else if( esr_val & ESR_PPR )
- printf( "** Privileged Instruction **\n" );
+ printf( "** Privileged Instruction **\n" );
else if( esr_val & ESR_PTR )
- printf( "** Trap Instruction **\n" );
+ printf( "** Trap Instruction **\n" );
print_backtrace((unsigned long *)regs->gpr[1]);
panic("Program Check Exception");
void
DebugException(struct pt_regs *regs)
{
- printf("Debugger trap at @ %lx\n", regs->nip );
- show_regs(regs);
+ printf("Debugger trap at @ %lx\n", regs->nip );
+ show_regs(regs);
#if (CONFIG_COMMANDS & CFG_CMD_BEDBUG)
- do_bedbug_breakpoint( regs );
+ do_bedbug_breakpoint( regs );
#endif
}
__asm__ __volatile__( \
"1: lwz %0,0(%1)\n" \
- " eieio\n" \
- " li %0,0\n" \
- "2:\n" \
- ".section .fixup,\"ax\"\n" \
- "3: li %0,-1\n" \
- " b 2b\n" \
- ".section __ex_table,\"a\"\n" \
- " .align 2\n" \
- " .long 1b,3b\n" \
- ".text" \
- : "=r" (retval) : "r"(addr));
+ " eieio\n" \
+ " li %0,0\n" \
+ "2:\n" \
+ ".section .fixup,\"ax\"\n" \
+ "3: li %0,-1\n" \
+ " b 2b\n" \
+ ".section __ex_table,\"a\"\n" \
+ " .align 2\n" \
+ " .long 1b,3b\n" \
+ ".text" \
+ : "=r" (retval) : "r"(addr));
return (retval);
#endif
--- /dev/null
+/*
+* Copyright (C) 2002 Scott McNutt <smcnutt@artesyncp.com>
+*
+* See file CREDITS for list of people who contributed to this
+* project.
+*
+* This program is free software; you can redistribute it and/or
+* modify it under the terms of the GNU General Public License as
+* published by the Free Software Foundation; either version 2 of
+* the License, or (at your option) any later version.
+*
+* This program is distributed in the hope that it will be useful,
+* but WITHOUT ANY WARRANTY; without even the implied warranty of
+* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+* GNU General Public License for more details.
+*
+* You should have received a copy of the GNU General Public License
+* along with this program; if not, write to the Free Software
+* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+* MA 02111-1307 USA
+*/
+
+/*
+ * Interrupt vector number definitions to ease the
+ * 405 -- 440 porting pain ;-)
+ *
+ * NOTE: They're not all here yet ... update as needed.
+ *
+ */
+
+#ifndef _VECNUMS_H_
+#define _VECNUMS_H_
+
+#if defined(CONFIG_440)
+
+/* UIC 0 */
+#define VECNUM_U0 0 /* UART0 */
+#define VECNUM_U1 1 /* UART1 */
+#define VECNUM_IIC0 2 /* IIC0 */
+#define VECNUM_IIC1 3 /* IIC1 */
+#define VECNUM_PIM 4 /* PCI inbound message */
+#define VECNUM_PCRW 5 /* PCI command reg write */
+#define VECNUM_PPM 6 /* PCI power management */
+#define VECNUM_MSI0 7 /* PCI MSI level 0 */
+#define VECNUM_MSI1 8 /* PCI MSI level 0 */
+#define VECNUM_MSI2 9 /* PCI MSI level 0 */
+#define VECNUM_MTE 10 /* MAL TXEOB */
+#define VECNUM_MRE 11 /* MAL RXEOB */
+#define VECNUM_D0 12 /* DMA channel 0 */
+#define VECNUM_D1 13 /* DMA channel 1 */
+#define VECNUM_D2 14 /* DMA channel 2 */
+#define VECNUM_D3 15 /* DMA channel 3 */
+#define VECNUM_CT0 18 /* GPT compare timer 0 */
+#define VECNUM_CT1 19 /* GPT compare timer 1 */
+#define VECNUM_CT2 20 /* GPT compare timer 2 */
+#define VECNUM_CT3 21 /* GPT compare timer 3 */
+#define VECNUM_CT4 22 /* GPT compare timer 4 */
+#define VECNUM_EIR0 23 /* External interrupt 0 */
+#define VECNUM_EIR1 24 /* External interrupt 1 */
+#define VECNUM_EIR2 25 /* External interrupt 2 */
+#define VECNUM_EIR3 26 /* External interrupt 3 */
+#define VECNUM_EIR4 27 /* External interrupt 4 */
+#define VECNUM_EIR5 28 /* External interrupt 5 */
+#define VECNUM_EIR6 29 /* External interrupt 6 */
+#define VECNUM_UIC1NC 30 /* UIC1 non-critical interrupt */
+#define VECNUM_UIC1C 31 /* UIC1 critical interrupt */
+
+/* UIC 1 */
+#define VECNUM_MS (32 + 0 ) /* MAL SERR */
+#define VECNUM_TXDE (32 + 1 ) /* MAL TXDE */
+#define VECNUM_RXDE (32 + 2 ) /* MAL RXDE */
+#define VECNUM_ETH0 (32 + 28) /* Ethernet 0 interrupt status */
+#define VECNUM_EWU0 (32 + 29) /* Ethernet 0 wakeup */
+
+#else /* !defined(CONFIG_440) */
+
+#define VECNUM_U0 0 /* UART0 */
+#define VECNUM_U1 1 /* UART1 */
+#define VECNUM_D0 5 /* DMA channel 0 */
+#define VECNUM_D1 6 /* DMA channel 1 */
+#define VECNUM_D2 7 /* DMA channel 2 */
+#define VECNUM_D3 8 /* DMA channel 3 */
+#define VECNUM_EWU0 9 /* Ethernet wakeup */
+#define VECNUM_MS 10 /* MAL SERR */
+#define VECNUM_MTE 11 /* MAL TXEOB */
+#define VECNUM_MRE 12 /* MAL RXEOB */
+#define VECNUM_TXDE 13 /* MAL TXDE */
+#define VECNUM_RXDE 14 /* MAL RXDE */
+#define VECNUM_ETH0 15 /* Ethernet interrupt status */
+#define VECNUM_EIR0 25 /* External interrupt 0 */
+#define VECNUM_EIR1 26 /* External interrupt 1 */
+#define VECNUM_EIR2 27 /* External interrupt 2 */
+#define VECNUM_EIR3 28 /* External interrupt 3 */
+#define VECNUM_EIR4 29 /* External interrupt 4 */
+#define VECNUM_EIR5 30 /* External interrupt 5 */
+#define VECNUM_EIR6 31 /* External interrupt 6 */
+
+#endif /* defined(CONFIG_440) */
+
+#endif /* _VECNUMS_H_ */
/*Register addresses */
+#if defined(CONFIG_440)
+#define EMAC_BASE (CFG_PERIPHERAL_BASE + 0x0800)
+#else
#define EMAC_BASE 0xEF600800
+#endif
+
#define EMAC_M0 (EMAC_BASE)
#define EMAC_M1 (EMAC_BASE + 4)
#define EMAC_TXM0 (EMAC_BASE + 8)
--- /dev/null
+
+
+
+#ifndef _440_i2c_h_
+#define _440_i2c_h_
+
+#define I2C_BASE_ADDR (CFG_PERIPHERAL_BASE + 0x00000400)
+
+#define I2C_REGISTERS_BASE_ADDRESS I2C_BASE_ADDR
+#define IIC_MDBUF (I2C_REGISTERS_BASE_ADDRESS+IICMDBUF)
+#define IIC_SDBUF (I2C_REGISTERS_BASE_ADDRESS+IICSDBUF)
+#define IIC_LMADR (I2C_REGISTERS_BASE_ADDRESS+IICLMADR)
+#define IIC_HMADR (I2C_REGISTERS_BASE_ADDRESS+IICHMADR)
+#define IIC_CNTL (I2C_REGISTERS_BASE_ADDRESS+IICCNTL)
+#define IIC_MDCNTL (I2C_REGISTERS_BASE_ADDRESS+IICMDCNTL)
+#define IIC_STS (I2C_REGISTERS_BASE_ADDRESS+IICSTS)
+#define IIC_EXTSTS (I2C_REGISTERS_BASE_ADDRESS+IICEXTSTS)
+#define IIC_LSADR (I2C_REGISTERS_BASE_ADDRESS+IICLSADR)
+#define IIC_HSADR (I2C_REGISTERS_BASE_ADDRESS+IICHSADR)
+#define IIC_CLKDIV (I2C_REGISTERS_BASE_ADDRESS+IICCLKDIV)
+#define IIC_INTRMSK (I2C_REGISTERS_BASE_ADDRESS+IICINTRMSK)
+#define IIC_XFRCNT (I2C_REGISTERS_BASE_ADDRESS+IICXFRCNT)
+#define IIC_XTCNTLSS (I2C_REGISTERS_BASE_ADDRESS+IICXTCNTLSS)
+#define IIC_DIRECTCNTL (I2C_REGISTERS_BASE_ADDRESS+IICDIRECTCNTL)
+
+/* MDCNTL Register Bit definition */
+#define IIC_MDCNTL_HSCL 0x01
+#define IIC_MDCNTL_EUBS 0x02
+#define IIC_MDCNTL_EINT 0x04
+#define IIC_MDCNTL_ESM 0x08
+#define IIC_MDCNTL_FSM 0x10
+#define IIC_MDCNTL_EGC 0x20
+#define IIC_MDCNTL_FMDB 0x40
+#define IIC_MDCNTL_FSDB 0x80
+
+/* CNTL Register Bit definition */
+#define IIC_CNTL_PT 0x01
+#define IIC_CNTL_READ 0x02
+#define IIC_CNTL_CHT 0x04
+#define IIC_CNTL_RPST 0x08
+/* bit 2/3 for Transfer count*/
+#define IIC_CNTL_AMD 0x40
+#define IIC_CNTL_HMT 0x80
+
+/* STS Register Bit definition */
+#define IIC_STS_PT 0X01
+#define IIC_STS_IRQA 0x02
+#define IIC_STS_ERR 0X04
+#define IIC_STS_SCMP 0x08
+#define IIC_STS_MDBF 0x10
+#define IIC_STS_MDBS 0X20
+#define IIC_STS_SLPR 0x40
+#define IIC_STS_SSS 0x80
+
+/* EXTSTS Register Bit definition */
+#define IIC_EXTSTS_XFRA 0X01
+#define IIC_EXTSTS_ICT 0X02
+#define IIC_EXTSTS_LA 0X04
+
+/* XTCNTLSS Register Bit definition */
+#define IIC_XTCNTLSS_SRST 0x01
+#define IIC_XTCNTLSS_EPI 0x02
+#define IIC_XTCNTLSS_SDBF 0x04
+#define IIC_XTCNTLSS_SBDD 0x08
+#define IIC_XTCNTLSS_SWS 0x10
+#define IIC_XTCNTLSS_SWC 0x20
+#define IIC_XTCNTLSS_SRS 0x40
+#define IIC_XTCNTLSS_SRC 0x80
+#endif
#define PVR_405CR_RB 0x401100C5
#define PVR_405CR_RC 0x40110145 /* same as pc405gp rev e */
#define PVR_405GPR_RA 0x50910951
-#define PVR_440GP_RC 0x40120400
+#define PVR_440GP_RB 0x40120440
+#define PVR_440GP_RC 0x40120481
#define PVR_601 0x00010000
#define PVR_602 0x00050000
#define PVR_603 0x00030000
--- /dev/null
+/*
+ * (C) Copyright 2002
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/************************************************************************
+ * board/config_CPCI440.h - configuration for esd CPCI-440 board
+ ***********************************************************************/
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*-----------------------------------------------------------------------
+ * High Level Configuration Options
+ *----------------------------------------------------------------------*/
+#define CONFIG_EBONY 1 /* Board is ebony */
+#define CONFIG_4xx 1 /* ... PPC4xx family */
+#define CONFIG_BOARD_PRE_INIT /* Call board_pre_init */
+#undef CFG_DRAM_TEST /* Disable-takes long time! */
+#define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */
+
+/*-----------------------------------------------------------------------
+ * Base addresses -- Note these are effective addresses where the
+ * actual resources get mapped (not physical addresses)
+ *----------------------------------------------------------------------*/
+#define CFG_SDRAM_BASE 0x00000000 /* _must_ be 0 */
+#define CFG_FLASH_BASE 0xff800000 /* start of FLASH */
+#define CFG_MONITOR_BASE 0xfffc0000 /* start of monitor */
+#define CFG_PERIPHERAL_BASE 0xe0000000 /* internal peripherals */
+#define CFG_ISRAM_BASE 0xc0000000 /* internal SRAM */
+
+#define CFG_FPGA_BASE (CFG_PERIPHERAL_BASE + 0x08300000)
+#define CFG_NVRAM_BASE_ADDR (CFG_PERIPHERAL_BASE + 0x08000000)
+
+/*-----------------------------------------------------------------------
+ * Initial RAM & stack pointer (placed in internal SRAM)
+ *----------------------------------------------------------------------*/
+#define CFG_INIT_RAM_ADDR CFG_ISRAM_BASE /* Initial RAM address */
+#define CFG_INIT_RAM_END 0x2000 /* End of used area in RAM */
+#define CFG_INIT_DATA_SIZE 128 /* num bytes initial data */
+
+#define CFG_INIT_DATA_OFFSET (CFG_INIT_RAM_END - CFG_INIT_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET CFG_INIT_DATA_OFFSET
+
+#define CFG_MONITOR_LEN (192 * 1024) /* Reserve 192 kB for Mon */
+#define CFG_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc*/
+
+/*-----------------------------------------------------------------------
+ * Serial Port
+ *----------------------------------------------------------------------*/
+#undef CONFIG_SERIAL_SOFTWARE_FIFO
+#undef CFG_EXT_SERIAL_CLOCK (1843200 * 6) /* Ext clk @ 11.059 MHz */
+#define CONFIG_BAUDRATE 9600
+
+#define CFG_BAUDRATE_TABLE \
+ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400}
+
+/*-----------------------------------------------------------------------
+ * NVRAM/RTC
+ *
+ * NOTE: Upper 8 bytes of NVRAM is where the RTC registers are located.
+ * The DS1743 code assumes this condition (i.e. -- it assumes the base
+ * address for the RTC registers is:
+ *
+ * CFG_NVRAM_BASE_ADDR + CFG_NVRAM_SIZE
+ *
+ *----------------------------------------------------------------------*/
+#define CFG_NVRAM_SIZE (0x2000 - 8) /* NVRAM size(8k)- RTC regs */
+#define CONFIG_RTC_DS174x 1 /* DS1743 RTC */
+
+/*-----------------------------------------------------------------------
+ * FLASH related
+ *----------------------------------------------------------------------*/
+#if 1 /* test-only */
+
+#define CFG_FLASH_CFI 1 /* Flash is CFI conformant */
+#define CFG_MAX_FLASH_SECT 128 /* max number of sectors on one chip */
+#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
+#define CFG_FLASH_INCREMENT 0 /* there is only one bank */
+#define CFG_FLASH_PROTECTION 1 /* use hardware protection */
+#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
+#undef CFG_FLASH_BASE
+#define CFG_FLASH_BASE 0xFF800000 /* test-only...*/
+
+#else /* test-only */
+
+#define CFG_MAX_FLASH_BANKS 3 /* number of banks */
+#define CFG_MAX_FLASH_SECT 32 /* sectors per device */
+
+#undef CFG_FLASH_CHECKSUM
+#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
+#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
+
+#endif
+
+/*-----------------------------------------------------------------------
+ * Environment
+ *----------------------------------------------------------------------*/
+#if 0 /* test-only */
+#define CFG_ENV_IS_IN_NVRAM 1 /* Environment uses NVRAM */
+#undef CFG_ENV_IS_IN_FLASH /* ... not in flash */
+#undef CFG_ENV_IS_IN_EEPROM /* ... not in EEPROM */
+
+#define CFG_ENV_SIZE 0x1000 /* Size of Environment vars */
+#define CFG_ENV_ADDR \
+ (CFG_NVRAM_BASE_ADDR+CFG_NVRAM_SIZE-CFG_ENV_SIZE)
+#else
+
+#if 0 /* test-only */
+#define CFG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */
+#define CFG_ENV_OFFSET 0x010 /* environment starts at the beginning of the EEPROM */
+#define CFG_ENV_SIZE 0x800 /* 2048 bytes may be used for env vars*/
+ /* total size of a CAT24WC16 is 2048 bytes */
+#else
+#define CFG_ENV_IS_IN_FLASH 1
+#define CFG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */
+#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
+#endif
+
+/*-----------------------------------------------------------------------
+ * I2C EEPROM (CAT24WC16) for environment
+ */
+#define CONFIG_HARD_I2C /* I2c with hardware support */
+#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
+#define CFG_I2C_SLAVE 0x7F
+
+#define CFG_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */
+#define CFG_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
+/* mask of address bits that overflow into the "EEPROM chip address" */
+#define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x07
+#define CFG_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */
+ /* 16 byte page write mode using*/
+ /* last 4 bits of the address */
+#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
+#define CFG_EEPROM_PAGE_WRITE_ENABLE
+
+#endif
+
+#define CONFIG_BOOTARGS "root=/dev/hda1 "
+#define CONFIG_BOOTCOMMAND "bootm ffc00000" /* autoboot command */
+#define CONFIG_BOOTDELAY -1 /* disable autoboot */
+#define CONFIG_BAUDRATE 9600
+
+#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
+#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
+
+#define CONFIG_MII 1 /* MII PHY management */
+#define CONFIG_PHY_ADDR 1 /* PHY address */
+
+#if 0 /* test-only */
+#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
+ CFG_CMD_IRQ | \
+ CFG_CMD_I2C | \
+ CFG_CMD_KGDB | \
+ CFG_CMD_DHCP | \
+ CFG_CMD_DATE | \
+ CFG_CMD_BEDBUG | \
+ CFG_CMD_ELF )
+#else
+#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
+ CFG_CMD_IRQ | \
+ CFG_CMD_ELF | \
+ CFG_CMD_DATE | \
+ CFG_CMD_I2C | \
+ CFG_CMD_EEPROM )
+/* test-only: support fehlt bisher... */
+/* CFG_CMD_IDE | \*/
+/* CFG_CMD_PCI | \*/
+#endif
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+#undef CONFIG_WATCHDOG /* watchdog disabled */
+
+#undef CONFIG_SPD_EEPROM /* don't use SPD EEPROM for setup */
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP /* undef to save memory */
+#define CFG_PROMPT "=> " /* Monitor Command Prompt */
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
+#else
+#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
+#endif
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS 16 /* max number of command args */
+#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
+
+#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
+#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
+
+#define CFG_LOAD_ADDR 0x100000 /* default load address */
+#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */
+
+#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
+
+#if 0 /* test-only */
+#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
+#undef CONFIG_SOFT_I2C /* I2C bit-banged */
+#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
+#define CFG_I2C_SLAVE 0x7F
+#endif
+
+
+/*-----------------------------------------------------------------------
+ * PCI stuff
+ *-----------------------------------------------------------------------
+ */
+#if 0
+#define PCI_HOST_ADAPTER 0 /* configure ar pci adapter */
+#define PCI_HOST_FORCE 1 /* configure as pci host */
+#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
+
+#define CONFIG_PCI /* include pci support */
+#define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */
+#define CONFIG_PCI_PNP /* do pci plug-and-play */
+ /* resource configuration */
+
+#define CFG_PCI_SUBSYS_VENDORID 0x0000 /* PCI Vendor ID: to-do!!! */
+#define CFG_PCI_SUBSYS_DEVICEID 0x0000 /* PCI Device ID: to-do!!! */
+#define CFG_PCI_PTM1LA 0x00000000 /* point to sdram */
+#define CFG_PCI_PTM1MS 0x80000001 /* 2GB, enable hard-wired to 1 */
+#define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
+#define CFG_PCI_PTM2LA 0x00000000 /* disabled */
+#define CFG_PCI_PTM2MS 0x00000000 /* disabled */
+#define CFG_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */
+#endif
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_DCACHE_SIZE 32768 /* For IBM 440 CPUs */
+#define CFG_CACHELINE_SIZE 32 /* ... */
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
+#endif
+
+
+/* Configuration Port location */
+#define CONFIG_PORT_ADDR 0xF0000500
+
+/*-----------------------------------------------------------------------
+ * Definitions for Serial Presence Detect EEPROM address
+ * (to get SDRAM settings)
+ */
+#define SPD_EEPROM_ADDRESS 0x50
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
+#define BOOTFLAG_WARM 0x02 /* Software reboot */
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
+#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
+#endif
+#endif /* __CONFIG_H */
--- /dev/null
+/*
+ * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/************************************************************************
+ * board/config_EBONY.h - configuration for IBM 440GP Ref (Ebony)
+ ***********************************************************************/
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*-----------------------------------------------------------------------
+ * High Level Configuration Options
+ *----------------------------------------------------------------------*/
+#define CONFIG_EBONY 1 /* Board is ebony */
+#define CONFIG_4xx 1 /* ... PPC4xx family */
+#define CONFIG_BOARD_PRE_INIT /* Call board_pre_init */
+#undef CFG_DRAM_TEST /* Disable-takes long time! */
+#define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */
+
+/*-----------------------------------------------------------------------
+ * Base addresses -- Note these are effective addresses where the
+ * actual resources get mapped (not physical addresses)
+ *----------------------------------------------------------------------*/
+#define CFG_SDRAM_BASE 0x00000000 /* _must_ be 0 */
+#define CFG_FLASH_BASE 0xff800000 /* start of FLASH */
+#define CFG_MONITOR_BASE 0xfff80000 /* start of monitor */
+#define CFG_PERIPHERAL_BASE 0xe0000000 /* internal peripherals */
+#define CFG_ISRAM_BASE 0xc0000000 /* internal SRAM */
+
+#define CFG_FPGA_BASE (CFG_PERIPHERAL_BASE + 0x08300000)
+#define CFG_NVRAM_BASE_ADDR (CFG_PERIPHERAL_BASE + 0x08000000)
+
+/*-----------------------------------------------------------------------
+ * Initial RAM & stack pointer (placed in internal SRAM)
+ *----------------------------------------------------------------------*/
+#define CFG_INIT_RAM_ADDR CFG_ISRAM_BASE /* Initial RAM address */
+#define CFG_INIT_RAM_END 0x2000 /* End of used area in RAM */
+#define CFG_INIT_DATA_SIZE 128 /* num bytes initial data */
+
+#define CFG_INIT_DATA_OFFSET (CFG_INIT_RAM_END - CFG_INIT_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET CFG_INIT_DATA_OFFSET
+
+#define CFG_MONITOR_LEN (192 * 1024) /* Reserve 192 kB for Mon */
+#define CFG_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc*/
+
+/*-----------------------------------------------------------------------
+ * Serial Port
+ *----------------------------------------------------------------------*/
+#undef CONFIG_SERIAL_SOFTWARE_FIFO
+#define CFG_EXT_SERIAL_CLOCK (1843200 * 6) /* Ext clk @ 11.059 MHz */
+#define CONFIG_BAUDRATE 9600
+
+#define CFG_BAUDRATE_TABLE \
+ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400}
+
+/*-----------------------------------------------------------------------
+ * NVRAM/RTC
+ *
+ * NOTE: Upper 8 bytes of NVRAM is where the RTC registers are located.
+ * The DS1743 code assumes this condition (i.e. -- it assumes the base
+ * address for the RTC registers is:
+ *
+ * CFG_NVRAM_BASE_ADDR + CFG_NVRAM_SIZE
+ *
+ *----------------------------------------------------------------------*/
+#define CFG_NVRAM_SIZE (0x2000 - 8) /* NVRAM size(8k)- RTC regs */
+#define CONFIG_RTC_DS174x 1 /* DS1743 RTC */
+
+/*-----------------------------------------------------------------------
+ * FLASH related
+ *----------------------------------------------------------------------*/
+#define CFG_MAX_FLASH_BANKS 3 /* number of banks */
+#define CFG_MAX_FLASH_SECT 32 /* sectors per device */
+
+#undef CFG_FLASH_CHECKSUM
+#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
+#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
+
+/*-----------------------------------------------------------------------
+ * Environment
+ *----------------------------------------------------------------------*/
+#define CFG_ENV_IS_IN_NVRAM 1 /* Environment uses NVRAM */
+#undef CFG_ENV_IS_IN_FLASH /* ... not in flash */
+#undef CFG_ENV_IS_IN_EEPROM /* ... not in EEPROM */
+
+#define CFG_ENV_SIZE 0x1000 /* Size of Environment vars */
+#define CFG_ENV_ADDR \
+ (CFG_NVRAM_BASE_ADDR+CFG_NVRAM_SIZE-CFG_ENV_SIZE)
+
+#define CONFIG_BOOTARGS "root=/dev/hda1 "
+#define CONFIG_BOOTCOMMAND "bootm ffc00000" /* autoboot command */
+#define CONFIG_BOOTDELAY -1 /* disable autoboot */
+#define CONFIG_BAUDRATE 9600
+
+#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
+#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
+
+#define CONFIG_MII 1 /* MII PHY management */
+#define CONFIG_PHY_ADDR 1 /* PHY address */
+
+
+#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
+ CFG_CMD_IRQ | \
+ CFG_CMD_I2C | \
+ CFG_CMD_KGDB | \
+ CFG_CMD_DHCP | \
+ CFG_CMD_DATE | \
+ CFG_CMD_BEDBUG | \
+ CFG_CMD_ELF )
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+#undef CONFIG_WATCHDOG /* watchdog disabled */
+
+#undef CONFIG_SPD_EEPROM /* don't use SPD EEPROM for setup */
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP /* undef to save memory */
+#define CFG_PROMPT "=> " /* Monitor Command Prompt */
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
+#else
+#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
+#endif
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS 16 /* max number of command args */
+#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
+
+#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
+#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
+
+#define CFG_LOAD_ADDR 0x100000 /* default load address */
+#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */
+
+#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
+
+#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
+#undef CONFIG_SOFT_I2C /* I2C bit-banged */
+#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
+#define CFG_I2C_SLAVE 0x7F
+
+
+/*-----------------------------------------------------------------------
+ * PCI stuff
+ *-----------------------------------------------------------------------
+ */
+#if 0
+#define PCI_HOST_ADAPTER 0 /* configure ar pci adapter */
+#define PCI_HOST_FORCE 1 /* configure as pci host */
+#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
+
+#define CONFIG_PCI /* include pci support */
+#define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */
+#define CONFIG_PCI_PNP /* do pci plug-and-play */
+ /* resource configuration */
+
+#define CFG_PCI_SUBSYS_VENDORID 0x0000 /* PCI Vendor ID: to-do!!! */
+#define CFG_PCI_SUBSYS_DEVICEID 0x0000 /* PCI Device ID: to-do!!! */
+#define CFG_PCI_PTM1LA 0x00000000 /* point to sdram */
+#define CFG_PCI_PTM1MS 0x80000001 /* 2GB, enable hard-wired to 1 */
+#define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
+#define CFG_PCI_PTM2LA 0x00000000 /* disabled */
+#define CFG_PCI_PTM2MS 0x00000000 /* disabled */
+#define CFG_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */
+#endif
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_DCACHE_SIZE 8192 /* For IBM 405 CPUs */
+#define CFG_CACHELINE_SIZE 32 /* ... */
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
+#endif
+
+
+/* Configuration Port location */
+#define CONFIG_PORT_ADDR 0xF0000500
+
+/*-----------------------------------------------------------------------
+ * Definitions for Serial Presence Detect EEPROM address
+ * (to get SDRAM settings)
+ */
+#define SPD_EEPROM_ADDRESS 0x50
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
+#define BOOTFLAG_WARM 0x02 /* Software reboot */
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
+#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
+#endif
+#endif /* __CONFIG_H */
#endif /* CFG_ENV_IS_IN_NVRAM */
#ifdef CFG_ENV_IS_IN_EEPROM
-#define CFG_ENV_OFFSET 0 /* Start right at beginning of NVRAM */
-#define CFG_ENV_SIZE 1024 /* Use only a part of it - it's slow! */
+#define CFG_ENV_OFFSET 512 /* Leave 512 bytes free for other data */
+#define CFG_ENV_SIZE 1536 /* Use remaining space */
#endif /* CFG_ENV_IS_IN_EEPROM */
-#define CFG_ENV_EEPROM_ADDR 0xA0
-#define CFG_ENV_EEPROM_ADDR_LEN 2
-
/*-----------------------------------------------------------------------
* Cache Configuration
*/
#define FLASH_AMDL324B 0x0015
#define FLASH_AMDL640 0x0016 /* AMD AM29DL640D */
+#define FLASH_AMD016 0x0018 /* AMD AM29F016D */
#define FLASH_SST200A 0x0040 /* SST 39xF200A ID ( 2M = 128K x 16 ) */
#define FLASH_SST400A 0x0042 /* SST 39xF400A ID ( 4M = 256K x 16 ) */
--- /dev/null
+/*----------------------------------------------------------------------------+
+|
+| This source code has been made available to you by IBM on an AS-IS
+| basis. Anyone receiving this source is licensed under IBM
+| copyrights to use it in any way he or she deems fit, including
+| copying it, modifying it, compiling it, and redistributing it either
+| with or without modifications. No license under IBM patents or
+| patent applications is to be implied by the copyright license.
+|
+| Any user of this software should understand that IBM cannot provide
+| technical support for this software and will not be responsible for
+| any consequences resulting from the use of this software.
+|
+| Any person who transfers this source code or any derivative work
+| must include the IBM copyright notice, this paragraph, and the
+| preceding two paragraphs in the transferred software.
+|
+| COPYRIGHT I B M CORPORATION 1999
+| LICENSED MATERIAL - PROGRAM PROPERTY OF I B M
++----------------------------------------------------------------------------*/
+
+#ifndef __PPC405_H__
+#define __PPC405_H__
+
+/*
+//-------------------------------------------------------------------------------
+// Special Purpose Registers
+//-------------------------------------------------------------------------------
+*/
+ #define srr2 0x3de /* save/restore register 2 */
+ #define srr3 0x3df /* save/restore register 3 */
+ #define dbsr 0x3f0 /* debug status register */
+ #define dbcr0 0x3f2 /* debug control register 0 */
+ #define dbcr1 0x3bd /* debug control register 1 */
+ #define iac1 0x3f4 /* instruction address comparator 1 */
+ #define iac2 0x3f5 /* instruction address comparator 2 */
+ #define iac3 0x3b4 /* instruction address comparator 3 */
+ #define iac4 0x3b5 /* instruction address comparator 4 */
+ #define dac1 0x3f6 /* data address comparator 1 */
+ #define dac2 0x3f7 /* data address comparator 2 */
+ #define dccr 0x3fa /* data cache control register */
+ #define iccr 0x3fb /* instruction cache control register */
+ #define esr 0x3d4 /* execption syndrome register */
+ #define dear 0x3d5 /* data exeption address register */
+ #define evpr 0x3d6 /* exeption vector prefix register */
+ #define tsr 0x3d8 /* timer status register */
+ #define tcr 0x3da /* timer control register */
+ #define pit 0x3db /* programmable interval timer */
+ #define sgr 0x3b9 /* storage guarded reg */
+ #define dcwr 0x3ba /* data cache write-thru reg*/
+ #define sler 0x3bb /* storage little-endian reg */
+ #define cdbcr 0x3d7 /* cache debug cntrl reg */
+ #define icdbdr 0x3d3 /* instr cache dbug data reg*/
+ #define ccr0 0x3b3 /* core configuration register */
+ #define dvc1 0x3b6 /* data value compare register 1 */
+ #define dvc2 0x3b7 /* data value compare register 2 */
+ #define pid 0x3b1 /* process ID */
+ #define su0r 0x3bc /* storage user-defined register 0 */
+ #define zpr 0x3b0 /* zone protection regsiter */
+
+ #define tbl 0x11c /* time base lower - privileged write */
+ #define tbu 0x11d /* time base upper - privileged write */
+
+ #define sprg4r 0x104 /* Special purpose general 4 - read only */
+ #define sprg5r 0x105 /* Special purpose general 5 - read only */
+ #define sprg6r 0x106 /* Special purpose general 6 - read only */
+ #define sprg7r 0x107 /* Special purpose general 7 - read only */
+ #define sprg4w 0x114 /* Special purpose general 4 - write only */
+ #define sprg5w 0x115 /* Special purpose general 5 - write only */
+ #define sprg6w 0x116 /* Special purpose general 6 - write only */
+ #define sprg7w 0x117 /* Special purpose general 7 - write only */
+
+/******************************************************************************
+ * Special for PPC405GP
+ ******************************************************************************/
+
+/******************************************************************************
+ * DMA
+ ******************************************************************************/
+#define DMA_DCR_BASE 0x100
+#define dmacr0 (DMA_DCR_BASE+0x00) /* DMA channel control register 0 */
+#define dmact0 (DMA_DCR_BASE+0x01) /* DMA count register 0 */
+#define dmada0 (DMA_DCR_BASE+0x02) /* DMA destination address register 0 */
+#define dmasa0 (DMA_DCR_BASE+0x03) /* DMA source address register 0 */
+#define dmasb0 (DMA_DCR_BASE+0x04) /* DMA scatter/gather descriptor addr 0 */
+#define dmacr1 (DMA_DCR_BASE+0x08) /* DMA channel control register 1 */
+#define dmact1 (DMA_DCR_BASE+0x09) /* DMA count register 1 */
+#define dmada1 (DMA_DCR_BASE+0x0a) /* DMA destination address register 1 */
+#define dmasa1 (DMA_DCR_BASE+0x0b) /* DMA source address register 1 */
+#define dmasb1 (DMA_DCR_BASE+0x0c) /* DMA scatter/gather descriptor addr 1 */
+#define dmacr2 (DMA_DCR_BASE+0x10) /* DMA channel control register 2 */
+#define dmact2 (DMA_DCR_BASE+0x11) /* DMA count register 2 */
+#define dmada2 (DMA_DCR_BASE+0x12) /* DMA destination address register 2 */
+#define dmasa2 (DMA_DCR_BASE+0x13) /* DMA source address register 2 */
+#define dmasb2 (DMA_DCR_BASE+0x14) /* DMA scatter/gather descriptor addr 2 */
+#define dmacr3 (DMA_DCR_BASE+0x18) /* DMA channel control register 3 */
+#define dmact3 (DMA_DCR_BASE+0x19) /* DMA count register 3 */
+#define dmada3 (DMA_DCR_BASE+0x1a) /* DMA destination address register 3 */
+#define dmasa3 (DMA_DCR_BASE+0x1b) /* DMA source address register 3 */
+#define dmasb3 (DMA_DCR_BASE+0x1c) /* DMA scatter/gather descriptor addr 3 */
+#define dmasr (DMA_DCR_BASE+0x20) /* DMA status register */
+#define dmasgc (DMA_DCR_BASE+0x23) /* DMA scatter/gather command register */
+#define dmaadr (DMA_DCR_BASE+0x24) /* DMA address decode register */
+
+/******************************************************************************
+ * Universal interrupt controller
+ ******************************************************************************/
+#define UIC_DCR_BASE 0xc0
+#define uicsr (UIC_DCR_BASE+0x0) /* UIC status */
+#define uicsrs (UIC_DCR_BASE+0x1) /* UIC status set */
+#define uicer (UIC_DCR_BASE+0x2) /* UIC enable */
+#define uiccr (UIC_DCR_BASE+0x3) /* UIC critical */
+#define uicpr (UIC_DCR_BASE+0x4) /* UIC polarity */
+#define uictr (UIC_DCR_BASE+0x5) /* UIC triggering */
+#define uicmsr (UIC_DCR_BASE+0x6) /* UIC masked status */
+#define uicvr (UIC_DCR_BASE+0x7) /* UIC vector */
+#define uicvcr (UIC_DCR_BASE+0x8) /* UIC vector configuration */
+
+/*-----------------------------------------------------------------------------+
+| Universal interrupt controller interrupts
++-----------------------------------------------------------------------------*/
+#define UIC_UART0 0x80000000 /* UART 0 */
+#define UIC_UART1 0x40000000 /* UART 1 */
+#define UIC_IIC 0x20000000 /* IIC */
+#define UIC_EXT_MAST 0x10000000 /* External Master */
+#define UIC_PCI 0x08000000 /* PCI write to command reg */
+#define UIC_DMA0 0x04000000 /* DMA chan. 0 */
+#define UIC_DMA1 0x02000000 /* DMA chan. 1 */
+#define UIC_DMA2 0x01000000 /* DMA chan. 2 */
+#define UIC_DMA3 0x00800000 /* DMA chan. 3 */
+#define UIC_EMAC_WAKE 0x00400000 /* EMAC wake up */
+#define UIC_MAL_SERR 0x00200000 /* MAL SERR */
+#define UIC_MAL_TXEOB 0x00100000 /* MAL TXEOB */
+#define UIC_MAL_RXEOB 0x00080000 /* MAL RXEOB */
+#define UIC_MAL_TXDE 0x00040000 /* MAL TXDE */
+#define UIC_MAL_RXDE 0x00020000 /* MAL RXDE */
+#define UIC_ENET 0x00010000 /* Ethernet */
+#define UIC_EXT_PCI_SERR 0x00008000 /* External PCI SERR# */
+#define UIC_ECC_CE 0x00004000 /* ECC Correctable Error */
+#define UIC_PCI_PM 0x00002000 /* PCI Power Management */
+#define UIC_EXT0 0x00000040 /* External interrupt 0 */
+#define UIC_EXT1 0x00000020 /* External interrupt 1 */
+#define UIC_EXT2 0x00000010 /* External interrupt 2 */
+#define UIC_EXT3 0x00000008 /* External interrupt 3 */
+#define UIC_EXT4 0x00000004 /* External interrupt 4 */
+#define UIC_EXT5 0x00000002 /* External interrupt 5 */
+#define UIC_EXT6 0x00000001 /* External interrupt 6 */
+
+/******************************************************************************
+ * SDRAM Controller
+ ******************************************************************************/
+#define SDRAM_DCR_BASE 0x10
+#define memcfga (SDRAM_DCR_BASE+0x0) /* Memory configuration address reg */
+#define memcfgd (SDRAM_DCR_BASE+0x1) /* Memory configuration data reg */
+ /* values for memcfga register - indirect addressing of these regs */
+ #define mem_besra 0x00 /* bus error syndrome reg a */
+ #define mem_besrsa 0x04 /* bus error syndrome reg set a */
+ #define mem_besrb 0x08 /* bus error syndrome reg b */
+ #define mem_besrsb 0x0c /* bus error syndrome reg set b */
+ #define mem_bear 0x10 /* bus error address reg */
+ #define mem_mcopt1 0x20 /* memory controller options 1 */
+ #define mem_rtr 0x30 /* refresh timer reg */
+ #define mem_pmit 0x34 /* power management idle timer */
+ #define mem_mb0cf 0x40 /* memory bank 0 configuration */
+ #define mem_mb1cf 0x44 /* memory bank 1 configuration */
+ #define mem_mb2cf 0x48 /* memory bank 2 configuration */
+ #define mem_mb3cf 0x4c /* memory bank 3 configuration */
+ #define mem_sdtr1 0x80 /* timing reg 1 */
+ #define mem_ecccf 0x94 /* ECC configuration */
+ #define mem_eccerr 0x98 /* ECC error status */
+
+/******************************************************************************
+ * Decompression Controller
+ ******************************************************************************/
+#define DECOMP_DCR_BASE 0x14
+#define kiar (DECOMP_DCR_BASE+0x0) /* Decompression controller addr reg */
+#define kidr (DECOMP_DCR_BASE+0x1) /* Decompression controller data reg */
+ /* values for kiar register - indirect addressing of these regs */
+ #define kitor0 0x00 /* index table origin register 0 */
+ #define kitor1 0x01 /* index table origin register 1 */
+ #define kitor2 0x02 /* index table origin register 2 */
+ #define kitor3 0x03 /* index table origin register 3 */
+ #define kaddr0 0x04 /* address decode definition regsiter 0 */
+ #define kaddr1 0x05 /* address decode definition regsiter 1 */
+ #define kconf 0x40 /* decompression core config register */
+ #define kid 0x41 /* decompression core ID register */
+ #define kver 0x42 /* decompression core version # reg */
+ #define kpear 0x50 /* bus error addr reg (PLB addr) */
+ #define kbear 0x51 /* bus error addr reg (DCP to EBIU addr)*/
+ #define kesr0 0x52 /* bus error status reg 0 (R/clear) */
+ #define kesr0s 0x53 /* bus error status reg 0 (set) */
+ /* There are 0x400 of the following registers, from krom0 to krom3ff*/
+ /* Only the first one is given here. */
+ #define krom0 0x400 /* SRAM/ROM read/write */
+
+/******************************************************************************
+ * Power Management
+ ******************************************************************************/
+#define POWERMAN_DCR_BASE 0xb8
+#define cpmsr (POWERMAN_DCR_BASE+0x0) /* Power management status */
+#define cpmer (POWERMAN_DCR_BASE+0x1) /* Power management enable */
+#define cpmfr (POWERMAN_DCR_BASE+0x2) /* Power management force */
+
+/******************************************************************************
+ * Extrnal Bus Controller
+ ******************************************************************************/
+#define EBC_DCR_BASE 0x12
+#define ebccfga (EBC_DCR_BASE+0x0) /* External bus controller addr reg */
+#define ebccfgd (EBC_DCR_BASE+0x1) /* External bus controller data reg */
+ /* values for ebccfga register - indirect addressing of these regs */
+ #define pb0cr 0x00 /* periph bank 0 config reg */
+ #define pb1cr 0x01 /* periph bank 1 config reg */
+ #define pb2cr 0x02 /* periph bank 2 config reg */
+ #define pb3cr 0x03 /* periph bank 3 config reg */
+ #define pb4cr 0x04 /* periph bank 4 config reg */
+ #define pb5cr 0x05 /* periph bank 5 config reg */
+ #define pb6cr 0x06 /* periph bank 6 config reg */
+ #define pb7cr 0x07 /* periph bank 7 config reg */
+ #define pb0ap 0x10 /* periph bank 0 access parameters */
+ #define pb1ap 0x11 /* periph bank 1 access parameters */
+ #define pb2ap 0x12 /* periph bank 2 access parameters */
+ #define pb3ap 0x13 /* periph bank 3 access parameters */
+ #define pb4ap 0x14 /* periph bank 4 access parameters */
+ #define pb5ap 0x15 /* periph bank 5 access parameters */
+ #define pb6ap 0x16 /* periph bank 6 access parameters */
+ #define pb7ap 0x17 /* periph bank 7 access parameters */
+ #define pbear 0x20 /* periph bus error addr reg */
+ #define pbesr0 0x21 /* periph bus error status reg 0 */
+ #define pbesr1 0x22 /* periph bus error status reg 1 */
+ #define epcr 0x23 /* external periph control reg */
+
+/******************************************************************************
+ * Control
+ ******************************************************************************/
+#define CNTRL_DCR_BASE 0x0b0
+#define pllmd (CNTRL_DCR_BASE+0x0) /* PLL mode register */
+#define cntrl0 (CNTRL_DCR_BASE+0x1) /* Control 0 register */
+#define cntrl1 (CNTRL_DCR_BASE+0x2) /* Control 1 register */
+#define reset (CNTRL_DCR_BASE+0x3) /* reset register */
+#define strap (CNTRL_DCR_BASE+0x4) /* strap register */
+
+/* Bit definitions */
+#define PLLMR_FWD_DIV_MASK 0xE0000000 /* Forward Divisor */
+#define PLLMR_FWD_DIV_BYPASS 0xE0000000
+#define PLLMR_FWD_DIV_3 0xA0000000
+#define PLLMR_FWD_DIV_4 0x80000000
+#define PLLMR_FWD_DIV_6 0x40000000
+
+#define PLLMR_FB_DIV_MASK 0x1E000000 /* Feedback Divisor */
+#define PLLMR_FB_DIV_1 0x02000000
+#define PLLMR_FB_DIV_2 0x04000000
+#define PLLMR_FB_DIV_3 0x06000000
+#define PLLMR_FB_DIV_4 0x08000000
+
+#define PLLMR_TUNING_MASK 0x01F80000
+
+#define PLLMR_CPU_TO_PLB_MASK 0x00060000 /* CPU:PLB Frequency Divisor */
+#define PLLMR_CPU_PLB_DIV_1 0x00000000
+#define PLLMR_CPU_PLB_DIV_2 0x00020000
+#define PLLMR_CPU_PLB_DIV_3 0x00040000
+#define PLLMR_CPU_PLB_DIV_4 0x00060000
+
+#define PLLMR_OPB_TO_PLB_MASK 0x00018000 /* OPB:PLB Frequency Divisor */
+#define PLLMR_OPB_PLB_DIV_1 0x00000000
+#define PLLMR_OPB_PLB_DIV_2 0x00008000
+#define PLLMR_OPB_PLB_DIV_3 0x00010000
+#define PLLMR_OPB_PLB_DIV_4 0x00018000
+
+#define PLLMR_PCI_TO_PLB_MASK 0x00006000 /* PCI:PLB Frequency Divisor */
+#define PLLMR_PCI_PLB_DIV_1 0x00000000
+#define PLLMR_PCI_PLB_DIV_2 0x00002000
+#define PLLMR_PCI_PLB_DIV_3 0x00004000
+#define PLLMR_PCI_PLB_DIV_4 0x00006000
+
+#define PLLMR_EXB_TO_PLB_MASK 0x00001800 /* External Bus:PLB Divisor */
+#define PLLMR_EXB_PLB_DIV_2 0x00000000
+#define PLLMR_EXB_PLB_DIV_3 0x00000800
+#define PLLMR_EXB_PLB_DIV_4 0x00001000
+#define PLLMR_EXB_PLB_DIV_5 0x00001800
+
+/* definitions for PPC405GPr (new mode strapping) */
+#define PLLMR_FWDB_DIV_MASK 0x00000007 /* Forward Divisor B */
+
+#define PSR_PLL_FWD_MASK 0xC0000000
+#define PSR_PLL_FDBACK_MASK 0x30000000
+#define PSR_PLL_TUNING_MASK 0x0E000000
+#define PSR_PLB_CPU_MASK 0x01800000
+#define PSR_OPB_PLB_MASK 0x00600000
+#define PSR_PCI_PLB_MASK 0x00180000
+#define PSR_EB_PLB_MASK 0x00060000
+#define PSR_ROM_WIDTH_MASK 0x00018000
+#define PSR_ROM_LOC 0x00004000
+#define PSR_PCI_ASYNC_EN 0x00001000
+#define PSR_PERCLK_SYNC_MODE_EN 0x00000800 /* PPC405GPr only */
+#define PSR_PCI_ARBIT_EN 0x00000400
+#define PSR_NEW_MODE_EN 0x00000020 /* PPC405GPr only */
+
+/*
+ * PLL Voltage Controlled Oscillator (VCO) definitions
+ * Maximum and minimum values (in MHz) for correct PLL operation.
+ */
+#define VCO_MIN 400
+#define VCO_MAX 800
+
+/******************************************************************************
+ * Memory Access Layer
+ ******************************************************************************/
+#define MAL_DCR_BASE 0x180
+#define malmcr (MAL_DCR_BASE+0x00) /* MAL Config reg */
+#define malesr (MAL_DCR_BASE+0x01) /* Error Status reg (Read/Clear) */
+#define malier (MAL_DCR_BASE+0x02) /* Interrupt enable reg */
+#define maldbr (MAL_DCR_BASE+0x03) /* Mal Debug reg (Read only) */
+#define maltxcasr (MAL_DCR_BASE+0x04) /* TX Channel active reg (set) */
+#define maltxcarr (MAL_DCR_BASE+0x05) /* TX Channel active reg (Reset) */
+#define maltxeobisr (MAL_DCR_BASE+0x06) /* TX End of buffer int status reg */
+#define maltxdeir (MAL_DCR_BASE+0x07) /* TX Descr. Error Int reg */
+#define malrxcasr (MAL_DCR_BASE+0x10) /* RX Channel active reg (set) */
+#define malrxcarr (MAL_DCR_BASE+0x11) /* RX Channel active reg (Reset) */
+#define malrxeobisr (MAL_DCR_BASE+0x12) /* RX End of buffer int status reg */
+#define malrxdeir (MAL_DCR_BASE+0x13) /* RX Descr. Error Int reg */
+#define maltxctp0r (MAL_DCR_BASE+0x20) /* TX 0 Channel table pointer reg */
+#define maltxctp1r (MAL_DCR_BASE+0x21) /* TX 1 Channel table pointer reg */
+#define malrxctp0r (MAL_DCR_BASE+0x40) /* RX 0 Channel table pointer reg */
+#define malrcbs0 (MAL_DCR_BASE+0x60) /* RX 0 Channel buffer size reg */
+
+/*-----------------------------------------------------------------------------
+| IIC Register Offsets
+'----------------------------------------------------------------------------*/
+#define IICMDBUF 0x00
+#define IICSDBUF 0x02
+#define IICLMADR 0x04
+#define IICHMADR 0x05
+#define IICCNTL 0x06
+#define IICMDCNTL 0x07
+#define IICSTS 0x08
+#define IICEXTSTS 0x09
+#define IICLSADR 0x0A
+#define IICHSADR 0x0B
+#define IICCLKDIV 0x0C
+#define IICINTRMSK 0x0D
+#define IICXFRCNT 0x0E
+#define IICXTCNTLSS 0x0F
+#define IICDIRECTCNTL 0x10
+
+/*-----------------------------------------------------------------------------
+| UART Register Offsets
+'----------------------------------------------------------------------------*/
+#define DATA_REG 0x00
+#define DL_LSB 0x00
+#define DL_MSB 0x01
+#define INT_ENABLE 0x01
+#define FIFO_CONTROL 0x02
+#define LINE_CONTROL 0x03
+#define MODEM_CONTROL 0x04
+#define LINE_STATUS 0x05
+#define MODEM_STATUS 0x06
+#define SCRATCH 0x07
+
+/******************************************************************************
+ * On Chip Memory
+ ******************************************************************************/
+#define OCM_DCR_BASE 0x018
+#define ocmisarc (OCM_DCR_BASE+0x00) /* OCM I-side address compare reg */
+#define ocmiscntl (OCM_DCR_BASE+0x01) /* OCM I-side control reg */
+#define ocmdsarc (OCM_DCR_BASE+0x02) /* OCM D-side address compare reg */
+#define ocmdscntl (OCM_DCR_BASE+0x03) /* OCM D-side control reg */
+
+
+/*
+ * Macro for accessing the indirect EBC register
+ */
+#define mtebc(reg, data) mtdcr(ebccfga,reg);mtdcr(ebccfgd,data)
+#define mfebc(reg, data) mtdcr(ebccfga,reg);data = mfdcr(ebccfgd)
+
+
+#ifndef __ASSEMBLY__
+
+typedef struct
+{
+ unsigned long pllFwdDiv;
+ unsigned long pllFwdDivB;
+ unsigned long pllFbkDiv;
+ unsigned long pllPlbDiv;
+ unsigned long pllPciDiv;
+ unsigned long pllExtBusDiv;
+ unsigned long pllOpbDiv;
+ unsigned long freqVCOMhz; /* in MHz */
+ unsigned long freqProcessor;
+ unsigned long freqPLB;
+ unsigned long freqPCI;
+ unsigned long pciIntArbEn; /* Internal PCI arbiter is enabled */
+ unsigned long pciClkSync; /* PCI clock is synchronous */
+} PPC405_SYS_INFO;
+
+#endif /* _ASMLANGUAGE */
+
+#define RESET_VECTOR 0xfffffffc
+#define CACHELINE_MASK (CFG_CACHELINE_SIZE - 1) /* Address mask for cache
+ line aligned data. */
+
+#endif /* __PPC405_H__ */
+
--- /dev/null
+/*----------------------------------------------------------------------------+
+|
+| This source code has been made available to you by IBM on an AS-IS
+| basis. Anyone receiving this source is licensed under IBM
+| copyrights to use it in any way he or she deems fit, including
+| copying it, modifying it, compiling it, and redistributing it either
+| with or without modifications. No license under IBM patents or
+| patent applications is to be implied by the copyright license.
+|
+| Any user of this software should understand that IBM cannot provide
+| technical support for this software and will not be responsible for
+| any consequences resulting from the use of this software.
+|
+| Any person who transfers this source code or any derivative work
+| must include the IBM copyright notice, this paragraph, and the
+| preceding two paragraphs in the transferred software.
+|
+| COPYRIGHT I B M CORPORATION 1999
+| LICENSED MATERIAL - PROGRAM PROPERTY OF I B M
++----------------------------------------------------------------------------*/
+
+#ifndef __PPC440_H__
+#define __PPC440_H__
+
+/*
+//-------------------------------------------------------------------------------
+// Special Purpose Registers
+//-------------------------------------------------------------------------------
+*/
+ #define dec 0x016 /* decrementer */
+ #define srr0 0x01a /* save/restore register 0 */
+ #define srr1 0x01b /* save/restore register 1 */
+ #define pid 0x030 /* process id */
+ #define decar 0x036 /* decrementer auto-reload */
+ #define csrr0 0x03a /* critical save/restore register 0 */
+ #define csrr1 0x03b /* critical save/restore register 1 */
+ #define dear 0x03d /* data exception address register */
+ #define esr 0x03e /* exception syndrome register */
+ #define ivpr 0x03f /* interrupt prefix register */
+ #define usprg0 0x100 /* user special purpose register general 0 */
+ #define usprg1 0x110 /* user special purpose register general 1 */
+ #define sprg1 0x111 /* special purpose register general 1 */
+ #define sprg2 0x112 /* special purpose register general 2 */
+ #define sprg3 0x113 /* special purpose register general 3 */
+ #define sprg4 0x114 /* special purpose register general 4 */
+ #define sprg5 0x115 /* special purpose register general 5 */
+ #define sprg6 0x116 /* special purpose register general 6 */
+ #define sprg7 0x117 /* special purpose register general 7 */
+ #define tbl 0x11c /* time base lower (supervisor)*/
+ #define tbu 0x11d /* time base upper (supervisor)*/
+ #define pir 0x11e /* processor id register */
+ /*#define pvr 0x11f processor version register */
+ #define dbsr 0x130 /* debug status register */
+ #define dbcr0 0x134 /* debug control register 0 */
+ #define dbcr1 0x135 /* debug control register 1 */
+ #define dbcr2 0x136 /* debug control register 2 */
+ #define iac1 0x138 /* instruction address compare 1 */
+ #define iac2 0x139 /* instruction address compare 2 */
+ #define iac3 0x13a /* instruction address compare 3 */
+ #define iac4 0x13b /* instruction address compare 4 */
+ #define dac1 0x13c /* data address compare 1 */
+ #define dac2 0x13d /* data address compare 2 */
+ #define dvc1 0x13e /* data value compare 1 */
+ #define dvc2 0x13f /* data value compare 2 */
+ #define tsr 0x150 /* timer status register */
+ #define tcr 0x154 /* timer control register */
+ #define ivor0 0x190 /* interrupt vector offset register 0 */
+ #define ivor1 0x191 /* interrupt vector offset register 1 */
+ #define ivor2 0x192 /* interrupt vector offset register 2 */
+ #define ivor3 0x193 /* interrupt vector offset register 3 */
+ #define ivor4 0x194 /* interrupt vector offset register 4 */
+ #define ivor5 0x195 /* interrupt vector offset register 5 */
+ #define ivor6 0x196 /* interrupt vector offset register 6 */
+ #define ivor7 0x197 /* interrupt vector offset register 7 */
+ #define ivor8 0x198 /* interrupt vector offset register 8 */
+ #define ivor9 0x199 /* interrupt vector offset register 9 */
+ #define ivor10 0x19a /* interrupt vector offset register 10 */
+ #define ivor11 0x19b /* interrupt vector offset register 11 */
+ #define ivor12 0x19c /* interrupt vector offset register 12 */
+ #define ivor13 0x19d /* interrupt vector offset register 13 */
+ #define ivor14 0x19e /* interrupt vector offset register 14 */
+ #define ivor15 0x19f /* interrupt vector offset register 15 */
+ #define inv0 0x370 /* instruction cache normal victim 0 */
+ #define inv1 0x371 /* instruction cache normal victim 1 */
+ #define inv2 0x372 /* instruction cache normal victim 2 */
+ #define inv3 0x373 /* instruction cache normal victim 3 */
+ #define itv0 0x374 /* instruction cache transient victim 0 */
+ #define itv1 0x375 /* instruction cache transient victim 1 */
+ #define itv2 0x376 /* instruction cache transient victim 2 */
+ #define itv3 0x377 /* instruction cache transient victim 3 */
+ #define dnv0 0x390 /* data cache normal victim 0 */
+ #define dnv1 0x391 /* data cache normal victim 1 */
+ #define dnv2 0x392 /* data cache normal victim 2 */
+ #define dnv3 0x393 /* data cache normal victim 3 */
+ #define dtv0 0x394 /* data cache transient victim 0 */
+ #define dtv1 0x395 /* data cache transient victim 1 */
+ #define dtv2 0x396 /* data cache transient victim 2 */
+ #define dtv3 0x397 /* data cache transient victim 3 */
+ #define dvlim 0x398 /* data cache victim limit */
+ #define ivlim 0x399 /* instruction cache victim limit */
+ #define rstcfg 0x39b /* reset configuration */
+ #define dcdbtrl 0x39c /* data cache debug tag register low */
+ #define dcdbtrh 0x39d /* data cache debug tag register high */
+ #define icdbtrl 0x39e /* instruction cache debug tag register low */
+ #define icdbtrh 0x39f /* instruction cache debug tag register high */
+ #define mmucr 0x3b2 /* mmu control register */
+ #define ccr0 0x3b3 /* core configuration register 0 */
+ #define icdbdr 0x3d3 /* instruction cache debug data register */
+ #define dbdr 0x3f3 /* debug data register */
+
+/******************************************************************************
+ * DCRs & Related
+ ******************************************************************************/
+
+/*-----------------------------------------------------------------------------
+ | SDRAM Controller
+ +----------------------------------------------------------------------------*/
+#define SDRAM_DCR_BASE 0x10
+#define memcfga (SDRAM_DCR_BASE+0x0) /* Memory configuration address reg */
+#define memcfgd (SDRAM_DCR_BASE+0x1) /* Memory configuration data reg */
+
+ /* values for memcfga register - indirect addressing of these regs */
+ #define mem_besr0_clr 0x0000 /* bus error status reg 0 (clr) */
+ #define mem_besr0_set 0x0004 /* bus error status reg 0 (set) */
+ #define mem_besr1_clr 0x0008 /* bus error status reg 1 (clr) */
+ #define mem_besr1_set 0x000c /* bus error status reg 1 (set) */
+ #define mem_bear 0x0010 /* bus error address reg */
+ #define mem_mirq_clr 0x0011 /* bus master interrupt (clr) */
+ #define mem_mirq_set 0x0012 /* bus master interrupt (set) */
+ #define mem_slio 0x0018 /* ddr sdram slave interface options */
+ #define mem_cfg0 0x0020 /* ddr sdram options 0 */
+ #define mem_cfg1 0x0021 /* ddr sdram options 1 */
+ #define mem_devopt 0x0022 /* ddr sdram device options */
+ #define mem_mcsts 0x0024 /* memory controller status */
+ #define mem_rtr 0x0030 /* refresh timer register */
+ #define mem_pmit 0x0034 /* power management idle timer */
+ #define mem_uabba 0x0038 /* plb UABus base address */
+ #define mem_b0cr 0x0040 /* ddr sdram bank 0 configuration */
+ #define mem_b1cr 0x0044 /* ddr sdram bank 1 configuration */
+ #define mem_b2cr 0x0048 /* ddr sdram bank 2 configuration */
+ #define mem_b3cr 0x004c /* ddr sdram bank 3 configuration */
+ #define mem_tr0 0x0080 /* sdram timing register 0 */
+ #define mem_tr1 0x0081 /* sdram timing register 1 */
+ #define mem_clktr 0x0082 /* ddr clock timing register */
+ #define mem_wddctr 0x0083 /* write data/dm/dqs clock timing reg */
+ #define mem_dlycal 0x0084 /* delay line calibration register */
+ #define mem_eccesr 0x0098 /* ECC error status */
+
+/*-----------------------------------------------------------------------------
+ | Extrnal Bus Controller
+ +----------------------------------------------------------------------------*/
+#define EBC_DCR_BASE 0x12
+#define ebccfga (EBC_DCR_BASE+0x0) /* External bus controller addr reg */
+#define ebccfgd (EBC_DCR_BASE+0x1) /* External bus controller data reg */
+ /* values for ebccfga register - indirect addressing of these regs */
+ #define pb0cr 0x00 /* periph bank 0 config reg */
+ #define pb1cr 0x01 /* periph bank 1 config reg */
+ #define pb2cr 0x02 /* periph bank 2 config reg */
+ #define pb3cr 0x03 /* periph bank 3 config reg */
+ #define pb4cr 0x04 /* periph bank 4 config reg */
+ #define pb5cr 0x05 /* periph bank 5 config reg */
+ #define pb6cr 0x06 /* periph bank 6 config reg */
+ #define pb7cr 0x07 /* periph bank 7 config reg */
+ #define pb0ap 0x10 /* periph bank 0 access parameters */
+ #define pb1ap 0x11 /* periph bank 1 access parameters */
+ #define pb2ap 0x12 /* periph bank 2 access parameters */
+ #define pb3ap 0x13 /* periph bank 3 access parameters */
+ #define pb4ap 0x14 /* periph bank 4 access parameters */
+ #define pb5ap 0x15 /* periph bank 5 access parameters */
+ #define pb6ap 0x16 /* periph bank 6 access parameters */
+ #define pb7ap 0x17 /* periph bank 7 access parameters */
+ #define pbear 0x20 /* periph bus error addr reg */
+ #define pbesr 0x21 /* periph bus error status reg */
+ #define xbcfg 0x23 /* external bus configuration reg */
+ #define xbcid 0x23 /* external bus core id reg */
+
+/*-----------------------------------------------------------------------------
+ | Internal SRAM
+ +----------------------------------------------------------------------------*/
+#define ISRAM0_DCR_BASE 0x020
+#define isram0_sb0cr (ISRAM0_DCR_BASE+0x00) /* SRAM bank config 0*/
+#define isram0_sb1cr (ISRAM0_DCR_BASE+0x01) /* SRAM bank config 1*/
+#define isram0_sb2cr (ISRAM0_DCR_BASE+0x02) /* SRAM bank config 2*/
+#define isram0_sb3cr (ISRAM0_DCR_BASE+0x03) /* SRAM bank config 3*/
+#define isram0_bear (ISRAM0_DCR_BASE+0x04) /* SRAM bus error addr reg */
+#define isram0_besr0 (ISRAM0_DCR_BASE+0x05) /* SRAM bus error status reg 0 */
+#define isram0_besr1 (ISRAM0_DCR_BASE+0x06) /* SRAM bus error status reg 1 */
+#define isram0_pmeg (ISRAM0_DCR_BASE+0x07) /* SRAM power management */
+#define isram0_cid (ISRAM0_DCR_BASE+0x08) /* SRAM bus core id reg */
+#define isram0_revid (ISRAM0_DCR_BASE+0x09) /* SRAM bus revision id reg */
+#define isram0_dpc (ISRAM0_DCR_BASE+0x0a) /* SRAM data parity check reg */
+
+/*-----------------------------------------------------------------------------
+ | On-Chip Buses
+ +----------------------------------------------------------------------------*/
+/* TODO: as needed */
+
+/*-----------------------------------------------------------------------------
+ | Clocking, Power Management and Chip Control
+ +----------------------------------------------------------------------------*/
+#define CNTRL_DCR_BASE 0x0b0
+
+#define cpc0_sr (CNTRL_DCR_BASE+0x00) /* CPM status register */
+#define cpc0_er (CNTRL_DCR_BASE+0x01) /* CPM enable register */
+#define cpc0_fr (CNTRL_DCR_BASE+0x02) /* CPM force register */
+
+#define cpc0_sys0 (CNTRL_DCR_BASE+0x30) /* System configuration reg 0 */
+#define cpc0_sys1 (CNTRL_DCR_BASE+0x31) /* System configuration reg 1 */
+#define cpc0_cust0 (CNTRL_DCR_BASE+0x32) /* Customer configuration reg 0 */
+#define cpc0_cust1 (CNTRL_DCR_BASE+0x33) /* Customer configuration reg 1 */
+
+#define cntrl0 (CNTRL_DCR_BASE+0x3b) /* Control 0 register */
+#define cntrl1 (CNTRL_DCR_BASE+0x3a) /* Control 1 register */
+
+/*-----------------------------------------------------------------------------
+ | Universal interrupt controller
+ +----------------------------------------------------------------------------*/
+#define UIC0_DCR_BASE 0xc0
+#define uic0sr (UIC0_DCR_BASE+0x0) /* UIC0 status */
+#define uic0er (UIC0_DCR_BASE+0x2) /* UIC0 enable */
+#define uic0cr (UIC0_DCR_BASE+0x3) /* UIC0 critical */
+#define uic0pr (UIC0_DCR_BASE+0x4) /* UIC0 polarity */
+#define uic0tr (UIC0_DCR_BASE+0x5) /* UIC0 triggering */
+#define uic0msr (UIC0_DCR_BASE+0x6) /* UIC0 masked status */
+#define uic0vr (UIC0_DCR_BASE+0x7) /* UIC0 vector */
+#define uic0vcr (UIC0_DCR_BASE+0x8) /* UIC0 vector configuration */
+
+#define UIC1_DCR_BASE 0xd0
+#define uic1sr (UIC1_DCR_BASE+0x0) /* UIC1 status */
+#define uic1er (UIC1_DCR_BASE+0x2) /* UIC1 enable */
+#define uic1cr (UIC1_DCR_BASE+0x3) /* UIC1 critical */
+#define uic1pr (UIC1_DCR_BASE+0x4) /* UIC1 polarity */
+#define uic1tr (UIC1_DCR_BASE+0x5) /* UIC1 triggering */
+#define uic1msr (UIC1_DCR_BASE+0x6) /* UIC1 masked status */
+#define uic1vr (UIC1_DCR_BASE+0x7) /* UIC1 vector */
+#define uic1vcr (UIC1_DCR_BASE+0x8) /* UIC1 vector configuration */
+
+/* The following is for compatibility with 405 code */
+#define uicsr uic0sr
+#define uicer uic0er
+#define uiccr uic0cr
+#define uicpr uic0pr
+#define uictr uic0tr
+#define uicmsr uic0msr
+#define uicvr uic0vr
+#define uicvcr uic0vcr
+
+/*-----------------------------------------------------------------------------
+ | DMA
+ +----------------------------------------------------------------------------*/
+#define DMA_DCR_BASE 0x100
+#define dmacr0 (DMA_DCR_BASE+0x00) /* DMA channel control register 0 */
+#define dmact0 (DMA_DCR_BASE+0x01) /* DMA count register 0 */
+#define dmasah0 (DMA_DCR_BASE+0x02) /* DMA source address high 0 */
+#define dmasal0 (DMA_DCR_BASE+0x03) /* DMA source address low 0 */
+#define dmadah0 (DMA_DCR_BASE+0x04) /* DMA destination address high 0 */
+#define dmadal0 (DMA_DCR_BASE+0x05) /* DMA destination address low 0 */
+#define dmasgh0 (DMA_DCR_BASE+0x06) /* DMA scatter/gather desc addr high 0 */
+#define dmasgl0 (DMA_DCR_BASE+0x07) /* DMA scatter/gather desc addr low 0 */
+#define dmacr1 (DMA_DCR_BASE+0x08) /* DMA channel control register 1 */
+#define dmact1 (DMA_DCR_BASE+0x09) /* DMA count register 1 */
+#define dmasah1 (DMA_DCR_BASE+0x0a) /* DMA source address high 1 */
+#define dmasal1 (DMA_DCR_BASE+0x0b) /* DMA source address low 1 */
+#define dmadah1 (DMA_DCR_BASE+0x0c) /* DMA destination address high 1 */
+#define dmadal1 (DMA_DCR_BASE+0x0d) /* DMA destination address low 1 */
+#define dmasgh1 (DMA_DCR_BASE+0x0e) /* DMA scatter/gather desc addr high 1 */
+#define dmasgl1 (DMA_DCR_BASE+0x0f) /* DMA scatter/gather desc addr low 1 */
+#define dmacr2 (DMA_DCR_BASE+0x10) /* DMA channel control register 2 */
+#define dmact2 (DMA_DCR_BASE+0x11) /* DMA count register 2 */
+#define dmasah2 (DMA_DCR_BASE+0x12) /* DMA source address high 2 */
+#define dmasal2 (DMA_DCR_BASE+0x13) /* DMA source address low 2 */
+#define dmadah2 (DMA_DCR_BASE+0x14) /* DMA destination address high 2 */
+#define dmadal2 (DMA_DCR_BASE+0x15) /* DMA destination address low 2 */
+#define dmasgh2 (DMA_DCR_BASE+0x16) /* DMA scatter/gather desc addr high 2 */
+#define dmasgl2 (DMA_DCR_BASE+0x17) /* DMA scatter/gather desc addr low 2 */
+#define dmacr3 (DMA_DCR_BASE+0x18) /* DMA channel control register 2 */
+#define dmact3 (DMA_DCR_BASE+0x19) /* DMA count register 2 */
+#define dmasah3 (DMA_DCR_BASE+0x1a) /* DMA source address high 2 */
+#define dmasal3 (DMA_DCR_BASE+0x1b) /* DMA source address low 2 */
+#define dmadah3 (DMA_DCR_BASE+0x1c) /* DMA destination address high 2 */
+#define dmadal3 (DMA_DCR_BASE+0x1d) /* DMA destination address low 2 */
+#define dmasgh3 (DMA_DCR_BASE+0x1e) /* DMA scatter/gather desc addr high 2 */
+#define dmasgl3 (DMA_DCR_BASE+0x1f) /* DMA scatter/gather desc addr low 2 */
+#define dmasr (DMA_DCR_BASE+0x20) /* DMA status register */
+#define dmasgc (DMA_DCR_BASE+0x23) /* DMA scatter/gather command register */
+#define dmaslp (DMA_DCR_BASE+0x25) /* DMA sleep mode register */
+#define dmapol (DMA_DCR_BASE+0x26) /* DMA polarity configuration register */
+
+/*-----------------------------------------------------------------------------
+ | Memory Access Layer
+ +----------------------------------------------------------------------------*/
+#define MAL_DCR_BASE 0x180
+#define malmcr (MAL_DCR_BASE+0x00) /* MAL Config reg */
+#define malesr (MAL_DCR_BASE+0x01) /* Error Status reg (Read/Clear) */
+#define malier (MAL_DCR_BASE+0x02) /* Interrupt enable reg */
+#define maldbr (MAL_DCR_BASE+0x03) /* Mal Debug reg (Read only) */
+#define maltxcasr (MAL_DCR_BASE+0x04) /* TX Channel active reg (set) */
+#define maltxcarr (MAL_DCR_BASE+0x05) /* TX Channel active reg (Reset) */
+#define maltxeobisr (MAL_DCR_BASE+0x06) /* TX End of buffer int status reg */
+#define maltxdeir (MAL_DCR_BASE+0x07) /* TX Descr. Error Int reg */
+#define maltxtattrr (MAL_DCR_BASE+0x08) /* TX PLB attribute reg */
+#define maltxbattr (MAL_DCR_BASE+0x09) /* TX descriptor base addr reg */
+#define malrxcasr (MAL_DCR_BASE+0x10) /* RX Channel active reg (set) */
+#define malrxcarr (MAL_DCR_BASE+0x11) /* RX Channel active reg (Reset) */
+#define malrxeobisr (MAL_DCR_BASE+0x12) /* RX End of buffer int status reg */
+#define malrxdeir (MAL_DCR_BASE+0x13) /* RX Descr. Error Int reg */
+#define malrxtattrr (MAL_DCR_BASE+0x14) /* RX PLB attribute reg */
+#define malrxbattr (MAL_DCR_BASE+0x15) /* RX descriptor base addr reg */
+#define maltxctp0r (MAL_DCR_BASE+0x20) /* TX 0 Channel table pointer reg */
+#define maltxctp1r (MAL_DCR_BASE+0x21) /* TX 1 Channel table pointer reg */
+#define malrxctp0r (MAL_DCR_BASE+0x40) /* RX 0 Channel table pointer reg */
+#define malrxctp1r (MAL_DCR_BASE+0x41) /* RX 1 Channel table pointer reg */
+#define malrcbs0 (MAL_DCR_BASE+0x60) /* RX 0 Channel buffer size reg */
+
+/*---------------------------------------------------------------------------+
+| Universal interrupt controller 0 interrupts (UIC0)
++---------------------------------------------------------------------------*/
+#define UIC_U0 0x80000000 /* UART 0 */
+#define UIC_U1 0x40000000 /* UART 1 */
+#define UIC_IIC0 0x20000000 /* IIC */
+#define UIC_IIC1 0x10000000 /* IIC */
+#define UIC_PIM 0x08000000 /* PCI inbound message */
+#define UIC_PCRW 0x04000000 /* PCI command register write */
+#define UIC_PPM 0x02000000 /* PCI power management */
+#define UIC_MSI0 0x01000000 /* PCI MSI level 0 */
+#define UIC_MSI1 0x00800000 /* PCI MSI level 1 */
+#define UIC_MSI2 0x00400000 /* PCI MSI level 2 */
+#define UIC_MTE 0x00200000 /* MAL TXEOB */
+#define UIC_MRE 0x00100000 /* MAL RXEOB */
+#define UIC_D0 0x00080000 /* DMA channel 0 */
+#define UIC_D1 0x00040000 /* DMA channel 1 */
+#define UIC_D2 0x00020000 /* DMA channel 2 */
+#define UIC_D3 0x00010000 /* DMA channel 3 */
+#define UIC_RSVD0 0x00008000 /* Reserved */
+#define UIC_RSVD1 0x00004000 /* Reserved */
+#define UIC_CT0 0x00002000 /* GPT compare timer 0 */
+#define UIC_CT1 0x00001000 /* GPT compare timer 1 */
+#define UIC_CT2 0x00000800 /* GPT compare timer 2 */
+#define UIC_CT3 0x00000400 /* GPT compare timer 3 */
+#define UIC_CT4 0x00000200 /* GPT compare timer 4 */
+#define UIC_EIR0 0x00000100 /* External interrupt 0 */
+#define UIC_EIR1 0x00000080 /* External interrupt 1 */
+#define UIC_EIR2 0x00000040 /* External interrupt 2 */
+#define UIC_EIR3 0x00000020 /* External interrupt 3 */
+#define UIC_EIR4 0x00000010 /* External interrupt 4 */
+#define UIC_EIR5 0x00000008 /* External interrupt 5 */
+#define UIC_EIR6 0x00000004 /* External interrupt 6 */
+#define UIC_UIC1NC 0x00000002 /* UIC1 non-critical interrupt */
+#define UIC_UIC1C 0x00000001 /* UIC1 critical interrupt */
+
+/* For compatibility with 405 code */
+#define UIC_MAL_TXEOB UIC_MTE
+#define UIC_MAL_RXEOB UIC_MRE
+
+/*---------------------------------------------------------------------------+
+| Universal interrupt controller 1 interrupts (UIC1)
++---------------------------------------------------------------------------*/
+#define UIC_MS 0x80000000 /* MAL SERR */
+#define UIC_MTDE 0x40000000 /* MAL TXDE */
+#define UIC_MRDE 0x20000000 /* MAL RXDE */
+#define UIC_DEUE 0x10000000 /* DDR SDRAM ECC uncorrectible error*/
+#define UIC_DECE 0x08000000 /* DDR SDRAM correctible error */
+#define UIC_EBCO 0x04000000 /* EBCO interrupt status */
+#define UIC_EBMI 0x02000000 /* EBMI interrupt status */
+#define UIC_OPB 0x01000000 /* OPB to PLB bridge interrupt stat */
+#define UIC_MSI3 0x00800000 /* PCI MSI level 3 */
+#define UIC_MSI4 0x00400000 /* PCI MSI level 4 */
+#define UIC_MSI5 0x00200000 /* PCI MSI level 5 */
+#define UIC_MSI6 0x00100000 /* PCI MSI level 6 */
+#define UIC_MSI7 0x00080000 /* PCI MSI level 7 */
+#define UIC_MSI8 0x00040000 /* PCI MSI level 8 */
+#define UIC_MSI9 0x00020000 /* PCI MSI level 9 */
+#define UIC_MSI10 0x00010000 /* PCI MSI level 10 */
+#define UIC_MSI11 0x00008000 /* PCI MSI level 11 */
+#define UIC_PPMI 0x00004000 /* PPM interrupt status */
+#define UIC_EIR7 0x00002000 /* External interrupt 7 */
+#define UIC_EIR8 0x00001000 /* External interrupt 8 */
+#define UIC_EIR9 0x00000800 /* External interrupt 9 */
+#define UIC_EIR10 0x00000400 /* External interrupt 10 */
+#define UIC_EIR11 0x00000200 /* External interrupt 11 */
+#define UIC_EIR12 0x00000100 /* External interrupt 12 */
+#define UIC_SRE 0x00000080 /* Serial ROM error */
+#define UIC_RSVD2 0x00000040 /* Reserved */
+#define UIC_RSVD3 0x00000020 /* Reserved */
+#define UIC_PAE 0x00000010 /* PCI asynchronous error */
+#define UIC_ETH0 0x00000008 /* Ethernet 0 */
+#define UIC_EWU0 0x00000004 /* Ethernet 0 wakeup */
+#define UIC_ETH1 0x00000002 /* Ethernet 1 */
+#define UIC_EWU1 0x00000001 /* Ethernet 1 wakeup */
+
+/* For compatibility with 405 code */
+#define UIC_MAL_SERR UIC_MS
+#define UIC_MAL_TXDE UIC_MTDE
+#define UIC_MAL_RXDE UIC_MRDE
+#define UIC_ENET UIC_ETH0
+
+/*-----------------------------------------------------------------------------+
+| Clocking
++-----------------------------------------------------------------------------*/
+#define PLLSYS0_TUNE_MASK 0xffc00000 /* PLL TUNE bits */
+#define PLLSYS0_FB_DIV_MASK 0x003c0000 /* Feedback divisor */
+#define PLLSYS0_FWD_DIV_A_MASK 0x00038000 /* Forward divisor A */
+#define PLLSYS0_FWD_DIV_B_MASK 0x00007000 /* Forward divisor B */
+#define PLLSYS0_OPB_DIV_MASK 0x00000c00 /* OPB divisor */
+#define PLLSYS0_EPB_DIV_MASK 0x00000300 /* EPB divisor */
+#define PLLSYS0_EXTSL_MASK 0x00000080 /* PerClk feedback path */
+#define PLLSYS0_RW_MASK 0x00000060 /* ROM width */
+#define PLLSYS0_RL_MASK 0x00000010 /* ROM location */
+#define PLLSYS0_ZMII_SEL_MASK 0x0000000c /* ZMII selection */
+#define PLLSYS0_BYPASS_MASK 0x00000002 /* Bypass PLL */
+#define PLLSYS0_NTO1_MASK 0x00000001 /* CPU:PLB N-to-1 ratio */
+
+#define PLL_VCO_FREQ_MIN 500 /* Min VCO freq (MHz) */
+#define PLL_VCO_FREQ_MAX 1000 /* Max VCO freq (MHz) */
+#define PLL_CPU_FREQ_MAX 400 /* Max CPU freq (MHz) */
+#define PLL_PLB_FREQ_MAX 133 /* Max PLB freq (MHz) */
+
+/*-----------------------------------------------------------------------------
+| IIC Register Offsets
+'----------------------------------------------------------------------------*/
+#define IICMDBUF 0x00
+#define IICSDBUF 0x02
+#define IICLMADR 0x04
+#define IICHMADR 0x05
+#define IICCNTL 0x06
+#define IICMDCNTL 0x07
+#define IICSTS 0x08
+#define IICEXTSTS 0x09
+#define IICLSADR 0x0A
+#define IICHSADR 0x0B
+#define IICCLKDIV 0x0C
+#define IICINTRMSK 0x0D
+#define IICXFRCNT 0x0E
+#define IICXTCNTLSS 0x0F
+#define IICDIRECTCNTL 0x10
+
+/*-----------------------------------------------------------------------------
+| UART Register Offsets
+'----------------------------------------------------------------------------*/
+#define DATA_REG 0x00
+#define DL_LSB 0x00
+#define DL_MSB 0x01
+#define INT_ENABLE 0x01
+#define FIFO_CONTROL 0x02
+#define LINE_CONTROL 0x03
+#define MODEM_CONTROL 0x04
+#define LINE_STATUS 0x05
+#define MODEM_STATUS 0x06
+#define SCRATCH 0x07
+
+
+/*
+ * Macros for accessing the indirect EBC registers
+ */
+#define mtebc(reg, data) mtdcr(ebccfga,reg);mtdcr(ebccfgd,data)
+#define mfebc(reg, data) mtdcr(ebccfga,reg);data = mfdcr(ebccfgd)
+
+/*
+ * Macros for accessing the indirect SDRAM controller registers
+ */
+#define mtsdram(reg, data) mtdcr(memcfga,reg);mtdcr(memcfgd,data)
+#define mfsdram(reg, data) mtdcr(memcfga,reg);data = mfdcr(memcfgd)
+
+
+#ifndef __ASSEMBLY__
+
+typedef struct
+{
+ unsigned long pllFwdDivA;
+ unsigned long pllFwdDivB;
+ unsigned long pllFbkDiv;
+ unsigned long pllOpbDiv;
+ unsigned long pllExtBusDiv;
+ unsigned long freqVCOMhz; /* in MHz */
+ unsigned long freqProcessor;
+ unsigned long freqPLB;
+ unsigned long freqOPB;
+ unsigned long freqEPB;
+} PPC440_SYS_INFO;
+
+#endif /* _ASMLANGUAGE */
+
+#define RESET_VECTOR 0xfffffffc
+#define CACHELINE_MASK (CFG_CACHELINE_SIZE - 1) /* Address mask for cache
+ line aligned data. */
+
+#endif /* __PPC440_H__ */
+
#ifndef __PPC4XX_H__
#define __PPC4XX_H__
-/*
-//-------------------------------------------------------------------------------
-// Special Purpose Registers
-//-------------------------------------------------------------------------------
-*/
- #define srr2 0x3de /* save/restore register 2 */
- #define srr3 0x3df /* save/restore register 3 */
- #define dbsr 0x3f0 /* debug status register */
- #define dbcr0 0x3f2 /* debug control register 0 */
- #define dbcr1 0x3bd /* debug control register 1 */
- #define iac1 0x3f4 /* instruction address comparator 1 */
- #define iac2 0x3f5 /* instruction address comparator 2 */
- #define iac3 0x3b4 /* instruction address comparator 3 */
- #define iac4 0x3b5 /* instruction address comparator 4 */
- #define dac1 0x3f6 /* data address comparator 1 */
- #define dac2 0x3f7 /* data address comparator 2 */
- #define dccr 0x3fa /* data cache control register */
- #define iccr 0x3fb /* instruction cache control register */
- #define esr 0x3d4 /* execption syndrome register */
- #define dear 0x3d5 /* data exeption address register */
- #define evpr 0x3d6 /* exeption vector prefix register */
- #define tsr 0x3d8 /* timer status register */
- #define tcr 0x3da /* timer control register */
- #define pit 0x3db /* programmable interval timer */
- #define sgr 0x3b9 /* storage guarded reg */
- #define dcwr 0x3ba /* data cache write-thru reg*/
- #define sler 0x3bb /* storage little-endian reg */
- #define cdbcr 0x3d7 /* cache debug cntrl reg */
- #define icdbdr 0x3d3 /* instr cache dbug data reg*/
- #define ccr0 0x3b3 /* core configuration register */
- #define dvc1 0x3b6 /* data value compare register 1 */
- #define dvc2 0x3b7 /* data value compare register 2 */
- #define pid 0x3b1 /* process ID */
- #define su0r 0x3bc /* storage user-defined register 0 */
- #define zpr 0x3b0 /* zone protection regsiter */
- #define tbl 0x11c /* time base lower - privileged write */
- #define tbu 0x11d /* time base upper - privileged write */
-
- #define sprg4r 0x104 /* Special purpose general 4 - read only */
- #define sprg5r 0x105 /* Special purpose general 5 - read only */
- #define sprg6r 0x106 /* Special purpose general 6 - read only */
- #define sprg7r 0x107 /* Special purpose general 7 - read only */
- #define sprg4w 0x114 /* Special purpose general 4 - write only */
- #define sprg5w 0x115 /* Special purpose general 5 - write only */
- #define sprg6w 0x116 /* Special purpose general 6 - write only */
- #define sprg7w 0x117 /* Special purpose general 7 - write only */
-
-
-/******************************************************************************
- * Special for PPC405GP
- ******************************************************************************/
-
-/******************************************************************************
- * DMA
- ******************************************************************************/
-#define DMA_DCR_BASE 0x100
-#define dmacr0 (DMA_DCR_BASE+0x00) /* DMA channel control register 0 */
-#define dmact0 (DMA_DCR_BASE+0x01) /* DMA count register 0 */
-#define dmada0 (DMA_DCR_BASE+0x02) /* DMA destination address register 0 */
-#define dmasa0 (DMA_DCR_BASE+0x03) /* DMA source address register 0 */
-#define dmasb0 (DMA_DCR_BASE+0x04) /* DMA scatter/gather descriptor addr 0 */
-#define dmacr1 (DMA_DCR_BASE+0x08) /* DMA channel control register 1 */
-#define dmact1 (DMA_DCR_BASE+0x09) /* DMA count register 1 */
-#define dmada1 (DMA_DCR_BASE+0x0a) /* DMA destination address register 1 */
-#define dmasa1 (DMA_DCR_BASE+0x0b) /* DMA source address register 1 */
-#define dmasb1 (DMA_DCR_BASE+0x0c) /* DMA scatter/gather descriptor addr 1 */
-#define dmacr2 (DMA_DCR_BASE+0x10) /* DMA channel control register 2 */
-#define dmact2 (DMA_DCR_BASE+0x11) /* DMA count register 2 */
-#define dmada2 (DMA_DCR_BASE+0x12) /* DMA destination address register 2 */
-#define dmasa2 (DMA_DCR_BASE+0x13) /* DMA source address register 2 */
-#define dmasb2 (DMA_DCR_BASE+0x14) /* DMA scatter/gather descriptor addr 2 */
-#define dmacr3 (DMA_DCR_BASE+0x18) /* DMA channel control register 3 */
-#define dmact3 (DMA_DCR_BASE+0x19) /* DMA count register 3 */
-#define dmada3 (DMA_DCR_BASE+0x1a) /* DMA destination address register 3 */
-#define dmasa3 (DMA_DCR_BASE+0x1b) /* DMA source address register 3 */
-#define dmasb3 (DMA_DCR_BASE+0x1c) /* DMA scatter/gather descriptor addr 3 */
-#define dmasr (DMA_DCR_BASE+0x20) /* DMA status register */
-#define dmasgc (DMA_DCR_BASE+0x23) /* DMA scatter/gather command register */
-#define dmaadr (DMA_DCR_BASE+0x24) /* DMA address decode register */
-
-/******************************************************************************
- * Universal interrupt controller
- ******************************************************************************/
-#define UIC_DCR_BASE 0xc0
-#define uicsr (UIC_DCR_BASE+0x0) /* UIC status */
-#define uicsrs (UIC_DCR_BASE+0x1) /* UIC status set */
-#define uicer (UIC_DCR_BASE+0x2) /* UIC enable */
-#define uiccr (UIC_DCR_BASE+0x3) /* UIC critical */
-#define uicpr (UIC_DCR_BASE+0x4) /* UIC polarity */
-#define uictr (UIC_DCR_BASE+0x5) /* UIC triggering */
-#define uicmsr (UIC_DCR_BASE+0x6) /* UIC masked status */
-#define uicvr (UIC_DCR_BASE+0x7) /* UIC vector */
-#define uicvcr (UIC_DCR_BASE+0x8) /* UIC vector configuration */
-
-/*-----------------------------------------------------------------------------+
-| Universal interrupt controller interrupts
-+-----------------------------------------------------------------------------*/
-#define UIC_UART0 0x80000000 /* UART 0 */
-#define UIC_UART1 0x40000000 /* UART 1 */
-#define UIC_IIC 0x20000000 /* IIC */
-#define UIC_EXT_MAST 0x10000000 /* External Master */
-#define UIC_PCI 0x08000000 /* PCI write to command reg */
-#define UIC_DMA0 0x04000000 /* DMA chan. 0 */
-#define UIC_DMA1 0x02000000 /* DMA chan. 1 */
-#define UIC_DMA2 0x01000000 /* DMA chan. 2 */
-#define UIC_DMA3 0x00800000 /* DMA chan. 3 */
-#define UIC_EMAC_WAKE 0x00400000 /* EMAC wake up */
-#define UIC_MAL_SERR 0x00200000 /* MAL SERR */
-#define UIC_MAL_TXEOB 0x00100000 /* MAL TXEOB */
-#define UIC_MAL_RXEOB 0x00080000 /* MAL RXEOB */
-#define UIC_MAL_TXDE 0x00040000 /* MAL TXDE */
-#define UIC_MAL_RXDE 0x00020000 /* MAL RXDE */
-#define UIC_ENET 0x00010000 /* Ethernet */
-#define UIC_EXT_PCI_SERR 0x00008000 /* External PCI SERR# */
-#define UIC_ECC_CE 0x00004000 /* ECC Correctable Error */
-#define UIC_PCI_PM 0x00002000 /* PCI Power Management */
-#define UIC_EXT0 0x00000040 /* External interrupt 0 */
-#define UIC_EXT1 0x00000020 /* External interrupt 1 */
-#define UIC_EXT2 0x00000010 /* External interrupt 2 */
-#define UIC_EXT3 0x00000008 /* External interrupt 3 */
-#define UIC_EXT4 0x00000004 /* External interrupt 4 */
-#define UIC_EXT5 0x00000002 /* External interrupt 5 */
-#define UIC_EXT6 0x00000001 /* External interrupt 6 */
-
-/******************************************************************************
- * SDRAM Controller
- ******************************************************************************/
-#define SDRAM_DCR_BASE 0x10
-#define memcfga (SDRAM_DCR_BASE+0x0) /* Memory configuration address reg */
-#define memcfgd (SDRAM_DCR_BASE+0x1) /* Memory configuration data reg */
- /* values for memcfga register - indirect addressing of these regs */
- #define mem_besra 0x00 /* bus error syndrome reg a */
- #define mem_besrsa 0x04 /* bus error syndrome reg set a */
- #define mem_besrb 0x08 /* bus error syndrome reg b */
- #define mem_besrsb 0x0c /* bus error syndrome reg set b */
- #define mem_bear 0x10 /* bus error address reg */
- #define mem_mcopt1 0x20 /* memory controller options 1 */
- #define mem_rtr 0x30 /* refresh timer reg */
- #define mem_pmit 0x34 /* power management idle timer */
- #define mem_mb0cf 0x40 /* memory bank 0 configuration */
- #define mem_mb1cf 0x44 /* memory bank 1 configuration */
- #define mem_mb2cf 0x48 /* memory bank 2 configuration */
- #define mem_mb3cf 0x4c /* memory bank 3 configuration */
- #define mem_sdtr1 0x80 /* timing reg 1 */
- #define mem_ecccf 0x94 /* ECC configuration */
- #define mem_eccerr 0x98 /* ECC error status */
-
-/******************************************************************************
- * Decompression Controller
- ******************************************************************************/
-#define DECOMP_DCR_BASE 0x14
-#define kiar (DECOMP_DCR_BASE+0x0) /* Decompression controller addr reg */
-#define kidr (DECOMP_DCR_BASE+0x1) /* Decompression controller data reg */
- /* values for kiar register - indirect addressing of these regs */
- #define kitor0 0x00 /* index table origin register 0 */
- #define kitor1 0x01 /* index table origin register 1 */
- #define kitor2 0x02 /* index table origin register 2 */
- #define kitor3 0x03 /* index table origin register 3 */
- #define kaddr0 0x04 /* address decode definition regsiter 0 */
- #define kaddr1 0x05 /* address decode definition regsiter 1 */
- #define kconf 0x40 /* decompression core config register */
- #define kid 0x41 /* decompression core ID register */
- #define kver 0x42 /* decompression core version # reg */
- #define kpear 0x50 /* bus error addr reg (PLB addr) */
- #define kbear 0x51 /* bus error addr reg (DCP to EBIU addr)*/
- #define kesr0 0x52 /* bus error status reg 0 (R/clear) */
- #define kesr0s 0x53 /* bus error status reg 0 (set) */
- /* There are 0x400 of the following registers, from krom0 to krom3ff*/
- /* Only the first one is given here. */
- #define krom0 0x400 /* SRAM/ROM read/write */
-
-/******************************************************************************
- * Power Management
- ******************************************************************************/
-#define POWERMAN_DCR_BASE 0xb8
-#define cpmsr (POWERMAN_DCR_BASE+0x0) /* Power management status */
-#define cpmer (POWERMAN_DCR_BASE+0x1) /* Power management enable */
-#define cpmfr (POWERMAN_DCR_BASE+0x2) /* Power management force */
-
-/******************************************************************************
- * Extrnal Bus Controller
- ******************************************************************************/
-#define EBC_DCR_BASE 0x12
-#define ebccfga (EBC_DCR_BASE+0x0) /* External bus controller addr reg */
-#define ebccfgd (EBC_DCR_BASE+0x1) /* External bus controller data reg */
- /* values for ebccfga register - indirect addressing of these regs */
- #define pb0cr 0x00 /* periph bank 0 config reg */
- #define pb1cr 0x01 /* periph bank 1 config reg */
- #define pb2cr 0x02 /* periph bank 2 config reg */
- #define pb3cr 0x03 /* periph bank 3 config reg */
- #define pb4cr 0x04 /* periph bank 4 config reg */
- #define pb5cr 0x05 /* periph bank 5 config reg */
- #define pb6cr 0x06 /* periph bank 6 config reg */
- #define pb7cr 0x07 /* periph bank 7 config reg */
- #define pb0ap 0x10 /* periph bank 0 access parameters */
- #define pb1ap 0x11 /* periph bank 1 access parameters */
- #define pb2ap 0x12 /* periph bank 2 access parameters */
- #define pb3ap 0x13 /* periph bank 3 access parameters */
- #define pb4ap 0x14 /* periph bank 4 access parameters */
- #define pb5ap 0x15 /* periph bank 5 access parameters */
- #define pb6ap 0x16 /* periph bank 6 access parameters */
- #define pb7ap 0x17 /* periph bank 7 access parameters */
- #define pbear 0x20 /* periph bus error addr reg */
- #define pbesr0 0x21 /* periph bus error status reg 0 */
- #define pbesr1 0x22 /* periph bus error status reg 1 */
- #define epcr 0x23 /* external periph control reg */
-
-/******************************************************************************
- * Control
- ******************************************************************************/
-#define CNTRL_DCR_BASE 0x0b0
-#define pllmd (CNTRL_DCR_BASE+0x0) /* PLL mode register */
-#define cntrl0 (CNTRL_DCR_BASE+0x1) /* Control 0 register */
-#define cntrl1 (CNTRL_DCR_BASE+0x2) /* Control 1 register */
-#define reset (CNTRL_DCR_BASE+0x3) /* reset register */
-#define strap (CNTRL_DCR_BASE+0x4) /* strap register */
-
-/* Bit definitions */
-#define PLLMR_FWD_DIV_MASK 0xE0000000 /* Forward Divisor */
-#define PLLMR_FWD_DIV_BYPASS 0xE0000000
-#define PLLMR_FWD_DIV_3 0xA0000000
-#define PLLMR_FWD_DIV_4 0x80000000
-#define PLLMR_FWD_DIV_6 0x40000000
-
-#define PLLMR_FB_DIV_MASK 0x1E000000 /* Feedback Divisor */
-#define PLLMR_FB_DIV_1 0x02000000
-#define PLLMR_FB_DIV_2 0x04000000
-#define PLLMR_FB_DIV_3 0x06000000
-#define PLLMR_FB_DIV_4 0x08000000
-
-#define PLLMR_TUNING_MASK 0x01F80000
-
-#define PLLMR_CPU_TO_PLB_MASK 0x00060000 /* CPU:PLB Frequency Divisor */
-#define PLLMR_CPU_PLB_DIV_1 0x00000000
-#define PLLMR_CPU_PLB_DIV_2 0x00020000
-#define PLLMR_CPU_PLB_DIV_3 0x00040000
-#define PLLMR_CPU_PLB_DIV_4 0x00060000
-
-#define PLLMR_OPB_TO_PLB_MASK 0x00018000 /* OPB:PLB Frequency Divisor */
-#define PLLMR_OPB_PLB_DIV_1 0x00000000
-#define PLLMR_OPB_PLB_DIV_2 0x00008000
-#define PLLMR_OPB_PLB_DIV_3 0x00010000
-#define PLLMR_OPB_PLB_DIV_4 0x00018000
-
-#define PLLMR_PCI_TO_PLB_MASK 0x00006000 /* PCI:PLB Frequency Divisor */
-#define PLLMR_PCI_PLB_DIV_1 0x00000000
-#define PLLMR_PCI_PLB_DIV_2 0x00002000
-#define PLLMR_PCI_PLB_DIV_3 0x00004000
-#define PLLMR_PCI_PLB_DIV_4 0x00006000
-
-#define PLLMR_EXB_TO_PLB_MASK 0x00001800 /* External Bus:PLB Divisor */
-#define PLLMR_EXB_PLB_DIV_2 0x00000000
-#define PLLMR_EXB_PLB_DIV_3 0x00000800
-#define PLLMR_EXB_PLB_DIV_4 0x00001000
-#define PLLMR_EXB_PLB_DIV_5 0x00001800
-
-/* definitions for PPC405GPr (new mode strapping) */
-#define PLLMR_FWDB_DIV_MASK 0x00000007 /* Forward Divisor B */
-
-#define PSR_PLL_FWD_MASK 0xC0000000
-#define PSR_PLL_FDBACK_MASK 0x30000000
-#define PSR_PLL_TUNING_MASK 0x0E000000
-#define PSR_PLB_CPU_MASK 0x01800000
-#define PSR_OPB_PLB_MASK 0x00600000
-#define PSR_PCI_PLB_MASK 0x00180000
-#define PSR_EB_PLB_MASK 0x00060000
-#define PSR_ROM_WIDTH_MASK 0x00018000
-#define PSR_ROM_LOC 0x00004000
-#define PSR_PCI_ASYNC_EN 0x00001000
-#define PSR_PERCLK_SYNC_MODE_EN 0x00000800 /* PPC405GPr only */
-#define PSR_PCI_ARBIT_EN 0x00000400
-#define PSR_NEW_MODE_EN 0x00000020 /* PPC405GPr only */
-
-/*
- * PLL Voltage Controlled Oscillator (VCO) definitions
- * Maximum and minimum values (in MHz) for correct PLL operation.
- */
-#define VCO_MIN 400
-#define VCO_MAX 800
-
-/******************************************************************************
- * Memory Access Layer
- ******************************************************************************/
-#define MAL_DCR_BASE 0x180
-#define malmcr (MAL_DCR_BASE+0x00) /* MAL Config reg */
-#define malesr (MAL_DCR_BASE+0x01) /* Error Status reg (Read/Clear) */
-#define malier (MAL_DCR_BASE+0x02) /* Interrupt enable reg */
-#define maldbr (MAL_DCR_BASE+0x03) /* Mal Debug reg (Read only) */
-#define maltxcasr (MAL_DCR_BASE+0x04) /* TX Channel active reg (set) */
-#define maltxcarr (MAL_DCR_BASE+0x05) /* TX Channel active reg (Reset) */
-#define maltxeobisr (MAL_DCR_BASE+0x06) /* TX End of buffer int status reg */
-#define maltxdeir (MAL_DCR_BASE+0x07) /* TX Descr. Error Int reg */
-#define malrxcasr (MAL_DCR_BASE+0x10) /* RX Channel active reg (set) */
-#define malrxcarr (MAL_DCR_BASE+0x11) /* RX Channel active reg (Reset) */
-#define malrxeobisr (MAL_DCR_BASE+0x12) /* RX End of buffer int status reg */
-#define malrxdeir (MAL_DCR_BASE+0x13) /* RX Descr. Error Int reg */
-#define maltxctp0r (MAL_DCR_BASE+0x20) /* TX 0 Channel table pointer reg */
-#define maltxctp1r (MAL_DCR_BASE+0x21) /* TX 1 Channel table pointer reg */
-#define malrxctp0r (MAL_DCR_BASE+0x40) /* RX 0 Channel table pointer reg */
-#define malrcbs0 (MAL_DCR_BASE+0x60) /* RX 0 Channel buffer size reg */
-
-/*-----------------------------------------------------------------------------
-| IIC Register Offsets
-'----------------------------------------------------------------------------*/
-#define IICMDBUF 0x00
-#define IICSDBUF 0x02
-#define IICLMADR 0x04
-#define IICHMADR 0x05
-#define IICCNTL 0x06
-#define IICMDCNTL 0x07
-#define IICSTS 0x08
-#define IICEXTSTS 0x09
-#define IICLSADR 0x0A
-#define IICHSADR 0x0B
-#define IICCLKDIV 0x0C
-#define IICINTRMSK 0x0D
-#define IICXFRCNT 0x0E
-#define IICXTCNTLSS 0x0F
-#define IICDIRECTCNTL 0x10
-
-/*-----------------------------------------------------------------------------
-| UART Register Offsets
-'----------------------------------------------------------------------------*/
-#define DATA_REG 0x00
-#define DL_LSB 0x00
-#define DL_MSB 0x01
-#define INT_ENABLE 0x01
-#define FIFO_CONTROL 0x02
-#define LINE_CONTROL 0x03
-#define MODEM_CONTROL 0x04
-#define LINE_STATUS 0x05
-#define MODEM_STATUS 0x06
-#define SCRATCH 0x07
-
-/******************************************************************************
- * On Chip Memory
- ******************************************************************************/
-#define OCM_DCR_BASE 0x018
-#define ocmisarc (OCM_DCR_BASE+0x00) /* OCM I-side address compare reg */
-#define ocmiscntl (OCM_DCR_BASE+0x01) /* OCM I-side control reg */
-#define ocmdsarc (OCM_DCR_BASE+0x02) /* OCM D-side address compare reg */
-#define ocmdscntl (OCM_DCR_BASE+0x03) /* OCM D-side control reg */
-
-
-/*
- * Macro for accessing the indirect EBC register
- */
-#define mtebc(reg, data) mtdcr(ebccfga,reg);mtdcr(ebccfgd,data)
-#define mfebc(reg, data) mtdcr(ebccfga,reg);data = mfdcr(ebccfgd)
-
-
-#ifndef __ASSEMBLY__
-
-typedef struct
-{
- unsigned long pllFwdDiv;
- unsigned long pllFwdDivB;
- unsigned long pllFbkDiv;
- unsigned long pllPlbDiv;
- unsigned long pllPciDiv;
- unsigned long pllExtBusDiv;
- unsigned long pllOpbDiv;
- unsigned long freqVCOMhz; /* in MHz */
- unsigned long freqProcessor;
- unsigned long freqPLB;
- unsigned long freqPCI;
- unsigned long pciIntArbEn; /* Internal PCI arbiter is enabled */
- unsigned long pciClkSync; /* PCI clock is synchronous */
-} PPC405_SYS_INFO;
-
-#endif /* _ASMLANGUAGE */
-
-#define RESET_VECTOR 0xfffffffc
-#define CACHELINE_MASK (CFG_CACHELINE_SIZE - 1) /* Address mask for cache
- line aligned data. */
+#if defined(CONFIG_440)
+#include <ppc440.h>
+#else
+#include <ppc405.h>
+#endif
#endif /* __PPC4XX_H__ */
unsigned long bi_vco; /* VCO Out from PLL, in MHz */
#endif
unsigned long bi_baudrate; /* Console Baudrate */
-#if defined(CONFIG_405GP) || defined(CONFIG_405CR)
+#if defined(CONFIG_405GP) || defined(CONFIG_405CR) || defined(CONFIG_440)
unsigned char bi_s_version[4]; /* Version of this structure */
unsigned char bi_r_version[32]; /* Version of the ROM (IBM) */
unsigned int bi_procfreq; /* CPU (Internal) Freq, in Hz */
ulong get_bus_freq (ulong);
#if defined(CONFIG_4xx) || defined(CONFIG_IOP480)
-void get_sys_info (PPC405_SYS_INFO *);
+# if defined(CONFIG_440)
+ typedef PPC440_SYS_INFO sys_info_t;
+# else
+ typedef PPC405_SYS_INFO sys_info_t;
+# endif
+void get_sys_info ( sys_info_t * );
#endif
/* $(CPU)/cpu_init.c */
projects / users / rw / ppcboot.git / commitdiff