perf/x86/intel: Fix event constraints for LNC

According to the latest event list, update the event constraint tables
for Lion Cove core.

The general rule (the event codes < 0x90 are restricted to counters
0-3.) has been removed. There is no restriction for most of the
performance monitoring events.

Fixes: a932aa0e868f ("perf/x86: Add Lunar Lake and Arrow Lake support")
Reported-by: Amiri Khalil <amiri.khalil@intel.com>
Signed-off-by: Kan Liang <kan.liang@linux.intel.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Cc: stable@vger.kernel.org
Link: https://lkml.kernel.org/r/20250219141005.2446823-1-kan.liang@linux.intel.com

diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c
index e86333eee2668f4a068c7eaa096ab0c18b2798f2..cdcebf30468a005fa77b0030a4d1b5aef1a54e3c 100644 (file)
--- a/arch/x86/events/intel/core.c
+++ b/arch/x86/events/intel/core.c
@@ -397,34 +397,28 @@ static struct event_constraint intel_lnc_event_constraints[] = {
        METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_FETCH_LAT, 6),
        METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_MEM_BOUND, 7),
 
+       INTEL_EVENT_CONSTRAINT(0x20, 0xf),
+
+       INTEL_UEVENT_CONSTRAINT(0x012a, 0xf),
+       INTEL_UEVENT_CONSTRAINT(0x012b, 0xf),
        INTEL_UEVENT_CONSTRAINT(0x0148, 0x4),
        INTEL_UEVENT_CONSTRAINT(0x0175, 0x4),
 
        INTEL_EVENT_CONSTRAINT(0x2e, 0x3ff),
        INTEL_EVENT_CONSTRAINT(0x3c, 0x3ff),
-       /*
-        * Generally event codes < 0x90 are restricted to counters 0-3.
-        * The 0x2E and 0x3C are exception, which has no restriction.
-        */
-       INTEL_EVENT_CONSTRAINT_RANGE(0x01, 0x8f, 0xf),
 
-       INTEL_UEVENT_CONSTRAINT(0x01a3, 0xf),
-       INTEL_UEVENT_CONSTRAINT(0x02a3, 0xf),
        INTEL_UEVENT_CONSTRAINT(0x08a3, 0x4),
        INTEL_UEVENT_CONSTRAINT(0x0ca3, 0x4),
        INTEL_UEVENT_CONSTRAINT(0x04a4, 0x1),
        INTEL_UEVENT_CONSTRAINT(0x08a4, 0x1),
        INTEL_UEVENT_CONSTRAINT(0x10a4, 0x1),
        INTEL_UEVENT_CONSTRAINT(0x01b1, 0x8),
+       INTEL_UEVENT_CONSTRAINT(0x01cd, 0x3fc),
        INTEL_UEVENT_CONSTRAINT(0x02cd, 0x3),
-       INTEL_EVENT_CONSTRAINT(0xce, 0x1),
 
        INTEL_EVENT_CONSTRAINT_RANGE(0xd0, 0xdf, 0xf),
-       /*
-        * Generally event codes >= 0x90 are likely to have no restrictions.
-        * The exception are defined as above.
-        */
-       INTEL_EVENT_CONSTRAINT_RANGE(0x90, 0xfe, 0x3ff),
+
+       INTEL_UEVENT_CONSTRAINT(0x00e0, 0xf),
 
        EVENT_CONSTRAINT_END
 };

diff --git a/arch/x86/events/intel/ds.c b/arch/x86/events/intel/ds.c
index c2e2eae7309c3370a17026af6e933780be8a4dd5..f122882ef278f834383e3a1ab7564e86d18f28ed 100644 (file)
--- a/arch/x86/events/intel/ds.c
+++ b/arch/x86/events/intel/ds.c
@@ -1199,7 +1199,7 @@ struct event_constraint intel_lnc_pebs_event_constraints[] = {
        INTEL_FLAGS_UEVENT_CONSTRAINT(0x100, 0x100000000ULL),   /* INST_RETIRED.PREC_DIST */
        INTEL_FLAGS_UEVENT_CONSTRAINT(0x0400, 0x800000000ULL),
 
-       INTEL_HYBRID_LDLAT_CONSTRAINT(0x1cd, 0x3ff),
+       INTEL_HYBRID_LDLAT_CONSTRAINT(0x1cd, 0x3fc),
        INTEL_HYBRID_STLAT_CONSTRAINT(0x2cd, 0x3),
        INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x11d0, 0xf),   /* MEM_INST_RETIRED.STLB_MISS_LOADS */
        INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x12d0, 0xf),   /* MEM_INST_RETIRED.STLB_MISS_STORES */