drm/i915: set up PIPECONF explicitly on ilk-ivb

Dragging random garbage along from the BIOS isn't a good idea, since
we really only support exactly what we've set up.

In the specific case for the bug reporter the BIOS used the 10bit
gamma table, but since we only support an 8bit table the dark colors
ended up all wrong and the light ones all unadjusted.

Note that this has a nice implication for fastboot, it essentially
means that we have quite a bit more state to check and compare before
we can decide whether fastboot is possible.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=65593
Reported-and-Tested-by: Thomas Hebb <tommyhebb@gmail.com>
Cc: stable@vger.kernel.org
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 015614fb04d91236d3c177aec786b968e4e66aa3..3097fb164fd8d29f1e2782c22e921c018105da51 100644 (file)
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -5342,9 +5342,8 @@ static void ironlake_set_pipeconf(struct drm_crtc *crtc)
        int pipe = intel_crtc->pipe;
        uint32_t val;
 
-       val = I915_READ(PIPECONF(pipe));
+       val = 0;
 
-       val &= ~PIPECONF_BPC_MASK;
        switch (intel_crtc->config.pipe_bpp) {
        case 18:
                val |= PIPECONF_6BPC;
@@ -5363,11 +5362,9 @@ static void ironlake_set_pipeconf(struct drm_crtc *crtc)
                BUG();
        }
 
-       val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
        if (intel_crtc->config.dither)
                val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
 
-       val &= ~PIPECONF_INTERLACE_MASK;
        if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
                val |= PIPECONF_INTERLACED_ILK;
        else
@@ -5375,8 +5372,6 @@ static void ironlake_set_pipeconf(struct drm_crtc *crtc)
 
        if (intel_crtc->config.limited_color_range)
                val |= PIPECONF_COLOR_RANGE_SELECT;
-       else
-               val &= ~PIPECONF_COLOR_RANGE_SELECT;
 
        I915_WRITE(PIPECONF(pipe), val);
        POSTING_READ(PIPECONF(pipe));