union {
                                __le32 rss; /* RSS Hash */
                                __le32 fcoe_param; /* FCoE DDP Context id */
+                               /* Flow director filter id in case of
+                                * Programming status desc WB
+                                */
+                               __le32 fd_id;
                        } hi_dword;
                } qword0;
                struct {
 enum i40e_rx_prog_status_desc_error_bits {
        /* Note: These are predefined bit offsets */
        I40E_RX_PROG_STATUS_DESC_FD_TBL_FULL_SHIFT      = 0,
-       I40E_RX_PROG_STATUS_DESC_NO_FD_QUOTA_SHIFT      = 1,
+       I40E_RX_PROG_STATUS_DESC_NO_FD_ENTRY_SHIFT      = 1,
        I40E_RX_PROG_STATUS_DESC_FCOE_TBL_FULL_SHIFT    = 2,
        I40E_RX_PROG_STATUS_DESC_FCOE_CONFLICT_SHIFT    = 3
 };
 
                        union {
                                __le32 rss; /* RSS Hash */
                                __le32 fcoe_param; /* FCoE DDP Context id */
+                               /* Flow director filter id in case of
+                                * Programming status desc WB
+                                */
+                               __le32 fd_id;
                        } hi_dword;
                } qword0;
                struct {
 enum i40e_rx_prog_status_desc_error_bits {
        /* Note: These are predefined bit offsets */
        I40E_RX_PROG_STATUS_DESC_FD_TBL_FULL_SHIFT      = 0,
-       I40E_RX_PROG_STATUS_DESC_NO_FD_QUOTA_SHIFT      = 1,
+       I40E_RX_PROG_STATUS_DESC_NO_FD_ENTRY_SHIFT      = 1,
        I40E_RX_PROG_STATUS_DESC_FCOE_TBL_FULL_SHIFT    = 2,
        I40E_RX_PROG_STATUS_DESC_FCOE_CONFLICT_SHIFT    = 3
 };