iommu/tegra: gart: Fix register offset correctly

DT passes the exact GART register ranges without any overlapping with
MC register ranges. GART register offset needs to be adjusted by one
passed by DT correctly.

Signed-off-by: Hiroshi DOYU <hdoyu@nvidia.com>
Acked-by: Stephen Warren <swarren@wwwdotorg.org>
Signed-off-by: Joerg Roedel <joerg.roedel@amd.com>

diff --git a/Documentation/devicetree/bindings/iommu/nvidia,tegra20-gart.txt b/Documentation/devicetree/bindings/iommu/nvidia,tegra20-gart.txt
index 2d87b9191fce1a2a3764368bf90936f8fdd1ac0a..099d9362ebc106442a47be8f59f2f1d3f88fa161 100644 (file)
--- a/Documentation/devicetree/bindings/iommu/nvidia,tegra20-gart.txt
+++ b/Documentation/devicetree/bindings/iommu/nvidia,tegra20-gart.txt
@@ -7,8 +7,8 @@ Required properties:
 
 Example:
 
-       gart: gart@7000f000 {
+       gart {
                compatible = "nvidia,tegra20-gart";
-               reg = < 0x7000f000 0x00000100    /* controller registers */
-                       0x58000000 0x02000000 >; /* GART aperture */
+               reg = <0x7000f024 0x00000018    /* controller registers */
+                      0x58000000 0x02000000>;  /* GART aperture */
        };

diff --git a/drivers/iommu/tegra-gart.c b/drivers/iommu/tegra-gart.c
index 40533bba62547961051933d01471c8036f8d94ed..0c0a37792218452fb9d48f7b84364604564669b0 100644 (file)
--- a/drivers/iommu/tegra-gart.c
+++ b/drivers/iommu/tegra-gart.c
@@ -36,9 +36,10 @@
 /* bitmap of the page sizes currently supported */
 #define GART_IOMMU_PGSIZES     (SZ_4K)
 
-#define GART_CONFIG            0x24
-#define GART_ENTRY_ADDR                0x28
-#define GART_ENTRY_DATA                0x2c
+#define GART_REG_BASE          0x24
+#define GART_CONFIG            (0x24 - GART_REG_BASE)
+#define GART_ENTRY_ADDR                (0x28 - GART_REG_BASE)
+#define GART_ENTRY_DATA                (0x2c - GART_REG_BASE)
 #define GART_ENTRY_PHYS_ADDR_VALID     (1 << 31)
 
 #define GART_PAGE_SHIFT                12