drm/bridge: samsung-dsim: add driver support for exynos7870 DSIM bridge

Add support for Exynos7870's DSIM IP block in the bridge driver.

Signed-off-by: Kaustabh Chakraborty <kauschluss@disroot.org>
Signed-off-by: Inki Dae <inki.dae@samsung.com>

diff --git a/drivers/gpu/drm/bridge/samsung-dsim.c b/drivers/gpu/drm/bridge/samsung-dsim.c
index 802164e6adfffd9b939aa07e0f53a9eb09fdd0ed..eabc4c32f6ab4a0ebb753136ca490229f3dfbd91 100644 (file)
--- a/drivers/gpu/drm/bridge/samsung-dsim.c
+++ b/drivers/gpu/drm/bridge/samsung-dsim.c
@@ -244,6 +244,13 @@ static struct clk_bulk_data exynos5433_clk_bulk_data[] = {
        { .id = "sclk_rgb_vclk_to_dsim0" },
 };
 
+static struct clk_bulk_data exynos7870_clk_bulk_data[] = {
+       { .id = "bus" },
+       { .id = "pll" },
+       { .id = "byte" },
+       { .id = "esc" },
+};
+
 enum reg_idx {
        DSIM_STATUS_REG,        /* Status register (legacy) */
        DSIM_LINK_STATUS_REG,   /* Link status register */
@@ -320,6 +327,32 @@ static const unsigned int exynos5433_reg_ofs[] = {
        [DSIM_PHYTIMING2_REG] = 0xBC,
 };
 
+static const unsigned int exynos7870_reg_ofs[] = {
+       [DSIM_LINK_STATUS_REG] = 0x04,
+       [DSIM_DPHY_STATUS_REG] = 0x08,
+       [DSIM_SWRST_REG] = 0x0C,
+       [DSIM_CLKCTRL_REG] = 0x10,
+       [DSIM_TIMEOUT_REG] = 0x14,
+       [DSIM_ESCMODE_REG] = 0x1C,
+       [DSIM_MDRESOL_REG] = 0x20,
+       [DSIM_MVPORCH_REG] = 0x24,
+       [DSIM_MHPORCH_REG] = 0x28,
+       [DSIM_MSYNC_REG] = 0x2C,
+       [DSIM_CONFIG_REG] = 0x30,
+       [DSIM_INTSRC_REG] = 0x34,
+       [DSIM_INTMSK_REG] = 0x38,
+       [DSIM_PKTHDR_REG] = 0x3C,
+       [DSIM_PAYLOAD_REG] = 0x40,
+       [DSIM_RXFIFO_REG] = 0x44,
+       [DSIM_SFRCTRL_REG] = 0x48,
+       [DSIM_FIFOCTRL_REG] = 0x4C,
+       [DSIM_PLLCTRL_REG] = 0x94,
+       [DSIM_PHYCTRL_REG] = 0xA4,
+       [DSIM_PHYTIMING_REG] = 0xB4,
+       [DSIM_PHYTIMING1_REG] = 0xB8,
+       [DSIM_PHYTIMING2_REG] = 0xBC,
+};
+
 enum reg_value_idx {
        RESET_TYPE,
        PLL_TIMER,
@@ -392,6 +425,24 @@ static const unsigned int exynos5433_reg_values[] = {
        [PHYTIMING_HS_TRAIL] = DSIM_PHYTIMING2_HS_TRAIL(0x0c),
 };
 
+static const unsigned int exynos7870_reg_values[] = {
+       [RESET_TYPE] = DSIM_SWRST,
+       [PLL_TIMER] = 80000,
+       [STOP_STATE_CNT] = 0xa,
+       [PHYCTRL_ULPS_EXIT] = DSIM_PHYCTRL_ULPS_EXIT(0x177),
+       [PHYCTRL_VREG_LP] = 0,
+       [PHYCTRL_SLEW_UP] = 0,
+       [PHYTIMING_LPX] = DSIM_PHYTIMING_LPX(0x07),
+       [PHYTIMING_HS_EXIT] = DSIM_PHYTIMING_HS_EXIT(0x0c),
+       [PHYTIMING_CLK_PREPARE] = DSIM_PHYTIMING1_CLK_PREPARE(0x08),
+       [PHYTIMING_CLK_ZERO] = DSIM_PHYTIMING1_CLK_ZERO(0x2b),
+       [PHYTIMING_CLK_POST] = DSIM_PHYTIMING1_CLK_POST(0x0d),
+       [PHYTIMING_CLK_TRAIL] = DSIM_PHYTIMING1_CLK_TRAIL(0x09),
+       [PHYTIMING_HS_PREPARE] = DSIM_PHYTIMING2_HS_PREPARE(0x09),
+       [PHYTIMING_HS_ZERO] = DSIM_PHYTIMING2_HS_ZERO(0x0f),
+       [PHYTIMING_HS_TRAIL] = DSIM_PHYTIMING2_HS_TRAIL(0x0c),
+};
+
 static const unsigned int imx8mm_dsim_reg_values[] = {
        [RESET_TYPE] = DSIM_SWRST,
        [PLL_TIMER] = 500,
@@ -563,6 +614,36 @@ static const struct samsung_dsim_driver_data exynos5422_dsi_driver_data = {
        .min_freq = 500,
 };
 
+static const struct samsung_dsim_driver_data exynos7870_dsi_driver_data = {
+       .reg_ofs = exynos7870_reg_ofs,
+       .plltmr_reg = 0xa0,
+       .has_clklane_stop = 1,
+       .has_sfrctrl = 1,
+       .clk_data = exynos7870_clk_bulk_data,
+       .num_clks = ARRAY_SIZE(exynos7870_clk_bulk_data),
+       .max_freq = 1500,
+       .wait_for_hdr_fifo = 0,
+       .wait_for_reset = 1,
+       .num_bits_resol = 12,
+       .video_mode_bit = 18,
+       .pll_stable_bit = 24,
+       .esc_clken_bit = 16,
+       .byte_clken_bit = 17,
+       .tx_req_hsclk_bit = 20,
+       .lane_esc_clk_bit = 8,
+       .lane_esc_data_offset = 9,
+       .pll_p_offset = 13,
+       .pll_m_offset = 3,
+       .pll_s_offset = 0,
+       .main_vsa_offset = 16,
+       .reg_values = exynos7870_reg_values,
+       .pll_fin_min = 6,
+       .pll_fin_max = 12,
+       .m_min = 41,
+       .m_max = 125,
+       .min_freq = 500,
+};
+
 static const struct samsung_dsim_driver_data imx8mm_dsi_driver_data = {
        .reg_ofs = exynos5433_reg_ofs,
        .plltmr_reg = 0xa0,
@@ -604,6 +685,7 @@ samsung_dsim_types[DSIM_TYPE_COUNT] = {
        [DSIM_TYPE_EXYNOS5410] = &exynos5_dsi_driver_data,
        [DSIM_TYPE_EXYNOS5422] = &exynos5422_dsi_driver_data,
        [DSIM_TYPE_EXYNOS5433] = &exynos5433_dsi_driver_data,
+       [DSIM_TYPE_EXYNOS7870] = &exynos7870_dsi_driver_data,
        [DSIM_TYPE_IMX8MM] = &imx8mm_dsi_driver_data,
        [DSIM_TYPE_IMX8MP] = &imx8mm_dsi_driver_data,
 };

diff --git a/include/drm/bridge/samsung-dsim.h b/include/drm/bridge/samsung-dsim.h
index eb9fdbab1b34074923daa0aa0443c33c5b99ae42..31d7ed589233ce560767afa1877f4cc885bf41f3 100644 (file)
--- a/include/drm/bridge/samsung-dsim.h
+++ b/include/drm/bridge/samsung-dsim.h
@@ -29,6 +29,7 @@ enum samsung_dsim_type {
        DSIM_TYPE_EXYNOS5410,
        DSIM_TYPE_EXYNOS5422,
        DSIM_TYPE_EXYNOS5433,
+       DSIM_TYPE_EXYNOS7870,
        DSIM_TYPE_IMX8MM,
        DSIM_TYPE_IMX8MP,
        DSIM_TYPE_COUNT,