drm/amdgpu/cik: move uvd tiling config setup into uvd code

Split uvd and gfx programming.

Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
index 08c276c2080d951744e4c7949810e17b7f5ba84e..250bcbce7fdc04dd52315b16f03ede53b6ba361b 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
@@ -31,8 +31,6 @@
 #include "amdgpu_ucode.h"
 #include "clearstate_ci.h"
 
-#include "uvd/uvd_4_2_d.h"
-
 #include "dce/dce_8_0_d.h"
 #include "dce/dce_8_0_sh_mask.h"
 
@@ -1721,9 +1719,6 @@ static void gfx_v7_0_gpu_init(struct amdgpu_device *adev)
        WREG32(mmGB_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
        WREG32(mmHDP_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
        WREG32(mmDMIF_ADDR_CALC, adev->gfx.config.gb_addr_config);
-       WREG32(mmUVD_UDEC_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
-       WREG32(mmUVD_UDEC_DB_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
-       WREG32(mmUVD_UDEC_DBW_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
 
        gfx_v7_0_tiling_mode_table_init(adev);
 
@@ -4600,12 +4595,6 @@ static void gfx_v7_0_print_status(void *handle)
                 RREG32(mmHDP_ADDR_CONFIG));
        dev_info(adev->dev, "  DMIF_ADDR_CALC=0x%08X\n",
                 RREG32(mmDMIF_ADDR_CALC));
-       dev_info(adev->dev, "  UVD_UDEC_ADDR_CONFIG=0x%08X\n",
-                RREG32(mmUVD_UDEC_ADDR_CONFIG));
-       dev_info(adev->dev, "  UVD_UDEC_DB_ADDR_CONFIG=0x%08X\n",
-                RREG32(mmUVD_UDEC_DB_ADDR_CONFIG));
-       dev_info(adev->dev, "  UVD_UDEC_DBW_ADDR_CONFIG=0x%08X\n",
-                RREG32(mmUVD_UDEC_DBW_ADDR_CONFIG));
 
        dev_info(adev->dev, "  CP_MEQ_THRESHOLDS=0x%08X\n",
                 RREG32(mmCP_MEQ_THRESHOLDS));

diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c b/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c
index 232fe2a3a9b8a297dc00c6f9e919e5cb80e99892..70ed73fa51561dea8401ebbb4370c614d4f48683 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c
+++ b/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c
@@ -576,6 +576,10 @@ static void uvd_v4_2_mc_resume(struct amdgpu_device *adev)
        addr = (adev->uvd.gpu_addr >> 32) & 0xFF;
        WREG32(mmUVD_LMI_EXT40_ADDR, addr | (0x9 << 16) | (0x1 << 31));
 
+       WREG32(mmUVD_UDEC_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
+       WREG32(mmUVD_UDEC_DB_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
+       WREG32(mmUVD_UDEC_DBW_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
+
        uvd_v4_2_init_cg(adev);
 }
 
@@ -777,6 +781,13 @@ static void uvd_v4_2_print_status(void *handle)
                 RREG32(mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL));
        dev_info(adev->dev, "  UVD_CONTEXT_ID=0x%08X\n",
                 RREG32(mmUVD_CONTEXT_ID));
+       dev_info(adev->dev, "  UVD_UDEC_ADDR_CONFIG=0x%08X\n",
+                RREG32(mmUVD_UDEC_ADDR_CONFIG));
+       dev_info(adev->dev, "  UVD_UDEC_DB_ADDR_CONFIG=0x%08X\n",
+                RREG32(mmUVD_UDEC_DB_ADDR_CONFIG));
+       dev_info(adev->dev, "  UVD_UDEC_DBW_ADDR_CONFIG=0x%08X\n",
+                RREG32(mmUVD_UDEC_DBW_ADDR_CONFIG));
+
 }
 
 static int uvd_v4_2_set_interrupt_state(struct amdgpu_device *adev,