void (*set_virtual_x2apic_mode)(struct kvm_vcpu *vcpu, bool set);
        void (*set_apic_access_page_addr)(struct kvm_vcpu *vcpu, hpa_t hpa);
        void (*deliver_posted_interrupt)(struct kvm_vcpu *vcpu, int vector);
-       void (*sync_pir_to_irr)(struct kvm_vcpu *vcpu);
+       int (*sync_pir_to_irr)(struct kvm_vcpu *vcpu);
        int (*set_tss_addr)(struct kvm *kvm, unsigned int addr);
        int (*get_tdp_level)(void);
        u64 (*get_mt_mask)(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio);
 
         */
        return apic_find_highest_irr(vcpu->arch.apic);
 }
+EXPORT_SYMBOL_GPL(kvm_lapic_find_highest_irr);
 
 static int __apic_accept_irq(struct kvm_lapic *apic, int delivery_mode,
                             int vector, int level, int trig_mode,
 static int apic_has_interrupt_for_ppr(struct kvm_lapic *apic, u32 ppr)
 {
        int highest_irr;
-       if (apic->vcpu->arch.apicv_active)
-               kvm_x86_ops->sync_pir_to_irr(apic->vcpu);
-       highest_irr = apic_find_highest_irr(apic);
+       if (kvm_x86_ops->sync_pir_to_irr && apic->vcpu->arch.apicv_active)
+               highest_irr = kvm_x86_ops->sync_pir_to_irr(apic->vcpu);
+       else
+               highest_irr = apic_find_highest_irr(apic);
        if (highest_irr == -1 || (highest_irr & 0xF0) <= ppr)
                return -1;
        return highest_irr;
 
        return;
 }
 
-static void svm_sync_pir_to_irr(struct kvm_vcpu *vcpu)
-{
-       return;
-}
-
 static void svm_deliver_avic_intr(struct kvm_vcpu *vcpu, int vec)
 {
        kvm_lapic_set_irr(vec, vcpu->arch.apic);
        .get_enable_apicv = svm_get_enable_apicv,
        .refresh_apicv_exec_ctrl = svm_refresh_apicv_exec_ctrl,
        .load_eoi_exitmap = svm_load_eoi_exitmap,
-       .sync_pir_to_irr = svm_sync_pir_to_irr,
        .hwapic_irr_update = svm_hwapic_irr_update,
        .hwapic_isr_update = svm_hwapic_isr_update,
        .apicv_post_state_restore = avic_post_state_restore,
 
        if (!cpu_has_vmx_ple())
                ple_gap = 0;
 
-       if (!cpu_has_vmx_apicv())
+       if (!cpu_has_vmx_apicv()) {
                enable_apicv = 0;
+               kvm_x86_ops->sync_pir_to_irr = NULL;
+       }
 
        if (cpu_has_vmx_tsc_scaling()) {
                kvm_has_tsc_control = true;
        }
 }
 
-static void vmx_sync_pir_to_irr(struct kvm_vcpu *vcpu)
+static int vmx_sync_pir_to_irr(struct kvm_vcpu *vcpu)
 {
        struct vcpu_vmx *vmx = to_vmx(vcpu);
+       int max_irr;
 
-       if (!pi_test_on(&vmx->pi_desc))
-               return;
-
-       pi_clear_on(&vmx->pi_desc);
-       /*
-        * IOMMU can write to PIR.ON, so the barrier matters even on UP.
-        * But on x86 this is just a compiler barrier anyway.
-        */
-       smp_mb__after_atomic();
-       kvm_apic_update_irr(vcpu, vmx->pi_desc.pir);
+       WARN_ON(!vcpu->arch.apicv_active);
+       if (pi_test_on(&vmx->pi_desc)) {
+               pi_clear_on(&vmx->pi_desc);
+               /*
+                * IOMMU can write to PIR.ON, so the barrier matters even on UP.
+                * But on x86 this is just a compiler barrier anyway.
+                */
+               smp_mb__after_atomic();
+               max_irr = kvm_apic_update_irr(vcpu, vmx->pi_desc.pir);
+       } else {
+               max_irr = kvm_lapic_find_highest_irr(vcpu);
+       }
+       vmx_hwapic_irr_update(vcpu, max_irr);
+       return max_irr;
 }
 
 static void vmx_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap)
 
 static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
                                    struct kvm_lapic_state *s)
 {
-       if (vcpu->arch.apicv_active)
+       if (kvm_x86_ops->sync_pir_to_irr && vcpu->arch.apicv_active)
                kvm_x86_ops->sync_pir_to_irr(vcpu);
 
        return kvm_apic_get_state(vcpu, s);
        if (irqchip_split(vcpu->kvm))
                kvm_scan_ioapic_routes(vcpu, vcpu->arch.ioapic_handled_vectors);
        else {
-               if (vcpu->arch.apicv_active)
+               if (kvm_x86_ops->sync_pir_to_irr && vcpu->arch.apicv_active)
                        kvm_x86_ops->sync_pir_to_irr(vcpu);
                kvm_ioapic_scan_entry(vcpu, vcpu->arch.ioapic_handled_vectors);
        }
                 * Update architecture specific hints for APIC
                 * virtual interrupt delivery.
                 */
-               if (vcpu->arch.apicv_active) {
+               if (kvm_x86_ops->sync_pir_to_irr && vcpu->arch.apicv_active)
                        kvm_x86_ops->sync_pir_to_irr(vcpu);
-                       kvm_x86_ops->hwapic_irr_update(vcpu,
-                               kvm_lapic_find_highest_irr(vcpu));
-               }
        }
 
        if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {