dt-bindings: clock: exynos850: Add CMU_CPUCLK0 and CMU_CPUCL1

Document CPU clock management unit compatibles and add corresponding
clock indices. Exynos850 has two CPU clusters (CL0 and CL1), each
containing 4 Cortex-A55 cores. CPU PLLs are generating main CPU clocks
for each cluster, and there are alternate ("switch") clocks that can be
used temporarily while re-configuring the PLL for the new rate. ACLK,
ATCLK, PCLKDBG and PERIPHCLK clocks are driving corresponding buses.
CLK_CLUSTERx_SCLK are actual leaf CPU clocks and should be used to
change CPU rates. Also some CoreSight clocks can be derived from
DBG_USER (debug clock).

Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
Link: https://lore.kernel.org/r/20240224202053.25313-2-semen.protsenko@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

diff --git a/Documentation/devicetree/bindings/clock/samsung,exynos850-clock.yaml b/Documentation/devicetree/bindings/clock/samsung,exynos850-clock.yaml
index c752c8985a536e9868492223746170300aa5c8ad..cdc5ded59fe5e0b18e4a80387de4e7318f3d6fc2 100644 (file)
--- a/Documentation/devicetree/bindings/clock/samsung,exynos850-clock.yaml
+++ b/Documentation/devicetree/bindings/clock/samsung,exynos850-clock.yaml
@@ -36,6 +36,8 @@ properties:
       - samsung,exynos850-cmu-aud
       - samsung,exynos850-cmu-cmgp
       - samsung,exynos850-cmu-core
+      - samsung,exynos850-cmu-cpucl0
+      - samsung,exynos850-cmu-cpucl1
       - samsung,exynos850-cmu-dpu
       - samsung,exynos850-cmu-g3d
       - samsung,exynos850-cmu-hsi
@@ -152,6 +154,46 @@ allOf:
             - const: dout_core_mmc_embd
             - const: dout_core_sss
 
+  - if:
+      properties:
+        compatible:
+          contains:
+            const: samsung,exynos850-cmu-cpucl0
+
+    then:
+      properties:
+        clocks:
+          items:
+            - description: External reference clock (26 MHz)
+            - description: CPUCL0 switch clock (from CMU_TOP)
+            - description: CPUCL0 debug clock (from CMU_TOP)
+
+        clock-names:
+          items:
+            - const: oscclk
+            - const: dout_cpucl0_switch
+            - const: dout_cpucl0_dbg
+
+  - if:
+      properties:
+        compatible:
+          contains:
+            const: samsung,exynos850-cmu-cpucl1
+
+    then:
+      properties:
+        clocks:
+          items:
+            - description: External reference clock (26 MHz)
+            - description: CPUCL1 switch clock (from CMU_TOP)
+            - description: CPUCL1 debug clock (from CMU_TOP)
+
+        clock-names:
+          items:
+            - const: oscclk
+            - const: dout_cpucl1_switch
+            - const: dout_cpucl1_dbg
+
   - if:
       properties:
         compatible:

diff --git a/include/dt-bindings/clock/exynos850.h b/include/dt-bindings/clock/exynos850.h
index bc15108aa3c2ab527c25d688c66121208b35eac9..7666241520f8761bf31ced7374a75f04913fd8cd 100644 (file)
--- a/include/dt-bindings/clock/exynos850.h
+++ b/include/dt-bindings/clock/exynos850.h
@@ -88,6 +88,18 @@
 #define CLK_MOUT_G3D_SWITCH            76
 #define CLK_GOUT_G3D_SWITCH            77
 #define CLK_DOUT_G3D_SWITCH            78
+#define CLK_MOUT_CPUCL0_DBG            79
+#define CLK_MOUT_CPUCL0_SWITCH         80
+#define CLK_GOUT_CPUCL0_DBG            81
+#define CLK_GOUT_CPUCL0_SWITCH         82
+#define CLK_DOUT_CPUCL0_DBG            83
+#define CLK_DOUT_CPUCL0_SWITCH         84
+#define CLK_MOUT_CPUCL1_DBG            85
+#define CLK_MOUT_CPUCL1_SWITCH         86
+#define CLK_GOUT_CPUCL1_DBG            87
+#define CLK_GOUT_CPUCL1_SWITCH         88
+#define CLK_DOUT_CPUCL1_DBG            89
+#define CLK_DOUT_CPUCL1_SWITCH         90
 
 /* CMU_APM */
 #define CLK_RCO_I3C_PMIC               1
@@ -195,6 +207,48 @@
 #define CLK_GOUT_CMGP_USI1_PCLK                14
 #define CLK_GOUT_SYSREG_CMGP_PCLK      15
 
+/* CMU_CPUCL0 */
+#define CLK_FOUT_CPUCL0_PLL            1
+#define CLK_MOUT_PLL_CPUCL0            2
+#define CLK_MOUT_CPUCL0_SWITCH_USER    3
+#define CLK_MOUT_CPUCL0_DBG_USER       4
+#define CLK_MOUT_CPUCL0_PLL            5
+#define CLK_DOUT_CPUCL0_CPU            6
+#define CLK_DOUT_CPUCL0_CMUREF         7
+#define CLK_DOUT_CPUCL0_PCLK           8
+#define CLK_DOUT_CLUSTER0_ACLK         9
+#define CLK_DOUT_CLUSTER0_ATCLK                10
+#define CLK_DOUT_CLUSTER0_PCLKDBG      11
+#define CLK_DOUT_CLUSTER0_PERIPHCLK    12
+#define CLK_GOUT_CLUSTER0_ATCLK                13
+#define CLK_GOUT_CLUSTER0_PCLK         14
+#define CLK_GOUT_CLUSTER0_PERIPHCLK    15
+#define CLK_GOUT_CLUSTER0_SCLK         16
+#define CLK_GOUT_CPUCL0_CMU_CPUCL0_PCLK        17
+#define CLK_GOUT_CLUSTER0_CPU          18
+#define CLK_CLUSTER0_SCLK              19
+
+/* CMU_CPUCL1 */
+#define CLK_FOUT_CPUCL1_PLL            1
+#define CLK_MOUT_PLL_CPUCL1            2
+#define CLK_MOUT_CPUCL1_SWITCH_USER    3
+#define CLK_MOUT_CPUCL1_DBG_USER       4
+#define CLK_MOUT_CPUCL1_PLL            5
+#define CLK_DOUT_CPUCL1_CPU            6
+#define CLK_DOUT_CPUCL1_CMUREF         7
+#define CLK_DOUT_CPUCL1_PCLK           8
+#define CLK_DOUT_CLUSTER1_ACLK         9
+#define CLK_DOUT_CLUSTER1_ATCLK                10
+#define CLK_DOUT_CLUSTER1_PCLKDBG      11
+#define CLK_DOUT_CLUSTER1_PERIPHCLK    12
+#define CLK_GOUT_CLUSTER1_ATCLK                13
+#define CLK_GOUT_CLUSTER1_PCLK         14
+#define CLK_GOUT_CLUSTER1_PERIPHCLK    15
+#define CLK_GOUT_CLUSTER1_SCLK         16
+#define CLK_GOUT_CPUCL1_CMU_CPUCL1_PCLK        17
+#define CLK_GOUT_CLUSTER1_CPU          18
+#define CLK_CLUSTER1_SCLK              19
+
 /* CMU_G3D */
 #define CLK_FOUT_G3D_PLL               1
 #define CLK_MOUT_G3D_PLL               2