Fix Exception handling for "Software Emulation Exception" etc.
======================================================================
-Modifications since 0.5.0:
+Modifications for 0.5.1:
======================================================================
+* Made many commands configurable to save memory on production
+ systems or to disable features (like network support) on hardware
+ which cannot support it
+
+* Added support for SPD823TS board.
+
+* Added CPM reset during CPU startup.
+
+* Update IMMR structure for MPC823; fix SCCR_DFLCDxxx definitions and
+ add MAMR_AMB_* definitions to mpc8xx.h
+
+* Allow default configuration of CPM interrupt level and GCLK
+ frequency
+
+* Allow default configuration of environment variables "ethaddr",
+ "ipaddr" and "serverip"
+
+* Fix udelay() for different EXTCLK / OSCLK combinations
+
+* Added memory compare command
+
+* Changes of the ethernet address and/or IP address in the
+ environment are copied to the board info structure for later use by
+ the network code and/or any other program
+
* Added multi-file images to allow to boot a combined kernel+initrd
file using BOOTP; see include/image.h for details.
# load other configuration
include $(TOPDIR)/config.mk
-
SUBDIRS = $(ARCH) $(CPU) $(BOARD) common net examples tools
#########################################################################
all: ppcboot.srec
install: all
- #cp ppcboot.srec /tftpboot/moni.srec
- cp ppcboot.srec /net/gatekeeper/tftpboot/moni.srec
+ #cp ppcboot.srec /tftpboot/moni.srec
+ cp ppcboot.srec /net/gatekeeper/tftpboot/moni.srec
ppcboot.srec: ppcboot
- $(OBJCOPY) ${OBJCFLAGS} -O srec $< $@
+ $(OBJCOPY) ${OBJCFLAGS} -O srec $< $@
ppcboot.bin: ppcboot
- $(OBJCOPY) ${OBJCFLAGS} -O binary $< $@
+ $(OBJCOPY) ${OBJCFLAGS} -O binary $< $@
ppcboot: depend $(SUBDIRS) $(OBJS) $(LDSCRIPT)
- $(LD) $(LDFLAGS) $(OBJS) -Map ppcboot.map -o ppcboot
+ $(LD) $(LDFLAGS) $(OBJS) -Map ppcboot.map -o ppcboot
$(SUBDIRS): dummy
- @for dir in $(SUBDIRS) ; do $(MAKE) -C $$dir || exit 1 ; done
+ @for dir in $(SUBDIRS) ; do $(MAKE) -C $$dir || exit 1 ; done
dummy:
depend dep:
- @for dir in $(SUBDIRS) ; do $(MAKE) -C $$dir .depend ; done
+ @for dir in $(SUBDIRS) ; do $(MAKE) -C $$dir .depend ; done
#########################################################################
else
echo "CPU = mpc8xx" >>config.mk ; \
echo "#include <config_$(@:_config=).h>" >config.h
+SPD823TS_config: unconfig
+ @echo "Configuring for $(@:_config=) Board..." ; \
+ cd include ; \
+ echo "ARCH = ppc" > config.mk ; \
+ echo "BOARD = spd8xx" >>config.mk ; \
+ echo "CPU = mpc8xx" >>config.mk ; \
+ echo "#include <config_$(@:_config=).h>" >config.h
+
FADS850SAR_config \
FADS860T_config: unconfig
@echo "Configuring for $(@:_config=) Board..." ; \
- mpc8xx Files specific to Motorola MPC8xx CPUs
- ppc4xx Files specific to IBM 4xx CPUs
-- adciop Files specific to ADCIOP boards
-- cpci405 Files specific to CPCI405 boards
-- tqm8xx Files specific to TQM8xxL boards
-- etx094 Files specific to ETX_094 boards
-- cogent Files specific to Cogent boards
+- adciop Files specific to ADCIOP boards
+- cpci405 Files specific to CPCI405 boards
+- tqm8xx Files specific to TQM8xxL boards
+- etx094 Files specific to ETX_094 boards
+- spd8xx Files specific to SPD8xxTS boards
+- cogent Files specific to Cogent boards
(need further configuration)
- fads Files specific to Motorola FADS boards
- Board Type: Define exactly one of
CONFIG_TQM823L, CONFIG_TQM850L, CONFIG_TQM855L,
CONFIG_TQM860L, CONFIG_ETX094, CONFIG_ADCIOP,
- CONFIG_CPCI405, CONFIG_COGENT, CONFIG_FADS
+ CONFIG_CPCI405, CONFIG_COGENT, CONFIG_FADS,
+ CONFIG_SPD823TS
--- FIXME --- not tested yet:
CONFIG_TQM860, CONFIG_FPS850L, CONFIG_MBX,
CONFIG_ADS, CONFIG_RPXLITE,
- Binary File Download (Kermit mode):
CONFIG_LOADB
- If defined, the "loadb" command will be added which
- allows to download binary files over the serial line
- using Kermit protocol.
+ If defined, the "loadb" command will be added which
+ allows to download binary files over the serial line
+ using Kermit protocol.
+
+- Monitor Functions:
+ CONFIG_COMMANDS
+ Most monitor functions can be selected (or
+ de-selected) by adjusting the definition of
+ CONFIG_COMMANDS; to select individual functions,
+ #define CONFIG_COMMANDS by "OR"ing any of the
+ following values:
+
+ #define enables commands:
+ -------------------------
+ CFG_CMD_BDI bdinfo
+ CFG_CMD_LOADS loads
+ CFG_CMD_LOADB loadb
+ CFG_CMD_IMI iminfo
+ CFG_CMD_CACHE icache, dcache
+ CFG_CMD_FLASH flinfo, erase, protect
+ CFG_CMD_MEMORY md, mm, nm, mw, cp, cmp, crc, base, loop, mtest
+ CFG_CMD_NET bootp, tftpboot, rarpboot
+ CFG_CMD_ENV saveenv
+ -------------------------
+ CFG_CMD_ALL all
+
+ If you don't define CONFIG_COMMANDS it defaults to CFG_CMD_ALL .
+
+ EXAMPLE: If you want all functions except of network support you
+ can write:
+
+ #define CONFIG_COMMANDS (CFG_CMD_ALL & ~CFG_CMD_NET)
+
+
Configuration Settings:
-----------------------
CPCI405_config
ADCIOP_config
FADS850SAR_config
+ SPD823TS_config
If the system board that you have is not listed, then you will need
static char *failed = "*** failed ***\n";
+ulong cpu_speed; /* VCOOUT = CPU clock in Hz! */
+
/*
* Begin and End of memory area for malloc(), and current "brk"
*/
board_init_f (ulong bootflag)
{
bd_t *bd;
- ulong reg, len;
+ ulong reg, len, clock_mhz;
int board_type;
ulong addr_moni, addr_sp;
- ulong dram_size, cpu_speed;
+ ulong dram_size;
char *s, *e;
int baudrate;
/* CPU Clock Speed */
- cpu_speed = get_gclk_freq () / 1000 / 1000; /* in MHz */
+ cpu_speed = get_gclk_freq (); /* in Hz */
+ clock_mhz = cpu_speed / 1000 / 1000; /* in MHz */
s = getenv ("baudrate");
baudrate = s ? (int)simple_strtoul(s, NULL, 10) : CONFIG_BAUDRATE;
/* set up serial port */
- serial_init (cpu_speed, baudrate);
+ serial_init (clock_mhz, baudrate);
display_options();
printf ("Initializing...\n CPU: "); /* Check CPU */
- if (checkcpu(cpu_speed) < 0) {
+ if (checkcpu(clock_mhz) < 0) {
printf (failed);
hang();
}
- printf (" Board: "); /* Check Board */
+ printf (" Board: "); /* Check Board */
if ((board_type = checkboard()) < 0) {
printf (failed);
if (s)
s = (*e) ? e+1 : e;
}
- bd->bi_intfreq = cpu_speed; /* Internal Freq, in MHz */
- bd->bi_busfreq = get_bus_freq(cpu_speed); /* Bus Freq, in MHz */
+ bd->bi_intfreq = clock_mhz; /* Internal Freq, in MHz */
+ bd->bi_busfreq = get_bus_freq(clock_mhz); /* Bus Freq, in MHz */
bd->bi_baudrate = baudrate; /* Console Baudrate */
/* Function pointers must be added after code relocation */
/* NOTREACHED - relocate_code() does not return */
}
-void hang(void)
-{
- printf ("### ERROR ### Please RESET the board ###\n");
- for (;;);
-}
-
void board_init_r (bd_t *bd, ulong dest_addr)
{
cmd_tbl_t *cmdtp;
/* initialize higher level parts of CPU like time base and timers */
cpu_init_r (bd);
+#ifdef CONFIG_SPD823TS
+ reset_phy ();
+#endif
+
/*
* Enable Interrupts
*/
for (;;)
;
}
+
+void hang(void)
+{
+ printf ("### ERROR ### Please RESET the board ###\n");
+ for (;;);
+}
#include <s_record.h>
+#if (CONFIG_COMMANDS & CFG_CMD_LOADS)
static ulong load_serial (ulong offset);
static int read_record (char *buf, ulong len);
-
static int do_echo = 1;
+#endif
+#if (CONFIG_COMMANDS & CFG_CMD_BDI)
void do_bdinfo (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[])
{
int i;
printf (" install_hdlr= 0x%08lx\n",(ulong)bd->bi_interrupt.install_hdlr);
printf (" free_hdr = 0x%08lx\n",(ulong)bd->bi_interrupt.free_hdlr);
}
+#endif /* CFG_CMD_BDI */
void do_go (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[])
{
printf ("## Application terminated, rc = 0x%lx\n", rc);
}
+#if (CONFIG_COMMANDS & CFG_CMD_LOADS)
void do_load_serial (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[])
{
ulong offset = 0;
*p = '\0';
return (p - buf);
}
+#endif /* CFG_CMD_LOADS */
-#ifdef CONFIG_LOADB /* loadb command (load binary) included */
+#if (CONFIG_COMMANDS & CFG_CMD_LOADB) /* loadb command (load binary) included */
#define XON_CHAR 17
#define XOFF_CHAR 19
return 0;
}
-#endif /* CONFIG_LOADB */
+#endif /* CFG_CMD_LOADB */
(*kernel) (kbd, initrd_start, initrd_end, cmd_start, cmd_end);
}
+#if (CONFIG_COMMANDS & CFG_CMD_IMI)
void do_iminfo (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[])
{
int arg;
printf ("OK\n");
}
}
+#endif /* CFG_CMD_IMI */
static void
print_header (image_header_t *hdr)
#include <command.h>
#include <cmd_cache.h>
+#if (CONFIG_COMMANDS & CFG_CMD_CACHE)
+
static int on_off (const char *);
void do_icache (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[])
switch (argc) {
case 2: /* on / off */
switch (on_off(argv[1])) {
-#if 0 /* prevented by marargs handling; FALLTROUGH is harmless, too */
+#if 0 /* prevented by varargs handling; FALLTROUGH is harmless, too */
default: printf ("Usage:\n%s\n", cmdtp->usage);
return;
#endif
switch (argc) {
case 2: /* on / off */
switch (on_off(argv[1])) {
-#if 0 /* prevented by marargs handling; FALLTROUGH is harmless, too */
+#if 0 /* prevented by varargs handling; FALLTROUGH is harmless, too */
default: printf ("Usage:\n%s\n", cmdtp->usage);
return;
#endif
}
return (-1);
}
+
+#endif /* CFG_CMD_CACHE */
#include <command.h>
#include <cmd_boot.h>
+#if (CONFIG_COMMANDS & CFG_CMD_FLASH)
+
extern flash_info_t flash_info[]; /* info for FLASH chips */
void flash_sect_erase (ulong addr_first, ulong addr_last);
" not on sector boundary\n");
}
}
+
+#endif /* CFG_CMD_FLASH */
#include <command.h>
#include <cmd_mem.h>
+#if (CONFIG_COMMANDS & CFG_CMD_MEMORY)
+
static void mod_mem(int incrflag, int flag, int argc, char *argv[]);
/* Display values from last command.
}
+void do_mem_cmp (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[])
+{
+ ulong size, addr1, addr2, count, ngood;
+
+ if (argc != 4) {
+ printf ("Usage:\n%s\n", cmdtp->usage);
+ return;
+ }
+
+ /* Check for size specification.
+ */
+ size = 4;
+ if (argv[0][3] == '.') {
+ if (argv[0][4] == 'b') {
+ size = 1;
+ } else if (argv[0][4] == 'w') {
+ size = 2;
+ }
+ }
+
+ addr1 = simple_strtoul(argv[1], NULL, 16);
+ addr1 += base_address;
+
+ addr2 = simple_strtoul(argv[2], NULL, 16);
+ addr2 += base_address;
+
+ count = simple_strtoul(argv[3], NULL, 16);
+
+ ngood = 0;
+
+ while (count-- > 0) {
+ if (size == 4) {
+ ulong word1 = *(ulong *)addr1;
+ ulong word2 = *(ulong *)addr2;
+ if (word1 != word2) {
+ printf("word at 0x%08lx (0x%08lx) "
+ "!= word at 0x%08lx (0x%08lx)\n",
+ addr1, word1, addr2, word2);
+ break;
+ }
+ }
+ else if (size == 2) {
+ ushort hword1 = *(ushort *)addr1;
+ ushort hword2 = *(ushort *)addr2;
+ if (hword1 != hword2) {
+ printf("halfword at 0x%08lx (0x%04x) "
+ "!= halfword at 0x%08lx (0x%04x)\n",
+ addr1, hword1, addr2, hword2);
+ break;
+ }
+ }
+ else {
+ u_char byte1 = *(u_char *)addr1;
+ u_char byte2 = *(u_char *)addr2;
+ if (byte1 != byte2) {
+ printf("byte at 0x%08lx (0x%02x) "
+ "!= byte at 0x%08lx (0x%02x)\n",
+ addr1, byte1, addr2, byte2);
+ break;
+ }
+ }
+ ngood++;
+ addr1 += size;
+ addr2 += size;
+ }
+
+ printf("Total of %ld %s%s were the same\n",
+ ngood, size == 4 ? "word" : size == 2 ? "halfword" : "byte",
+ ngood == 1 ? "" : "s");
+}
+
+
void do_mem_cp (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[])
{
ulong addr, size, dest, count;
printf ("CRC32 for %08lx ... %08lx ==> %08lx\n",
addr, addr + length -1, crc);
}
+
+#endif /* CFG_CMD_MEMORY */
#include <cmd_net.h>
#include <net.h>
+#if (CONFIG_COMMANDS & CFG_CMD_NET)
+
+extern void do_bootm (cmd_tbl_t *, bd_t *, int, int, char *[]);
+
static void netboot_common (int, cmd_tbl_t *, bd_t *, int , char *[]);
do_bootm (cmdtp, bd, 0, 2, local_args);
}
}
+
+#endif /* CFG_CMD_NET */
extern uchar environment[];
extern ulong env_size;
+#if (CONFIG_COMMANDS & CFG_CMD_ENV)
static uchar *flash_addr = environment;
+#endif
static uchar *envmatch (uchar *, uchar *);
static void env_init(void);
#endif
#if (CONFIG_BAUDRATE >= 0)
"baudrate=" MK_STR(CONFIG_BAUDRATE) "\0"
+#endif
+#ifdef CONFIG_ETHADDR
+ "ethaddr=" MK_STR(CONFIG_ETHADDR) "\0"
+#endif
+#ifdef CONFIG_IPADDR
+ "ipaddr=" MK_STR(CONFIG_IPADDR) "\0"
+#endif
+#ifdef CONFIG_SERVERIP
+ "serverip=" MK_STR(CONFIG_SERVERIP) "\0"
#endif
"\0"
};
/* end is marked with double '\0' */
*++env = '\0';
+
+ /* Changes of the Ethernet or IP address should be reflected
+ * in the board info structure.
+ */
+
+ if (strcmp(argv[1],"ethaddr") == 0) {
+ char *s = argv[2]; /* always use only one arg */
+ char *e;
+ for (i=0; i<6; ++i) {
+ bd->bi_enetaddr[i] = s ? simple_strtoul(s, &e, 16) : 0;
+ if (s) s = (*e) ? e+1 : e;
+ }
+ } else if (strcmp(argv[1],"ipaddr") == 0) {
+ char *s = argv[2]; /* always use only one arg */
+ char *e;
+ bd->bi_ip_addr = 0;
+ for (i=0; i<4; ++i) {
+ ulong val = s ? simple_strtoul(s, &e, 10) : 0;
+ bd->bi_ip_addr <<= 8;
+ bd->bi_ip_addr |= (val & 0xFF);
+ if (s) s = (*e) ? e+1 : e;
+ }
+ }
}
+#if (CONFIG_COMMANDS & CFG_CMD_ENV)
+
void do_saveenv (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[])
{
int rc;
}
flash_sect_protect (1, sector_flash_addr, sector_flash_addr+sector_flash_size-1);
-#else
+#else /* ! CONFIG_CPCI405 */
+
env_init();
flash_sect_protect (0, (ulong)flash_addr, (ulong)flash_addr+env_size-1);
}
flash_sect_protect (1, (ulong)flash_addr, (ulong)flash_addr+env_size-1);
-#endif
+
+#endif /* CONFIG_CPCI405 */
}
+#endif /* CFG_CMD_ENV */
+
/*
* s1 is either a simple 'name', or a 'name=value' pair.
* s2 is a 'name=value' pair.
"Without arguments, it prints a short usage message for all commands.\n\n" \
"To get detailed help information for specific commands you can type\n" \
"'help' with one or more command names as arguments.\n" \
- )
+ ),
#define CMD_TBL_QUES MK_CMD_TBL_ENTRY( \
"?", 1, CFG_MAXARGS, do_help, \
"? - alias for 'help'\n", \
NULL \
- )
+ ),
#define CMD_TBL_VERS MK_CMD_TBL_ENTRY( \
"version", 4, 1, do_version, \
"version - print monitor version\n", \
NULL \
- )
+ ),
void
do_version (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[])
}
cmd_tbl_t cmd_tbl[] = {
- CMD_TBL_GO,
- CMD_TBL_BOOTM,
- CMD_TBL_BOOTP,
- CMD_TBL_TFTPB,
- CMD_TBL_RARPB,
- CMD_TBL_LOADS,
-#ifdef CONFIG_LOADB
- CMD_TBL_LOADB,
-#endif
- CMD_TBL_MD,
- CMD_TBL_MM,
- CMD_TBL_NM,
- CMD_TBL_MW,
- CMD_TBL_CP,
- CMD_TBL_CRC,
- CMD_TBL_BASE,
- CMD_TBL_PRINTENV,
- CMD_TBL_SETENV,
- CMD_TBL_SAVEENV,
- CMD_TBL_BDINFO,
- CMD_TBL_FLINFO,
- CMD_TBL_IMINFO,
- CMD_TBL_FLERASE,
- CMD_TBL_PROTECT,
- CMD_TBL_LOOP,
- CMD_TBL_MTEST,
- CMD_TBL_ICACHE,
- CMD_TBL_DCACHE,
- CMD_TBL_RESET,
- CMD_TBL_VERS,
- CMD_TBL_HELP,
- CMD_TBL_QUES,
+ CMD_TBL_GO
+ CMD_TBL_BOOTM
+ CMD_TBL_BOOTP
+ CMD_TBL_TFTPB
+ CMD_TBL_RARPB
+ CMD_TBL_LOADS
+ CMD_TBL_LOADB
+ CMD_TBL_MD
+ CMD_TBL_MM
+ CMD_TBL_NM
+ CMD_TBL_MW
+ CMD_TBL_CP
+ CMD_TBL_CMP
+ CMD_TBL_CRC
+ CMD_TBL_BASE
+ CMD_TBL_PRINTENV
+ CMD_TBL_SETENV
+ CMD_TBL_SAVEENV
+ CMD_TBL_BDINFO
+ CMD_TBL_FLINFO
+ CMD_TBL_IMINFO
+ CMD_TBL_FLERASE
+ CMD_TBL_PROTECT
+ CMD_TBL_LOOP
+ CMD_TBL_MTEST
+ CMD_TBL_ICACHE
+ CMD_TBL_DCACHE
+ CMD_TBL_RESET
+ CMD_TBL_VERS
+ CMD_TBL_HELP
+ CMD_TBL_QUES
/* the following entry terminates this table */
- MK_CMD_TBL_ENTRY( NULL, 0, 0, NULL, NULL, NULL ),
+ MK_CMD_TBL_ENTRY( NULL, 0, 0, NULL, NULL, NULL )
};
.ascii MK_STR(CONFIG_BOOTDELAY)
.ascii "\0"
#endif
+#if (CONFIG_BAUDRATE >= 0)
.ascii "baudrate="
.ascii MK_STR(CONFIG_BAUDRATE)
.ascii "\0"
+#endif
.ascii "loads_echo="
.ascii MK_STR(CONFIG_LOADS_ECHO)
.ascii "\0"
+#ifdef CONFIG_ETHADDR
+ .ascii "ethaddr="
+ .ascii MK_STR(CONFIG_ETHADDR)
+ .ascii "\0"
+#endif
+#ifdef CONFIG_IPADDR
+ .ascii "ipaddr="
+ .ascii MK_STR(CONFIG_IPADDR)
+ .ascii "\0"
+#endif
+#ifdef CONFIG_SERVERIP
+ .ascii "serverip="
+ .ascii MK_STR(CONFIG_SERVERIP)
+ .ascii "\0"
+#endif
+
+
/* terminate list of environment strings */
.ascii "\0"
. = environment + CFG_FLASH_ENV_SIZE
ulong flash_get_size (vu_long *addr, flash_info_t *info)
{
short i;
+#if 0
ulong base = (ulong)addr;
+#endif
uchar value;
/* Write auto select command: read Manufacturer ID */
}
}
#else
- flash_get_offsets (addr, &flash_info[0]);
+ flash_get_offsets ((ulong)addr, &flash_info[0]);
#endif
/* check for protected sectors */
ushort cp_cpcr;
u_char res1[2];
ushort cp_rccr;
- u_char res2[6];
+ u_char res2;
+ u_char cp_rmds;
+ u_char res3[4];
ushort cp_cpmcr1;
ushort cp_cpmcr2;
ushort cp_cpmcr3;
ushort cp_cpmcr4;
- u_char res3[2];
- ushort cp_rter;
u_char res4[2];
+ ushort cp_rter;
+ u_char res5[2];
ushort cp_rtmr;
- u_char res5[0x14];
+ u_char res6[0x14];
/* Baud rate generators.
*/
/* Serial Peripheral Interface.
*/
ushort cp_spmode;
- u_char res6[4];
+ u_char res7[4];
u_char cp_spie;
- u_char res7[3];
+ u_char res8[3];
u_char cp_spim;
- u_char res8[2];
- u_char cp_spcom;
u_char res9[2];
+ u_char cp_spcom;
+ u_char res10[2];
/* Parallel Interface Port.
*/
- u_char res10[2];
- ushort cp_pipc;
u_char res11[2];
+ ushort cp_pipc;
+ u_char res12[2];
ushort cp_ptpr;
uint cp_pbdir;
uint cp_pbpar;
- u_char res12[2];
+ u_char res13[2];
ushort cp_pbodr;
uint cp_pbdat;
- u_char res13[0x18];
+ u_char res14[0x18];
/* Serial Interface and Time Slot Assignment.
*/
uint cp_simode;
u_char cp_sigmr;
- u_char res14;
+ u_char res15;
u_char cp_sistr;
u_char cp_sicmr;
- u_char res15[4];
+ u_char res16[4];
uint cp_sicr;
uint cp_sirp;
- u_char res16[0xc];
+ u_char res17[0xc];
/* 256 bytes of MPC823 video controller RAM array.
*/
#ifndef _CMD_BOOT_H
#define _CMD_BOOT_H
+#if (CONFIG_COMMANDS & CFG_CMD_BDI)
#define CMD_TBL_BDINFO MK_CMD_TBL_ENTRY( \
"bdinfo", 2, 1, do_bdinfo, \
"bdinfo - print Board Info structure\n", \
NULL \
-)
+),
void do_bdinfo (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[]);
+#else
+#define CMD_TBL_BDINFO
+#endif
+
+
#define CMD_TBL_GO MK_CMD_TBL_ENTRY( \
"go", 2, CFG_MAXARGS, do_go, \
"go - start application at address 'addr'\n", \
"addr [arg ...]\n - start application at address 'addr'\n" \
" passing 'arg' as arguments\n" \
-)
+),
void do_go (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[]);
+#if (CONFIG_COMMANDS & CFG_CMD_LOADS)
#ifdef CFG_LOADS_BAUD_CHANGE
-
#define CMD_TBL_LOADS MK_CMD_TBL_ENTRY( \
"loads", 5, 3, do_load_serial, \
"loads - load S-Record file over serial line\n", \
"[ off ] [ baud ]\n" \
" - load S-Record file over serial line" \
" with offset 'off' and baudrate 'baud'\n" \
-)
-
+),
#else /* ! CFG_LOADS_BAUD_CHANGE */
-
#define CMD_TBL_LOADS MK_CMD_TBL_ENTRY( \
"loads", 5, 2, do_load_serial, \
"loads - load S-Record file over serial line\n", \
"[ off ]\n" \
" - load S-Record file over serial line with offset 'off'\n" \
-)
+),
#endif /* CFG_LOADS_BAUD_CHANGE */
void do_load_serial (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[]);
-#ifdef CONFIG_LOADB
+#else /* ! CFG_CMD_LOADS */
+#define CMD_TBL_LOADS
+#endif /* CFG_CMD_LOADS */
+
+#if (CONFIG_COMMANDS & CFG_CMD_LOADB)
#define CMD_TBL_LOADB MK_CMD_TBL_ENTRY( \
"loadb", 5, 3, do_load_serial_bin, \
"loadb - load binary file over serial line (kermit mode)\n", \
"[ off ] [ baud ]\n" \
" - load binary file over serial line" \
" with offset 'off' and baudrate 'baud'\n" \
-)
+),
void do_load_serial_bin (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[]);
-#endif /* CONFIG_LOADB */
+#else
+#define CMD_TBL_LOADB
+#endif /* CFG_CMD_LOADB */
#define CMD_TBL_RESET MK_CMD_TBL_ENTRY( \
"reset", 5, 1, do_reset, \
"reset - Perform RESET of the CPU\n", \
NULL \
-)
+),
/* Implemented in $(CPU)/cpu.c */
void do_reset (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[]);
"addr [arg ...]\n - boot application image stored in memory\n" \
" passing arguments 'arg ...'; when booting a Linux kernel,\n" \
" 'arg' can be the address of an initrd image\n" \
-)
+),
+#if (CONFIG_COMMANDS & CFG_CMD_IMI)
void do_iminfo (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[]);
#define CMD_TBL_IMINFO MK_CMD_TBL_ENTRY( \
" - print header information for application image starting at\n" \
" address 'addr' in memory; this includes verification of the\n" \
" image contents (magic number, header and payload checksums)\n" \
-)
+),
+#else
+#define CMD_TBL_IMINFO
+#endif
#endif /* _CMD_BOOTM_H */
#ifndef _CMD_CACHE_H
#define _CMD_CACHE_H
+#if (CONFIG_COMMANDS & CFG_CMD_CACHE)
#define CMD_TBL_ICACHE MK_CMD_TBL_ENTRY( \
"icache", 2, 2, do_icache, \
"icache - enable or disable instruction cache\n", \
"[on, off]\n" \
" - enable or disable instruction cache\n" \
-)
+),
#define CMD_TBL_DCACHE MK_CMD_TBL_ENTRY( \
"dcache", 2, 2, do_dcache, \
"dcache - enable or disable data cache\n", \
"[on, off]\n" \
" - enable or disable data (writethrough) cache\n" \
-)
+),
void do_icache (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[]);
void do_dcache (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[]);
+#else
+#define CMD_TBL_ICACHE
+#define CMD_TBL_DCACHE
+#endif /* CFG_CMD_CACHE */
#endif /* _CMD_CACHE_H */
#ifndef _CMD_FLASH_H
#define _CMD_FLASH_H
+#if (CONFIG_COMMANDS & CFG_CMD_FLASH)
#define CMD_TBL_FLINFO MK_CMD_TBL_ENTRY( \
"flinfo", 3, 2, do_flinfo, \
"flinfo - print FLASH memory information\n", \
"\n - print information for all FLASH memory banks\n" \
"flinfo N\n - print information for FLASH memory bank # N\n" \
-)
+),
#define CMD_TBL_FLERASE MK_CMD_TBL_ENTRY( \
"erase", 3, 3, do_flerase, \
" - erase FLASH from addr 'start' to addr 'end'\n" \
"erase bank N\n - erase FLASH bank # N\n" \
"erase all\n - erase all FLASH banks\n" \
-)
+),
#define CMD_TBL_PROTECT MK_CMD_TBL_ENTRY( \
"protect", 4, 4, do_protect, \
" - make FLASH from addr 'start' to addr 'end' writable\n" \
"protect off bank N\n - make FLASH bank # N writable\n" \
"protect off all\n - make all FLASH banks writable\n" \
-)
+),
void do_flinfo (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[]);
void do_flerase(cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[]);
void do_protect(cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[]);
+#else
+#define CMD_TBL_FLINFO
+#define CMD_TBL_FLERASE
+#define CMD_TBL_PROTECT
+#endif /* CFG_CMD_FLASH */
#endif /* _CMD_FLASH_H */
#ifndef _CMD_MEM_H
#define _CMD_MEM_H
+#if (CONFIG_COMMANDS & CFG_CMD_MEMORY)
#define CMD_TBL_MD MK_CMD_TBL_ENTRY( \
"md", 2, 3, do_mem_md, \
"md - memory display\n", \
"[.b, .w, .l] address [# of objects]\n - memory display\n" \
-)
+),
#define CMD_TBL_MM MK_CMD_TBL_ENTRY( \
"mm", 2, 2, do_mem_mm, \
"mm - memory modify (auto-incrementing)\n", \
"[.b, .w, .l] address\n" \
" - memory modify, auto increment address\n" \
-)
+),
#define CMD_TBL_NM MK_CMD_TBL_ENTRY( \
"nm", 2, 2, do_mem_nm, \
"nm - memory modify (constant address)\n", \
"[.b, .w, .l] address\n - memory modify, read and keep address\n" \
-)
+),
#define CMD_TBL_MW MK_CMD_TBL_ENTRY( \
"mw", 2, 4, do_mem_mw, \
"mw - memory write (fill)\n", \
"[.b, .w, .l] address value [count]\n - write memory\n" \
-)
+),
#define CMD_TBL_CP MK_CMD_TBL_ENTRY( \
"cp", 2, 4, do_mem_cp, \
"cp - memory copy\n", \
"[.b, .w, .l] source target count\n - copy memory\n" \
-)
+),
+#define CMD_TBL_CMP MK_CMD_TBL_ENTRY( \
+ "cmp", 3, 4, do_mem_cmp, \
+ "cmp - memory compare\n", \
+ "[.b, .w, .l] addr1 addr2 count\n - compare memory\n" \
+),
#define CMD_TBL_CRC MK_CMD_TBL_ENTRY( \
"crc32", 3, 4, do_mem_crc, \
"crc32 - checksum calculation\n", \
"address count\n - compute CRC32 checksum\n" \
-)
+),
#define CMD_TBL_BASE MK_CMD_TBL_ENTRY( \
"base", 2, 2, do_mem_base, \
"base - print or set address offset\n", \
"\n - print address offset fpr memory commands\n" \
"base off\n - set address offset for memory commands to 'off'\n" \
-)
+),
/*
* Require full name for "loop" and "mtest" because these are infinite loops!
*/
"loop - infinite loop on address range\n", \
"[.b, .w, .l] address number_of_objects\n" \
" - loop on a set of addresses\n" \
-)
+),
#define CMD_TBL_MTEST MK_CMD_TBL_ENTRY( \
"mtest", 5, 1, do_mem_mtest, \
"mtest - simple RAM test\n", \
"\n - simple SDRAM read/write test\n" \
-)
+),
void do_mem_md (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[]);
void do_mem_mm (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[]);
void do_mem_nm (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[]);
void do_mem_mw (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[]);
void do_mem_cp (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[]);
+void do_mem_cmp (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[]);
void do_mem_crc (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[]);
void do_mem_base (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[]);
void do_mem_loop (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[]);
void do_mem_mtest (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[]);
+#else
+#define CMD_TBL_MD
+#define CMD_TBL_MM
+#define CMD_TBL_NM
+#define CMD_TBL_MW
+#define CMD_TBL_CP
+#define CMD_TBL_CMP
+#define CMD_TBL_CRC
+#define CMD_TBL_BASE
+#define CMD_TBL_LOOP
+#define CMD_TBL_MTEST
+#endif /* CFG_CMD_MEMORY */
+
#endif /* _CMD_MEM_H */
#ifndef _CMD_NET_H
#define _CMD_NET_H
+#if (CONFIG_COMMANDS & CFG_CMD_NET)
#define CMD_TBL_BOOTP MK_CMD_TBL_ENTRY( \
"bootp", 5, 3, do_bootp, \
"bootp - boot image via network using BootP/TFTP protocol\n", \
"[loadAddress] [bootfilename]\n" \
-)
+),
void do_bootp (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[]);
"tftpboot- boot image via network using TFTP protocol\n" \
" and env variables ipaddr and serverip\n", \
"[loadAddress] [bootfilename]\n" \
-)
+),
void do_tftpb (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[]);
"rarpboot", 4, 3, do_rarpb, \
"rarpboot- boot image via network using RARP/TFTP protocol\n", \
"[loadAddress] [bootfilename]\n" \
-)
+),
void do_rarpb (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[]);
+#else
+#define CMD_TBL_BOOTP
+#define CMD_TBL_TFTPB
+#define CMD_TBL_RARPB
+#endif /* CFG_CMD_NET */
+
#endif
"\n - print values of all environment variables\n" \
"printenv name ...\n" \
" - print value of environment variable 'name'\n" \
-)
+),
+void do_printenv (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[]);
#define CMD_TBL_SETENV MK_CMD_TBL_ENTRY( \
"setenv", 6, CFG_MAXARGS, do_setenv, \
" - set environment variable 'name' to 'value ...'\n" \
"setenv name\n" \
" - delete environment variable 'name'\n" \
-)
+),
+void do_setenv (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[]);
+#if (CONFIG_COMMANDS & CFG_CMD_ENV)
#define CMD_TBL_SAVEENV MK_CMD_TBL_ENTRY( \
"saveenv", 4, 1, do_saveenv, \
"saveenv - save environment variables to persistent storage\n", \
NULL \
-)
-
-void do_printenv (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[]);
-void do_setenv (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[]);
+),
void do_saveenv (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[]);
+#else
+#define CMD_TBL_SAVEENV
+#endif /* CFG_CMD_ENV */
#endif /* _CMD_NVEDIT_H */
*/
#define CMD_FLAG_REPEAT 0x0001 /* repeat same command as before */
+/*
+ * Configurable monitor commands
+ */
+#define CFG_CMD_BDI 0x00000001 /* bdinfo */
+#define CFG_CMD_LOADS 0x00000002 /* loads */
+#define CFG_CMD_LOADB 0x00000004 /* loadb */
+#define CFG_CMD_IMI 0x00000008 /* iminfo */
+#define CFG_CMD_CACHE 0x00000010 /* icache, dcache */
+#define CFG_CMD_FLASH 0x00000020 /* flinfo, erase, protect */
+#define CFG_CMD_MEMORY 0x00000040 /* md, mm, nm, mw, cp, cmp, */
+ /* crc, base, loop, mtest */
+#define CFG_CMD_NET 0x00000080 /* bootp, tftpboot, rarpboot */
+#define CFG_CMD_ENV 0x00000100 /* saveenv */
+
+#define CFG_CMD_ALL 0xFFFFFFFF /* ALL commands */
+
+#ifndef CONFIG_COMMANDS
+#define CONFIG_COMMANDS CFG_CMD_ALL
+#endif
+
#endif /* __COMMAND_H */
#define SICR_ENET_CLKRT ((uint)0x00000026)
#endif /* CONFIG_TQM860L */
+/*** SPD823TS ******************************************************/
+
+#ifdef CONFIG_SPD823TS
+/* Bits in parallel I/O port registers that have to be set/cleared
+ * to configure the pins for SCC2 use.
+ */
+#define PROFF_ENET PROFF_SCC2 /* Ethernet at SCC2 */
+#define CPM_CR_ENET CPM_CR_CH_SCC2
+#define SCC_ENET 1 /* index in SCC table starts
+ with 0, so we have here 1 */
+#define PA_ENET_MDC ((ushort)0x0001) /* PA 15 !!! */
+#define PA_ENET_MDIO ((ushort)0x0002) /* PA 14 !!! */
+#define PA_ENET_RXD ((ushort)0x0004) /* PA 13 */
+#define PA_ENET_TXD ((ushort)0x0008) /* PA 12 */
+#define PA_ENET_RCLK ((ushort)0x0200) /* PA 6 */
+#define PA_ENET_TCLK ((ushort)0x0400) /* PA 5 */
+
+#define PB_ENET_TENA ((uint)0x00002000) /* PB 18 */
+
+#define PC_ENET_CLSN ((ushort)0x0040) /* PC 9 */
+#define PC_ENET_RENA ((ushort)0x0080) /* PC 8 */
+#define PC_ENET_RESET ((ushort)0x0100) /* PC 7 !!! */
+
+/* Control bits in the SICR to route TCLK (CLK3) and RCLK (CLK2) to
+ * SCC2. Also, make sure GR2 (bit 16) and SC2 (bit 17) are zero.
+ */
+#define SICR_ENET_MASK ((uint)0x0000ff00)
+#define SICR_ENET_CLKRT ((uint)0x00002E00)
+#endif /* CONFIG_SPD823TS */
+
/**********************************************************************/
/* SCC Event register as used by Ethernet.
#define CONFIG_DRAM_SPEED (CONFIG_BUSCLOCK) /* MHz */
+#define CONFIG_COMMANDS (CFG_CMD_ALL & ~CFG_CMD_NET) /* no network on ADCIOP */
+
/*
* Miscellaneous configurable options
*/
#define CFG_PCMCIA_IO_ADDR (0xEC000000)
#define CFG_PCMCIA_IO_SIZE ( 64 << 20 )
-#define CFG_PCMCIA_INTERRUPT SIU_LEVEL6
-
/*-----------------------------------------------------------------------
*
*-----------------------------------------------------------------------
#define CONFIG_MPC860 1
#define CONFIG_MPC860T 1
-#define CONFIG_FADS 1
+#define CONFIG_FADS 1
#define CONFIG_8xx_CPUCLOCK 50
#define CONFIG_8xx_BUSCLOCK (CONFIG_8xx_CPUCLOCK)
#define CONFIG_BAUDRATE 9600
#if 0
-#define MPC8XX_FACT 10 /* Multiply by 10 */
-#define MPC8XX_XIN 50000000 /* 50 MHz in */
+#define MPC8XX_FACT 10 /* Multiply by 10 */
+#define MPC8XX_XIN 50000000 /* 50 MHz in */
#else
-#define MPC8XX_FACT 12 /* Multiply by 12 */
-#define MPC8XX_XIN 4000000 /* 4 MHz in */
+#define MPC8XX_FACT 12 /* Multiply by 12 */
+#define MPC8XX_XIN 4000000 /* 4 MHz in */
#define MPC8XX_HZ ((MPC8XX_XIN) * (MPC8XX_FACT))
#endif
#define CONFIG_DRAM_SPEED (CONFIG_8xx_BUSCLOCK) /* MHz */
#define CONFIG_BOOTCOMMAND "bootm 2800100" /* autoboot command */
#define CONFIG_BOOTARGS " "
+
+#define CONFIG_COMMANDS (CFG_CMD_ALL & ~CFG_CMD_NET) /* no network yet ??? */
+
/*
* Miscellaneous configurable options
*/
#undef CFG_LONGHELP /* undef to save memory */
-#define CFG_PROMPT ":>" /* Monitor Command Prompt */
-#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define CFG_MAXARGS 8 /* max number of command args */
+#define CFG_PROMPT ":>" /* Monitor Command Prompt */
+#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS 8 /* max number of command args */
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
-#define CFG_MEMTEST_START 0x0000000 /* memtest works on */
+#define CFG_MEMTEST_START 0x0100000 /* memtest works on */
#define CFG_MEMTEST_END 0x0400000 /* 1 ... 4 MB in DRAM */
-#define CFG_TFTP_LOADADDR 0x00100000
+#define CFG_TFTP_LOADADDR 0x00100000
/*
#define CFG_FLASH_SIZE ((uint)(8 * 1024 * 1024)) /* max 8Mbyte */
-#define CFG_MONITOR_LEN (384 << 10) /* Reserve 384 kB for Monitor */
-#define CFG_HWINFO_LEN 0x0040 /* Length of HW Info Data */
-#define CFG_MALLOC_LEN (384 << 10) /* Reserve 384 kB for malloc() */
+#define CFG_MONITOR_LEN (384 << 10) /* Reserve 384 kB for Monitor */
+#define CFG_HWINFO_LEN 0x0040 /* Length of HW Info Data */
+#define CFG_MALLOC_LEN (384 << 10) /* Reserve 384 kB for malloc() */
#if 0
#define CFG_HWINFO_ADDR (CFG_FLASH_BASE + CFG_MONITOR_LEN - CFG_HWINFO_LEN)
/*-----------------------------------------------------------------------
* FLASH organization
*/
-#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
-#define CFG_MAX_FLASH_SECT 8 /* max number of sectors on one chip */
+#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
+#define CFG_MAX_FLASH_SECT 8 /* max number of sectors on one chip */
#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
/*-----------------------------------------------------------------------
* Cache Configuration
*/
-#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
+#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
/*-----------------------------------------------------------------------
* SYPCR - System Protection Control 11-9
#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
/*-----------------------------------------------------------------------
- * SUMCR - SIU Module Configuration 11-6
+ * SUMCR - SIU Module Configuration 11-6
*-----------------------------------------------------------------------
* PCMCIA config., multi-function pin tri-state
*/
/* BCSRx - Board Control and Status Registers */
#define CFG_OR1_REMAP CFG_OR0_REMAP
-#define CFG_OR1_PRELIM 0xffff8110 /* 64Kbyte address space */
+#define CFG_OR1_PRELIM 0xffff8110 /* 64Kbyte address space */
#define CFG_BR1_PRELIM ((BCSR_ADDR) | BR_V )
*/
/* periodic timer for refresh */
-#define CFG_MAMR_PTA 97 /* start with divider for 100 MHz */
+#define CFG_MAMR_PTA 97 /* start with divider for 100 MHz */
/* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit */
#define CFG_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */
*
* Boot Flags
*/
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
+#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
+#define BOOTFLAG_WARM 0x02 /* Software reboot */
/* values according to the manual */
--- /dev/null
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_MPC823 1 /* This is a MPC823 CPU */
+#define CONFIG_SPD823TS 1 /* ...on a SPD823TS board */
+
+#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
+#undef CONFIG_8xx_CONS_SMC2
+#define CONFIG_BAUDRATE 115200
+#if 0
+#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
+#else
+#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
+#endif
+#define CONFIG_BOOTCOMMAND "bootp" /* autoboot command */
+
+#define CONFIG_BOOTARGS "root=/dev/nfs rw " \
+ "nfsroot=10.0.0.2:/LinuxPPC " \
+ "nfsaddrs=10.0.0.99:10.0.0.2"
+
+#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
+#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */
+
+/*----------------------------------------------------------------------*/
+#define CONFIG_ETHADDR 00:d0:93:00:01:cb
+#define CONFIG_IPADDR 10.0.0.98
+#define CONFIG_SERVERIP 10.0.0.1
+/*----------------------------------------------------------------------*/
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP /* undef to save memory */
+#define CFG_PROMPT "=> " /* Monitor Command Prompt */
+#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS 8 /* max number of command args */
+#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
+
+#define CFG_MEMTEST_START 0x00100000 /* memtest works on */
+#define CFG_MEMTEST_END 0x00F00000 /* 1 ... 15MB in DRAM */
+
+#define CFG_TFTP_LOADADDR 0x00100000 /* default load address */
+
+/*
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ */
+/*-----------------------------------------------------------------------
+ * Internal Memory Mapped Register
+ */
+#define CFG_IMMR 0xFFF00000 /* was: 0xFF000000 */
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CFG_SDRAM_BASE _must_ start at 0
+ */
+#define CFG_SDRAM_BASE 0x00000000
+#define CFG_FLASH_BASE 0x0C000000
+#ifdef DEBUG
+#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
+#else
+#define CFG_MONITOR_LEN (128 << 10) /* Reserve 128 kB for Monitor */
+#endif
+#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CFG_MAX_FLASH_BANKS 0 /* max number of memory banks */
+#define CFG_MAX_FLASH_SECT 0 /* max number of sectors on one chip */
+
+#define CFG_FLASH_ERASE_TOUT 0 /* Timeout for Flash Erase (in ms) */
+#define CFG_FLASH_WRITE_TOUT 0 /* Timeout for Flash Write (in ms) */
+
+#define CFG_FLASH_ENV_OFFSET 0x8000 /* Offset of Environment Sector */
+#define CFG_FLASH_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
+
+/*-----------------------------------------------------------------------
+ * SYPCR - System Protection Control 11-9
+ * SYPCR can only be written once after reset!
+ *-----------------------------------------------------------------------
+ * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
+ */
+#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
+
+/*-----------------------------------------------------------------------
+ * SUMCR - SIU Module Configuration 11-6
+ *-----------------------------------------------------------------------
+ * PCMCIA config., multi-function pin tri-state
+ */
+/* 0x00000040 */
+#define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC00 | SIUMCR_GB5E)
+
+/*-----------------------------------------------------------------------
+ * TBSCR - Time Base Status and Control 11-26
+ *-----------------------------------------------------------------------
+ * Clear Reference Interrupt Status, Timebase freezing enabled
+ */
+#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
+
+/*-----------------------------------------------------------------------
+ * PISCR - Periodic Interrupt Status and Control 11-31
+ *-----------------------------------------------------------------------
+ * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
+ */
+#define CFG_PISCR (PISCR_PS | PISCR_PITF)
+
+/*-----------------------------------------------------------------------
+ * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
+ *-----------------------------------------------------------------------
+ * Reset PLL lock status sticky bit, timer expired status bit and timer
+ * interrupt status bit, set PLL multiplication factor !
+ */
+/* 0x00b0c0c0 */
+#define CFG_PLPRCR \
+ 11 << (PLPRCR_MF_SHIFT) | \
+ (PLPRCR_SPLSS | PLPRCR_TEXPS| /*PLPRCR_TMIST|*/ \
+ /*PLPRCR_CSRC|*/ PLPRCR_LPM_NORMAL| \
+ PLPRCR_CSR|PLPRCR_LOLRE/*|PLPRCR_FIOPD*/)
+
+/*-----------------------------------------------------------------------
+ * SCCR - System Clock and reset Control Register 15-27
+ *-----------------------------------------------------------------------
+ * Set clock output, timebase and RTC source and divider,
+ * power management and some other internal clocks
+ */
+#define SCCR_MASK SCCR_EBDF11
+/* 0x01800014 */
+#define CFG_SCCR (SCCR_COM00 | /*SCCR_TBS|*/ \
+ SCCR_RTDIV | SCCR_RTSEL | \
+ /*SCCR_CRQEN|*/ /*SCCR_PRQEN|*/ \
+ SCCR_EBDF00 | SCCR_DFSYNC00 | \
+ SCCR_DFBRG00 | SCCR_DFNL000 | \
+ SCCR_DFNH000 | SCCR_DFLCD101 | \
+ SCCR_DFALCD00)
+
+/*-----------------------------------------------------------------------
+ * RTCSC - Real-Time Clock Status and Control Register
+ *-----------------------------------------------------------------------
+ */
+/* 0xc2 */
+#define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF)
+
+
+/*-----------------------------------------------------------------------
+ * RCCR - RISC Controller Configuration Register
+ *-----------------------------------------------------------------------
+ */
+/* TIMEP=2 */
+#define CFG_RCCR 0x0200
+
+/*-----------------------------------------------------------------------
+ * RMDS - RISC Microcode Development Support Control Register
+ *-----------------------------------------------------------------------
+ */
+#define CFG_RMDS 0
+
+/*-----------------------------------------------------------------------
+ * SDSR - SDMA Status Register
+ *-----------------------------------------------------------------------
+ */
+#define CFG_SDSR ((u_char)0x83)
+
+/*-----------------------------------------------------------------------
+ * SDMR - SDMA Mask Register
+ *-----------------------------------------------------------------------
+ */
+#define CFG_SDMR ((u_char)0x00)
+
+/*-----------------------------------------------------------------------
+ *
+ * Interrupt Levels
+ *-----------------------------------------------------------------------
+ */
+#define CFG_CPM_INTERRUPT 13 /* SIU_LEVEL6 */
+
+/*-----------------------------------------------------------------------
+ * PCMCIA stuff
+ *-----------------------------------------------------------------------
+ *
+ */
+#define CFG_PCMCIA_MEM_ADDR (0xE0000000)
+#define CFG_PCMCIA_MEM_SIZE ( 64 << 20 )
+#define CFG_PCMCIA_DMA_ADDR (0xE4000000)
+#define CFG_PCMCIA_DMA_SIZE ( 64 << 20 )
+#define CFG_PCMCIA_ATTRB_ADDR (0xE8000000)
+#define CFG_PCMCIA_ATTRB_SIZE ( 64 << 20 )
+#define CFG_PCMCIA_IO_ADDR (0xEC000000)
+#define CFG_PCMCIA_IO_SIZE ( 64 << 20 )
+
+/*-----------------------------------------------------------------------
+ *
+ *-----------------------------------------------------------------------
+ *
+ */
+/*#define CFG_DER 0x2002000F*/
+#define CFG_DER 0
+
+#define MPC8XX_FACT 1 /* Multiply by 1 */
+#if 0
+#define MPC8XX_XIN 50000000 /* 50 MHz in - ??? - XXX */
+/* #define MPC8XX_BUSDIV 2 */
+#define MPC8XX_HZ ((MPC8XX_XIN) * (MPC8XX_FACT))
+#endif
+
+/*
+ * Init Memory Controller:
+ *
+ * BR0/1 and OR0/1 (FLASH)
+ */
+
+#define SD 1
+
+#ifdef SD
+#define FLASH_BASE0_PRELIM 0x0C000000 /* FLASH bank #0 */
+#define FLASH_BASE1_PRELIM 0x0C080000 /* FLASH bank #1 */
+#else
+#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */
+#define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #1 */
+#endif
+
+/* used to re-map FLASH both when starting from SRAM or FLASH:
+ * restrict access enough to keep SRAM working (if any)
+ * but not too much to meddle with FLASH accesses
+ */
+/* EPROMs are 512kb */
+#ifdef SD
+#define CFG_REMAP_OR_AM 0xFFF80000 /* OR addr mask */
+#define CFG_PRELIM_OR_AM 0xFFF80000 /* OR addr mask */
+#else
+#define CFG_REMAP_OR_AM 0x80000000 /* OR addr mask */
+#define CFG_PRELIM_OR_AM 0xE0000000 /* OR addr mask */
+#endif
+
+/* FLASH timing: ACS = 11, TRLX = 0, CSNT = 1, SCY = 5, EHTR = 1 */
+#define CFG_OR_TIMING_FLASH (/* OR_CSNT_SAM | */ OR_ACS_DIV4 | OR_BI | \
+ OR_SCY_5_CLK | OR_EHTR)
+
+#define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH)
+#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
+/* 16 bit, bank valid */
+#define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V )
+
+#define CFG_OR1_REMAP CFG_OR0_REMAP
+#define CFG_OR1_PRELIM CFG_OR0_PRELIM
+/* 16 bit, bank valid */
+#define CFG_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V )
+
+/*
+ * BR2-5 and OR2-5 (SRAM/SDRAM/PER8/SHARC)
+ *
+ */
+#define SRAM_BASE2_PRELIM 0x04200000 /* SRAM bank */
+#define SRAM_PRELIM_OR_AM 0xFFE00000 /* SRAM is 2 MB */
+
+#define SDRAM_BASE3_PRELIM 0x00000000 /* SDRAM bank */
+#define SDRAM_PRELIM_OR_AM 0xE0000000 /* SDRAM is 16 MB */
+/* #define SDRAM_PRELIM_OR_AM 0xFF000000*/ /* SDRAM is 16 MB */
+#define SDRAM_MAX_SIZE 0x01000000 /* max 16 MB SDRAM */
+
+#define PER8_BASE4_PRELIM 0x04000000 /* PER8 bank */
+#define PER8_PRELIM_OR_AM 0xFFF00000 /* PER8 is 1 MB */
+
+#define SHARC_BASE5_PRELIM 0x04400000 /* SHARC bank */
+#define SHARC_PRELIM_OR_AM 0xFFC00000 /* SHARC is 4 MB */
+
+/* SRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */
+
+#define CFG_OR_TIMING_SRAM 0x00000D42 /* SRAM-Timing */
+#define CFG_OR2_PRELIM (SRAM_PRELIM_OR_AM | CFG_OR_TIMING_SRAM )
+#define CFG_BR2_PRELIM ((SRAM_BASE2_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V )
+
+/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */
+
+#define CFG_OR_TIMING_SDRAM 0x00000A00 /* SDRAM-Timing */
+#define CFG_OR3_PRELIM (SDRAM_PRELIM_OR_AM | CFG_OR_TIMING_SDRAM )
+#define CFG_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | \
+ BR_MS_UPMB | BR_V )
+
+#define CFG_OR_TIMING_PER8 0x00000F32 /* PER8-Timing */
+#define CFG_OR4_PRELIM (PER8_PRELIM_OR_AM | CFG_OR_TIMING_PER8 )
+#define CFG_BR4_PRELIM ((PER8_BASE4_PRELIM & BR_BA_MSK) | BR_PS_8 | \
+ BR_V )
+
+#define CFG_OR_TIMING_SHARC 0x00000700 /* SHARC-Timing */
+#define CFG_OR5_PRELIM (SHARC_PRELIM_OR_AM | CFG_OR_TIMING_PER8 )
+#define CFG_BR5_PRELIM ((SHARC_BASE5_PRELIM & BR_BA_MSK) | BR_PS_32 | \
+ BR_MS_UPMA | BR_V )
+/*
+ * Memory Periodic Timer Prescaler
+ */
+
+/* periodic timer for refresh */
+#define CFG_MAMR_PTB 204
+
+/* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit */
+#define CFG_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */
+#define CFG_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */
+
+/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */
+#define CFG_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */
+#define CFG_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */
+
+/*
+ * MBMR settings for SDRAM
+ */
+
+/* 8 column SDRAM */
+#define CFG_MBMR_8COL ((CFG_MAMR_PTB << MAMR_PTB_SHIFT) | \
+ MAMR_AMB_TYPE_0 | MAMR_DSB_1_CYCL | MAMR_G0CLB_A11 | \
+ MAMR_RLFB_1X | MAMR_WLFB_1X | MAMR_TLFB_4X)
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
+#define BOOTFLAG_WARM 0x02 /* Software reboot */
+
+#endif /* __CONFIG_H */
#define CFG_PCMCIA_IO_ADDR (0xEC000000)
#define CFG_PCMCIA_IO_SIZE ( 64 << 20 )
-#define CFG_PCMCIA_INTERRUPT SIU_LEVEL6
-
/*-----------------------------------------------------------------------
*
*-----------------------------------------------------------------------
#define CFG_PCMCIA_IO_ADDR (0xEC000000)
#define CFG_PCMCIA_IO_SIZE ( 64 << 20 )
-#define CFG_PCMCIA_INTERRUPT SIU_LEVEL6
-
/*-----------------------------------------------------------------------
*
*-----------------------------------------------------------------------
#define CFG_PCMCIA_IO_ADDR (0xEC000000)
#define CFG_PCMCIA_IO_SIZE ( 64 << 20 )
-#define CFG_PCMCIA_INTERRUPT SIU_LEVEL6
-
/*-----------------------------------------------------------------------
*
*-----------------------------------------------------------------------
#define SCCR_COM10 0x40000000 /* reserved */
#define SCCR_COM11 0x60000000 /* CLKOUT output buffer disabled */
#define SCCR_TBS 0x02000000 /* Time Base Source */
-#define SCCR_RTDIV 0x01000000 /* RTC Clock Dive */
+#define SCCR_RTDIV 0x01000000 /* RTC Clock Divide */
#define SCCR_RTSEL 0x00800000 /* RTC circuit input source select */
#define SCCR_CRQEN 0x00400000 /* CPM Request Enable */
#define SCCR_PRQEN 0x00200000 /* Power Management Request Enable */
#define SCCR_DFNH110 0x000000D0 /* Division by 64 (maximum) */
#define SCCR_DFNH111 0x000000E0 /* reserved */
#define SCCR_DFLCD000 0x00000000 /* Division by 1 (default = minimum) */
-#define SCCR_DFLCD110 0x00000180 /* Division by 64 (maximum) */
-#define SCCR_DFLCD111 0x000001C0 /* reserved */
+#define SCCR_DFLCD101 0x00000014 /* Division by 32 */
+#define SCCR_DFLCD110 0x00000018 /* Division by 64 (maximum) */
+#define SCCR_DFLCD111 0x0000001C /* reserved */
#define SCCR_DFALCD00 0x00000000 /* Division by 1 (default = minimum) */
#define SCCR_DFALCD01 0x00000001 /* Division by 3 */
#define SCCR_DFALCD10 0x00000002 /* Division by 5 */
* Machine B Mode Register 16-13
*/
#define MAMR_PTB_MSK 0xff000000 /* Periodic Timer B period mask */
+#define MAMR_PTB_SHIFT 0x00000018 /* Periodic Timer B period shift */
#define MAMR_PTBE 0x00800000 /* Periodic Timer B Enable */
#define MAMR_AMB_MSK 0x00700000 /* Addess Multiplex size B */
+#define MAMR_AMB_TYPE_0 0x00000000 /* Addess Multiplexing Type 0 */
+#define MAMR_AMB_TYPE_1 0x00100000 /* Addess Multiplexing Type 1 */
+#define MAMR_AMB_TYPE_2 0x00200000 /* Addess Multiplexing Type 2 */
+#define MAMR_AMB_TYPE_3 0x00300000 /* Addess Multiplexing Type 3 */
+#define MAMR_AMB_TYPE_4 0x00400000 /* Addess Multiplexing Type 4 */
+#define MAMR_AMB_TYPE_5 0x00500000 /* Addess Multiplexing Type 5 */
#define MAMR_DSB_MSK 0x00060000 /* Disable Timer period mask */
#define MAMR_DSB_1_CYCL 0x00000000 /* 1 cycle Disable Period */
#define MAMR_DSB_2_CYCL 0x00020000 /* 2 cycle Disable Period */
* My personal preference is CPM at level 2, which puts it above the
* MBX PCI/ISA/IDE interrupts.
*/
-#define PIT_INTERRUPT SIU_LEVEL0
-#define CPM_INTERRUPT SIU_LEVEL2
-#define PCMCIA_INTERRUPT SIU_LEVEL6
-#define DEC_INTERRUPT SIU_LEVEL7
+
+#ifdef CFG_CPM_INTERRUPT
+# define CPM_INTERRUPT CFG_CPM_INTERRUPT
+#else
+# define CPM_INTERRUPT SIU_LEVEL2
+#endif
/* Some internal interrupt registers use an 8-bit mask for the interrupt
* level instead of a number.
void main_loop (bd_t *);
void hang (void);
-void udelay (unsigned long);
/* */
void display_options (void);
/* common/main.c */
-int readline (const char *const prompt);
-void command_repeat_off (void);
+int readline (const char *const prompt);
+void command_repeat_off (void);
/* common/board.c */
void board_init_f (ulong);
void pciinfo (int);
#endif
+#ifdef CONFIG_SPD823TS
+/* $(BOARD)/spd8xx.c */
+void reset_phy (void);
+#endif
+
/* $(CPU)/serial.c */
void serial_init (ulong, int);
void serial_setbrg (ulong, int);
void relocate_code (ulong, bd_t *, ulong);
ulong get_endaddr (void);
void trap_init (ulong);
+void wait_ticks (unsigned long);
#ifdef CONFIG_4xx
unsigned char in8(unsigned int);
void out8(unsigned int, unsigned char);
int checkicache (void);
int checkdcache (void);
void upmconfig (unsigned int, unsigned int *, unsigned int);
+void udelay (unsigned long);
/* $(CPU)/speed.c */
ulong get_gclk_freq (void);
#ifndef __VERSION_H__
#define __VERSION_H__
-#define PPCBOOT_VERSION "ppcboot 0.5.0"
+#define PPCBOOT_VERSION "ppcboot 0.5.1"
#endif /* __VERSION_H__ */
}
/* ------------------------------------------------------------------------- */
+
+/*
+ * We implement the delay by converting the delay (the number of
+ * microseconds to wait) into a number of time base ticks; then we
+ * watch the time base until it has incremented by that amount.
+ */
+void udelay(unsigned long usec)
+{
+ extern ulong cpu_speed;
+ ulong tbclk;
+ ulong ticks;
+
+ if (((volatile immap_t *)CFG_IMMR)->im_clkrst.car_sccr & SCCR_TBS) {
+ tbclk = cpu_speed / 16;
+ } else {
+ ulong oscclk = cpu_speed /
+ ((((CFG_PLPRCR) & PLPRCR_MF_MSK) >> PLPRCR_MF_SHIFT)+1);
+ tbclk = oscclk / 4;
+ }
+ ticks = ((usec * (tbclk/1000)) + 500) / 1000;
+
+ wait_ticks (ticks);
+}
+
+/* ------------------------------------------------------------------------- */
#include <ppcboot.h>
#include <mpc8xx.h>
+#include <commproc.h>
/*
* Breath some life into the CPU...
* has been determined
*/
+ memctl->memc_br0 = CFG_BR0_PRELIM; /* XXX ??? XXX ??? XXX */
+
memctl->memc_or0 = CFG_OR0_REMAP;
memctl->memc_or1 = CFG_OR1_REMAP;
memctl->memc_or1 = CFG_OR1_PRELIM;
memctl->memc_br1 = CFG_BR1_PRELIM;
+
+ /*
+ * Reset CPM
+ */
+ immr->im_cpm.cp_cpcr = CPM_CR_RST;
+ do { /* Spin until command processed */
+ __asm__ ("eieio");
+ } while (immr->im_cpm.cp_cpcr & CPM_CR_FLG);
}
/*
/* Enable Time Base so udelay() works */
immr->im_sit.sit_tbscr |= TBSCR_TBE;
+
+#ifdef CFG_RTCSC
+ /* Unlock RTSC register */
+ immr->im_sitk.sitk_rtcsck = KAPWR_KEY;
+ /* write config value */
+ immr->im_sit.sit_rtcsc = CFG_RTCSC;
+#endif
+
+#ifdef CFG_RCCR
+ /* write config value */
+ immr->im_cpm.cp_rccr = CFG_RCCR;
+#endif
+
+#ifdef CFG_RMDS
+ /* write config value */
+ immr->im_cpm.cp_rmds = CFG_RMDS;
+#endif
}
*
*/
-
/*
* MPC823 <-> MC68160 Connections:
*
*
*/
-#include "ppcboot.h"
-#include "commproc.h"
-#include "net.h"
+#include <ppcboot.h>
+#include <commproc.h>
+#include <net.h>
+#include <command.h>
+
+#if (CONFIG_COMMANDS & CFG_CMD_NET)
#define BD_OFFSET 0x860 /* offset to begin of DPRAM + allocation for serial IF*/
/* assign static pointer to BD area */
rtx = (RTXBD *) (immr->im_cpm.cp_dpmem + BD_OFFSET);
-
/* Configure port A pins for Txd and Rxd.
*/
immr->im_ioport.iop_papar |= (PA_ENET_RXD | PA_ENET_TXD);
rtx->txbd[TX_BUF_CNT - 1].cbd_sc |= BD_ENET_TX_WRAP;
+ /*
+ * Enter Command: Initialize Rx Params for SCC
+ */
+
+ do { /* Spin until ready to issue command */
+ __asm__ ("eieio");
+ } while (immr->im_cpm.cp_cpcr & CPM_CR_FLG);
+ /* Issue command */
+ immr->im_cpm.cp_cpcr = ((CPM_CR_INIT_RX << 8) | (CPM_CR_ENET << 4) | CPM_CR_FLG);
+ do { /* Spin until command processed */
+ __asm__ ("eieio");
+ } while (immr->im_cpm.cp_cpcr & CPM_CR_FLG);
+
/*
* Ethernet Specific Parameter RAM
* see table 13-16, pg. 660,
pram_ptr->sen_disfc = 0x0; /* Discard Frame Counter (unused) */
pram_ptr->sen_pads = 0x8888; /* Short Frame PAD Characters */
- pram_ptr->sen_retlim = 0xf; /* Retry Limit Threshold */
+ pram_ptr->sen_retlim = 15; /* Retry Limit Threshold */
pram_ptr->sen_maxflr = 1518; /* MAX Frame Length Register */
pram_ptr->sen_minflr = 64; /* MIN Frame Length Register */
- pram_ptr->sen_maxd1 = 1518; /* MAX DMA1 Length Register */
- pram_ptr->sen_maxd2 = 1518; /* MAX DMA2 Length Register */
+ pram_ptr->sen_maxd1 = DBUF_LENGTH; /* MAX DMA1 Length Register */
+ pram_ptr->sen_maxd2 = DBUF_LENGTH; /* MAX DMA2 Length Register */
pram_ptr->sen_gaddr1 = 0x0; /* Group Address Filter 1 (unused) */
pram_ptr->sen_gaddr2 = 0x0; /* Group Address Filter 2 (unused) */
pram_ptr->sen_taddrl = 0x0; /* Tmp Address (LSB) (unused) */
/*
- * Enter Command: Initialize Rx and Tx Params for SCC
+ * Enter Command: Initialize Tx Params for SCC
*/
- while( immr->im_cpm.cp_cpcr & CPM_CR_FLG ){} /* SPIN UNTIL READY TO ISSUE COMMAND */
- /* ISSUE COMMAND */
- immr->im_cpm.cp_cpcr = ((CPM_CR_INIT_TRX << 8) | (CPM_CR_ENET << 4) | CPM_CR_FLG);
- while( immr->im_cpm.cp_cpcr & CPM_CR_FLG ){} /* SPIN UNTIL COMMAND PROCESSED */
+ do { /* Spin until ready to issue command */
+ __asm__ ("eieio");
+ } while (immr->im_cpm.cp_cpcr & CPM_CR_FLG);
+ /* Issue command */
+ immr->im_cpm.cp_cpcr = ((CPM_CR_INIT_TX << 8) | (CPM_CR_ENET << 4) | CPM_CR_FLG);
+ do { /* Spin until command processed */
+ __asm__ ("eieio");
+ } while (immr->im_cpm.cp_cpcr & CPM_CR_FLG);
/*
* Clear Events in SCCE -- Clear bits by writing 1's
*/
- immr->im_cpm.cp_scc[SCC_ENET].scc_scce = ~(0x0); /*SCC2 */
+ immr->im_cpm.cp_scc[SCC_ENET].scc_scce = ~(0x0);
* MODE = Ethernet
*/
- immr->im_cpm.cp_scc[SCC_ENET].scc_gsmrl = (SCC_GSMRL_TCI | SCC_GSMRL_TPL_48 | SCC_GSMRL_TPP_10 | SCC_GSMRL_MODE_ENET);
+ immr->im_cpm.cp_scc[SCC_ENET].scc_gsmrl = ( SCC_GSMRL_TCI | \
+ SCC_GSMRL_TPL_48 | \
+ SCC_GSMRL_TPP_10 | \
+ SCC_GSMRL_MODE_ENET);
/*
* Initialize the DSR -- see section 13.14.4 (pg. 513) v0.4
void eth_halt(void)
{
- volatile immap_t *immr = (immap_t *)CFG_IMMR;
- immr->im_cpm.cp_scc[SCC_ENET].scc_gsmrl &= ~(SCC_GSMRL_ENR | SCC_GSMRL_ENT);
+ volatile immap_t *immr = (immap_t *)CFG_IMMR;
+ immr->im_cpm.cp_scc[SCC_ENET].scc_gsmrl &= ~(SCC_GSMRL_ENR | SCC_GSMRL_ENT);
}
#if 0
immr->im_cpm.cp_scc[SCC_ENET].scc_gsmrl |= (SCC_GSMRL_ENR | SCC_GSMRL_ENT);
}
#endif
+
+#endif /* CFG_CMD_NET */
*/
im->im_siu_conf.sc_sdcr = 1;
+#ifdef CFG_SDSR
+ im->im_sdma.sdma_sdsr = CFG_SDSR;
+#endif
+
+#ifdef CFG_SDMR
+ im->im_sdma.sdma_sdmr = CFG_SDMR;
+#endif
+
#if defined(CONFIG_8xx_CONS_SMC1)
/* Use Port B for SMC1 instead of other functions.
*/
ulong get_gclk_freq (void)
{
+#ifndef CONFIG_8xx_GCLK_FREQ
volatile immap_t *immap = (immap_t *)CFG_IMMR;
volatile cpmtimer8xx_t *timerp = &immap->im_cpmtimer;
ulong timer2_val;
immap->im_sit.sit_piscr &= ~PISCR_PTE;
return (timer2_val * 400000L); /* convert to Hz */
+
+#else /* CONFIG_8xx_GCLK_FREQ */
+
+ /*
+ * If for some reason measuring the gclk frequency won't work,
+ * we return the hardwired value.
+ * (For example, the cogent CMA286-60 CPU module has no
+ * separate oscillator for PITRTCLK)
+ */
+
+ return (CONFIG_8xx_GCLK_FREQ);
+
+#endif /* CONFIG_8xx_GCLK_FREQ */
}
/* ------------------------------------------------------------------------- */
blr
/*
- * Delay for a number of microseconds
- * -- Use the BUS timer (assumes 50 MHz) -- FIXME --
+ * Delay for a number of ticks
*/
- .globl udelay
-udelay:
- mulli r4,r3,10000 /* 50 MHz / 16 = 3125000 */
- li r5,3125
- divw r4,r4,r5 /* BUS ticks */
-1: mftbu r5
- mftb r6
- mftbu r7
- cmp 0,r5,r7
+ .globl wait_ticks
+wait_ticks:
+1: mftbu r4
+ mftb r5
+ mftbu r6
+ cmp 0,r4,r6
bne 1b /* Get [synced] base time */
- addc r9,r6,r4 /* Compute end time */
- addze r8,r5
-2: mftbu r5
- cmp 0,r5,r8
+ addc r9,r5,r3 /* Compute end time */
+ addze r8,r4
+2: mftbu r4
+ cmp 0,r4,r8
blt 2b
bgt 3f
- mftb r6
- cmp 0,r6,r9
+ mftb r5
+ cmp 0,r5,r9
blt 2b
3: blr
static int TftpTimeoutCount;
static unsigned TftpBlock;
static unsigned TftpLastBlock;
-static unsigned TftpSize;
static int TftpState;
#define STATE_RRQ 1
#define STATE_DATA 2
--- /dev/null
+#
+# (C) Copyright 2000
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = lib$(BOARD).a
+
+OBJS = $(BOARD).o flash.o
+
+$(LIB): .depend $(OBJS)
+ $(AR) crv $@ $^
+
+#########################################################################
+
+.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+ $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################
--- /dev/null
+#
+# (C) Copyright 2000
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+# Ulrich Lutz, Speech Design GmbH, ulutz@datalab.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# SPD823TS boards
+#
+
+TEXT_BASE = 0x0C000000
--- /dev/null
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <ppcboot.h>
+#include <mpc8xx.h>
+
+flash_info_t flash_info[CFG_MAX_FLASH_BANKS];
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init (void)
+{
+ /* All Speech Design board memory (DRAM and EPROM) initialisation is
+ done in dram_init().
+ The caller of ths function here expects the total size and will hang,
+ if we give here back 0. So we return the EPROM size. */
+
+ return (1024 * 1024); /* 1 MB */
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+flash_info_t *addr2info (ulong addr)
+{
+ return (NULL);
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash.
+ * Returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ * 4 - target range includes protected sectors
+ * 8 - target address not in Flash memory
+ */
+int flash_write (uchar *src, ulong addr, ulong cnt)
+{
+ return (1); /* any other error codes are possible as well */
+}
+
+void flash_print_info (flash_info_t *info)
+{
+ printf("no FLASH memory in MPC823TS board\n");
+ return;
+}
+
+void flash_erase (flash_info_t *info, int s_first, int s_last)
+{
+ return;
+}
+
+/*-----------------------------------------------------------------------
+ */
--- /dev/null
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+ __DYNAMIC = 0; */
+SECTIONS
+{
+ /* Read-only sections, merged into text segment: */
+ . = + SIZEOF_HEADERS;
+ .interp : { *(.interp) }
+ .hash : { *(.hash) }
+ .dynsym : { *(.dynsym) }
+ .dynstr : { *(.dynstr) }
+ .rel.text : { *(.rel.text) }
+ .rela.text : { *(.rela.text) }
+ .rel.data : { *(.rel.data) }
+ .rela.data : { *(.rela.data) }
+ .rel.rodata : { *(.rel.rodata) }
+ .rela.rodata : { *(.rela.rodata) }
+ .rel.got : { *(.rel.got) }
+ .rela.got : { *(.rela.got) }
+ .rel.ctors : { *(.rel.ctors) }
+ .rela.ctors : { *(.rela.ctors) }
+ .rel.dtors : { *(.rel.dtors) }
+ .rela.dtors : { *(.rela.dtors) }
+ .rel.bss : { *(.rel.bss) }
+ .rela.bss : { *(.rela.bss) }
+ .rel.plt : { *(.rel.plt) }
+ .rela.plt : { *(.rela.plt) }
+ .init : { *(.init) }
+ .plt : { *(.plt) }
+ .text :
+ {
+ mpc8xx/start.o (.text)
+ common/environment.o(.text)
+ *(.text)
+ *(.fixup)
+ *(.got1)
+ }
+ _etext = .;
+ PROVIDE (etext = .);
+ .rodata :
+ {
+ *(.rodata)
+ *(.rodata1)
+ }
+ .fini : { *(.fini) } =0
+ .ctors : { *(.ctors) }
+ .dtors : { *(.dtors) }
+
+ /* Read-write section, merged into data segment: */
+ . = (. + 0x0FF) & 0xFFFFFF00;
+ _erotext = .;
+ PROVIDE (erotext = .);
+ .reloc :
+ {
+ *(.got)
+ _GOT2_TABLE_ = .;
+ *(.got2)
+ _FIXUP_TABLE_ = .;
+ *(.fixup)
+ }
+ __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+ __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+ .data :
+ {
+ *(.data)
+ *(.data1)
+ *(.sdata)
+ *(.sdata2)
+ *(.dynamic)
+ CONSTRUCTORS
+ }
+ _edata = .;
+ PROVIDE (edata = .);
+
+ __start___ex_table = .;
+ __ex_table : { *(__ex_table) }
+ __stop___ex_table = .;
+
+ . = ALIGN(256);
+ __init_begin = .;
+ .text.init : { *(.text.init) }
+ .data.init : { *(.data.init) }
+ . = ALIGN(256);
+ __init_end = .;
+
+ __bss_start = .;
+ .bss :
+ {
+ *(.sbss) *(.scommon)
+ *(.dynbss)
+ *(.bss)
+ *(COMMON)
+ }
+ _end = . ;
+ PROVIDE (end = .);
+}
+
--- /dev/null
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+ __DYNAMIC = 0; */
+SECTIONS
+{
+ /* Read-only sections, merged into text segment: */
+ . = + SIZEOF_HEADERS;
+ .interp : { *(.interp) }
+ .hash : { *(.hash) }
+ .dynsym : { *(.dynsym) }
+ .dynstr : { *(.dynstr) }
+ .rel.text : { *(.rel.text) }
+ .rela.text : { *(.rela.text) }
+ .rel.data : { *(.rel.data) }
+ .rela.data : { *(.rela.data) }
+ .rel.rodata : { *(.rel.rodata) }
+ .rela.rodata : { *(.rela.rodata) }
+ .rel.got : { *(.rel.got) }
+ .rela.got : { *(.rela.got) }
+ .rel.ctors : { *(.rel.ctors) }
+ .rela.ctors : { *(.rela.ctors) }
+ .rel.dtors : { *(.rel.dtors) }
+ .rela.dtors : { *(.rela.dtors) }
+ .rel.bss : { *(.rel.bss) }
+ .rela.bss : { *(.rela.bss) }
+ .rel.plt : { *(.rel.plt) }
+ .rela.plt : { *(.rela.plt) }
+ .init : { *(.init) }
+ .plt : { *(.plt) }
+ .text :
+ {
+ /* WARNING - the following is hand-optimized to fit within */
+ /* the sector layout of our flash chips! XXX FIXME XXX */
+
+ mpc8xx/start.o (.text)
+ common/dlmalloc.o (.text)
+ ppc/vsprintf.o (.text)
+ ppc/crc32.o (.text)
+ ppc/extable.o (.text)
+
+ . = env_offset;
+ common/environment.o(.text)
+
+ *(.text)
+ *(.fixup)
+ *(.got1)
+ }
+ _etext = .;
+ PROVIDE (etext = .);
+ .rodata :
+ {
+ *(.rodata)
+ *(.rodata1)
+ }
+ .fini : { *(.fini) } =0
+ .ctors : { *(.ctors) }
+ .dtors : { *(.dtors) }
+
+ /* Read-write section, merged into data segment: */
+ . = (. + 0x0FFF) & 0xFFFFF000;
+ _erotext = .;
+ PROVIDE (erotext = .);
+ .reloc :
+ {
+ *(.got)
+ _GOT2_TABLE_ = .;
+ *(.got2)
+ _FIXUP_TABLE_ = .;
+ *(.fixup)
+ }
+ __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+ __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+ .data :
+ {
+ *(.data)
+ *(.data1)
+ *(.sdata)
+ *(.sdata2)
+ *(.dynamic)
+ CONSTRUCTORS
+ }
+ _edata = .;
+ PROVIDE (edata = .);
+
+ __start___ex_table = .;
+ __ex_table : { *(__ex_table) }
+ __stop___ex_table = .;
+
+ . = ALIGN(4096);
+ __init_begin = .;
+ .text.init : { *(.text.init) }
+ .data.init : { *(.data.init) }
+ . = ALIGN(4096);
+ __init_end = .;
+
+ __bss_start = .;
+ .bss :
+ {
+ *(.sbss) *(.scommon)
+ *(.dynbss)
+ *(.bss)
+ *(COMMON)
+ }
+ _end = . ;
+ PROVIDE (end = .);
+}
+
--- /dev/null
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ * Ulrich Lutz, Speech Design GmbH, ulutz@datalab.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <ppcboot.h>
+#include <mpc8xx.h>
+#include <commproc.h>
+
+/* ------------------------------------------------------------------------- */
+
+static long int dram_size (long int, long int *, long int);
+
+/* ------------------------------------------------------------------------- */
+
+#define _NOT_USED_ 0xFFFFFFFF
+
+const uint sharc_table[] =
+{
+ /*
+ * Single Read. (Offset 0 in UPM RAM)
+ */
+ 0x0FF3FC04, 0x0FF3EC00, 0x7FFFEC04, 0xFFFFEC04,
+ 0xFFFFEC05, /* last */
+ _NOT_USED_, _NOT_USED_, _NOT_USED_,
+ /*
+ * Burst Read. (Offset 8 in UPM RAM)
+ */
+ /* last */
+ _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+ _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+ _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+ _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+ /*
+ * Single Write. (Offset 18 in UPM RAM)
+ */
+ 0x0FAFFC04, 0x0FAFEC00, 0x7FFFEC04, 0xFFFFEC04,
+ 0xFFFFEC05, /* last */
+ _NOT_USED_, _NOT_USED_, _NOT_USED_,
+ /*
+ * Burst Write. (Offset 20 in UPM RAM)
+ */
+ /* last */
+ _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+ _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+ _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+ _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+ /*
+ * Refresh (Offset 30 in UPM RAM)
+ */
+ /* last */
+ _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+ _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+ _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+ /*
+ * Exception. (Offset 3c in UPM RAM)
+ */
+ 0x7FFFFC07, /* last */
+ _NOT_USED_, _NOT_USED_, _NOT_USED_,
+};
+
+
+const uint sdram_table[] =
+{
+ /*
+ * Single Read. (Offset 0 in UPM RAM)
+ */
+ 0x1F07FC04, 0xEEAEFC04, 0x11ADFC04, 0xEFBBBC00,
+ 0x1FF77C47, /* last */
+ /*
+ * SDRAM Initialization (offset 5 in UPM RAM)
+ *
+ * This is no UPM entry point. The following definition uses
+ * the remaining space to establish an initialization
+ * sequence, which is executed by a RUN command.
+ *
+ */
+ 0x1FF77C35, 0xEFEABC34, 0x1FB57C35, /* last */
+ /*
+ * Burst Read. (Offset 8 in UPM RAM)
+ */
+ 0x1F07FC04, 0xEEAEFC04, 0x10ADFC04, 0xF0AFFC00,
+ 0xF0AFFC00, 0xF1AFFC00, 0xEFBBBC00, 0x1FF77C47, /* last */
+ _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+ _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+ /*
+ * Single Write. (Offset 18 in UPM RAM)
+ */
+ 0x1F27FC04, 0xEEAEBC00, 0x01B93C04, 0x1FF77C47, /* last */
+ _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+ /*
+ * Burst Write. (Offset 20 in UPM RAM)
+ */
+ 0x1F07FC04, 0xEEAEBC00, 0x10AD7C00, 0xF0AFFC00,
+ 0xF0AFFC00, 0xE1BBBC04, 0x1FF77C47, /* last */
+ _NOT_USED_,
+ _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+ _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+ /*
+ * Refresh (Offset 30 in UPM RAM)
+ */
+ 0x1FF5FC84, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04,
+ 0xFFFFFC84, 0xFFFFFC07, /* last */
+ _NOT_USED_, _NOT_USED_,
+ _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+ /*
+ * Exception. (Offset 3c in UPM RAM)
+ */
+ 0x7FFFFC07, /* last */
+ _NOT_USED_, _NOT_USED_, _NOT_USED_,
+};
+
+/* ------------------------------------------------------------------------- */
+
+
+/*
+ * Check Board Identity:
+ *
+ */
+
+int checkboard (void)
+{
+ printf ("MPC823TS\n");
+ return (1);
+}
+
+/* ------------------------------------------------------------------------- */
+
+long int
+initdram (int board_type)
+{
+ volatile immap_t *immap = (immap_t *)CFG_IMMR;
+ volatile memctl8xx_t *memctl = &immap->im_memctl;
+ long int size_b0;
+
+ /* this a ugly hack: DRAM init needs udelay() */
+ /* unlock */
+ immap->im_sitk.sitk_tbk = KAPWR_KEY;
+ /* write value */
+ immap->im_sit.sit_tbscr |= TBSCR_TBE;
+
+ /*
+ * Map controller bank 2 to the SRAM bank at preliminary address.
+ */
+ memctl->memc_or2 = CFG_OR2_PRELIM;
+ memctl->memc_br2 = CFG_BR2_PRELIM;
+
+ /*
+ * Map controller bank 4 to the PER8 bank at preliminary address.
+ */
+ memctl->memc_or4 = CFG_OR4_PRELIM;
+ memctl->memc_br4 = CFG_BR4_PRELIM;
+
+ /* Configure SHARC at UMA */
+ upmconfig(UPMA, (uint *)sharc_table, sizeof(sharc_table)/sizeof(uint));
+ /* Map controller bank 5 to the SHARC */
+ memctl->memc_or5 = CFG_OR5_PRELIM;
+ memctl->memc_br5 = CFG_BR5_PRELIM;
+
+ memctl->memc_mamr = 0x00001000;
+
+ /* Configure SDRAM at UMB */
+ upmconfig(UPMB, (uint *)sdram_table, sizeof(sdram_table)/sizeof(uint));
+
+ memctl->memc_mptpr = CFG_MPTPR_1BK_8K;
+
+ memctl->memc_mar = 0x00000088;
+
+ /*
+ * Map controller bank 3 to the SDRAM bank at preliminary address.
+ */
+ memctl->memc_or3 = CFG_OR3_PRELIM;
+ memctl->memc_br3 = CFG_BR3_PRELIM;
+
+ memctl->memc_mbmr = CFG_MBMR_8COL; /* refresh not enabled yet */
+
+ udelay(200);
+ memctl->memc_mcr = 0x80806105;
+ udelay(1);
+ memctl->memc_mcr = 0x80806130;
+ udelay(1);
+ memctl->memc_mcr = 0x80806130;
+ udelay(1);
+ memctl->memc_mcr = 0x80806106;
+
+ memctl->memc_mbmr |= MAMR_PTBE; /* refresh enabled */
+
+ /*
+ * Check Bank 0 Memory Size for re-configuration
+ */
+ size_b0 = dram_size (CFG_MBMR_8COL, (ulong *)SDRAM_BASE3_PRELIM, SDRAM_MAX_SIZE);
+
+ memctl->memc_mbmr = CFG_MBMR_8COL | MAMR_PTBE;
+
+ return (size_b0);
+}
+
+/* ------------------------------------------------------------------------- */
+
+/*
+ * Check memory range for valid RAM. A simple memory test determines
+ * the actually available RAM size between addresses `base' and
+ * `base + maxsize'. Some (not all) hardware errors are detected:
+ * - short between address lines
+ * - short between data lines
+ */
+
+static long int dram_size (long int mamr_value, long int *base, long int maxsize)
+{
+ volatile immap_t *immap = (immap_t *)CFG_IMMR;
+ volatile memctl8xx_t *memctl = &immap->im_memctl;
+ volatile long int *addr;
+ long int cnt, val;
+
+ memctl->memc_mbmr = mamr_value;
+
+ for (cnt = maxsize/sizeof(long); cnt > 0; cnt >>= 1) {
+ addr = base + cnt; /* pointer arith! */
+
+ *addr = ~cnt;
+ }
+
+ /* write 0 to base address */
+ addr = base;
+ *addr = 0;
+
+ /* check at base address */
+ if ((val = *addr) != 0) {
+ return (0);
+ }
+
+ for (cnt = 1; ; cnt <<= 1) {
+ addr = base + cnt; /* pointer arith! */
+
+ val = *addr;
+
+ if (val != (~cnt)) {
+ return (cnt * sizeof(long));
+ }
+ }
+ /* NOTREACHED */
+}
+
+/* ------------------------------------------------------------------------- */
+
+void reset_phy()
+{
+ immap_t *immr = (immap_t *)CFG_IMMR;
+ ushort sreg;
+
+ /* Configure extra port pins for NS DP83843 PHY */
+ immr->im_ioport.iop_papar &= ~(PA_ENET_MDC | PA_ENET_MDIO);
+
+ sreg = immr->im_ioport.iop_padir;
+ sreg |= PA_ENET_MDC; /* Mgmt. Data Clock is Output */
+ sreg &= ~(PA_ENET_MDIO); /* Mgmt. Data I/O is bidirect. => Input */
+ immr->im_ioport.iop_padir = sreg;
+
+ immr->im_ioport.iop_padat &= ~(PA_ENET_MDC); /* set MDC = 0 */
+
+ /*
+ * RESET in implemented by a positive pule of at least 1 us
+ * at the reset pin.
+ *
+ * Configure RESET pins for NS DP83843 PHY, and RESET chip.
+ *
+ * Note: The RESET pin is high active, but there is an
+ * inverter on the SPD823TS board...
+ */
+ immr->im_ioport.iop_pcpar &= ~(PC_ENET_RESET);
+ immr->im_ioport.iop_pcdir |= PC_ENET_RESET;
+ /* assert RESET signal of PHY */
+ immr->im_ioport.iop_pcdat &= ~(PC_ENET_RESET);
+ udelay (10);
+ /* de-assert RESET signal of PHY */
+ immr->im_ioport.iop_pcdat |= PC_ENET_RESET;
+ udelay (10);
+}
projects / users / rw / ppcboot.git / commitdiff