drm/i915/dsb: Evade transcoder undelayed vblank when using DSB

We want to start the DSB execution from the transcoder's undelayed
vblank, so in order to guarantee atomicity with the all the other
mmio register writes we need to evade both vblanks.

Note that currently we don't add any vblank delay, so this is
effectively a nop. But in the future when we start to program
double buffered registers from the DSB we'll need to delay the
pipe's vblank to provide the register programming "window2"
for the DSB.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20230606191504.18099-15-ville.syrjala@linux.intel.com
Reviewed-by: Uma Shankar <uma.shankar@intel.com>

diff --git a/drivers/gpu/drm/i915/display/intel_crtc.c b/drivers/gpu/drm/i915/display/intel_crtc.c
index 492347bd0e9dab6daea9df598ac8390ae2c065b5..e233ec9d1ba83fdab9e4f1abd39a11748ddff97f 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_crtc.c
+++ b/drivers/gpu/drm/i915/display/intel_crtc.c
@@ -516,8 +516,11 @@ static void intel_crtc_vblank_evade_scanlines(struct intel_atomic_state *state,
         * M/N and TRANS_VTOTAL are double buffered on the transcoder's
         * undelayed vblank, so with seamless M/N and LRR we must evade
         * both vblanks.
+        *
+        * DSB execution waits for the transcoder's undelayed vblank,
+        * hence we must kick off the commit before that.
         */
-       if (new_crtc_state->update_m_n || new_crtc_state->update_lrr)
+       if (new_crtc_state->dsb || new_crtc_state->update_m_n || new_crtc_state->update_lrr)
                *min -= adjusted_mode->crtc_vblank_start - adjusted_mode->crtc_vdisplay;
 }