u32 cpu_disp_imr_set;
        u32 other_disp_imr_clr;
        u32 other_disp_imr_set;
+       u32 bbrpt_com_err_imr_reg;
        u32 bbrpt_chinfo_err_imr_reg;
        u32 bbrpt_err_imr_set;
        u32 bbrpt_dfs_err_imr_reg;
 
 {
        const struct rtw89_imr_info *imr = rtwdev->chip->imr_info;
 
-       rtw89_write32_set(rtwdev, R_AX_BBRPT_COM_ERR_IMR,
+       rtw89_write32_set(rtwdev, imr->bbrpt_com_err_imr_reg,
                          B_AX_BBRPT_COM_NULL_PLPKTID_ERR_INT_EN);
        rtw89_write32_clr(rtwdev, imr->bbrpt_chinfo_err_imr_reg,
                          B_AX_BBRPT_CHINFO_IMR_CLR);
 
 #define B_AX_F2PCMDRPT_FULL_DROP_ERR_INT_EN BIT(8)
 #define B_AX_FSM1_TIMEOUT_ERR_INT_EN BIT(1)
 #define B_AX_FSM_TIMEOUT_ERR_INT_EN BIT(0)
+#define B_AX_PTCL_IMR_CLR_ALL GENMASK(31, 0)
 #define B_AX_PTCL_IMR_CLR (B_AX_FSM_TIMEOUT_ERR_INT_EN | \
                           B_AX_F2PCMDRPT_FULL_DROP_ERR_INT_EN | \
                           B_AX_TXPRT_FULL_DROP_ERR_INT_EN | \
 
        .cpu_disp_imr_set       = B_AX_CPU_DISP_IMR_SET,
        .other_disp_imr_clr     = B_AX_OTHER_DISP_IMR_CLR,
        .other_disp_imr_set     = 0,
+       .bbrpt_com_err_imr_reg  = R_AX_BBRPT_COM_ERR_IMR_ISR,
        .bbrpt_chinfo_err_imr_reg = R_AX_BBRPT_CHINFO_ERR_IMR_ISR,
        .bbrpt_err_imr_set      = 0,
        .bbrpt_dfs_err_imr_reg  = R_AX_BBRPT_DFS_ERR_IMR_ISR,
 
        .cpu_disp_imr_set       = B_AX_CPU_DISP_IMR_SET_V1,
        .other_disp_imr_clr     = B_AX_OTHER_DISP_IMR_CLR_V1,
        .other_disp_imr_set     = B_AX_OTHER_DISP_IMR_SET_V1,
+       .bbrpt_com_err_imr_reg  = R_AX_BBRPT_COM_ERR_IMR,
        .bbrpt_chinfo_err_imr_reg = R_AX_BBRPT_CHINFO_ERR_IMR,
        .bbrpt_err_imr_set      = R_AX_BBRPT_CHINFO_IMR_SET_V1,
        .bbrpt_dfs_err_imr_reg  = R_AX_BBRPT_DFS_ERR_IMR,