PCI: apple: Fix REFCLK1 enable/poll logic

REFCLK1 has req/ack bits that need to be programmed, just like REFCLK0.

Link: https://lore.kernel.org/r/20211117140044.193865-1-marcan@marcan.st
Fixes: 1e33888fbe44 ("PCI: apple: Add initial hardware bring-up")
Signed-off-by: Hector Martin <marcan@marcan.st>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Acked-by: Marc Zyngier <maz@kernel.org>

diff --git a/drivers/pci/controller/pcie-apple.c b/drivers/pci/controller/pcie-apple.c
index fa5e9c31d80b9c285b6080601bb1d75d342a4f8a..f98551336b423c882c8ffd5562a4dd692e0b172d 100644 (file)
--- a/drivers/pci/controller/pcie-apple.c
+++ b/drivers/pci/controller/pcie-apple.c
@@ -42,8 +42,9 @@
 #define   CORE_FABRIC_STAT_MASK                0x001F001F
 #define CORE_LANE_CFG(port)            (0x84000 + 0x4000 * (port))
 #define   CORE_LANE_CFG_REFCLK0REQ     BIT(0)
-#define   CORE_LANE_CFG_REFCLK1                BIT(1)
+#define   CORE_LANE_CFG_REFCLK1REQ     BIT(1)
 #define   CORE_LANE_CFG_REFCLK0ACK     BIT(2)
+#define   CORE_LANE_CFG_REFCLK1ACK     BIT(3)
 #define   CORE_LANE_CFG_REFCLKEN       (BIT(9) | BIT(10))
 #define CORE_LANE_CTL(port)            (0x84004 + 0x4000 * (port))
 #define   CORE_LANE_CTL_CFGACC         BIT(15)
@@ -482,9 +483,9 @@ static int apple_pcie_setup_refclk(struct apple_pcie *pcie,
        if (res < 0)
                return res;
 
-       rmw_set(CORE_LANE_CFG_REFCLK1, pcie->base + CORE_LANE_CFG(port->idx));
+       rmw_set(CORE_LANE_CFG_REFCLK1REQ, pcie->base + CORE_LANE_CFG(port->idx));
        res = readl_relaxed_poll_timeout(pcie->base + CORE_LANE_CFG(port->idx),
-                                        stat, stat & CORE_LANE_CFG_REFCLK1,
+                                        stat, stat & CORE_LANE_CFG_REFCLK1ACK,
                                         100, 50000);
 
        if (res < 0)