phy_err(phy, "Timeout waiting for stop state\n");
 }
 
+static void cal_camerarx_enable_irqs(struct cal_camerarx *phy)
+{
+       const u32 cio_err_mask =
+               CAL_CSI2_COMPLEXIO_IRQ_LANE_ERRORS_MASK |
+               CAL_CSI2_COMPLEXIO_IRQ_FIFO_OVR_MASK |
+               CAL_CSI2_COMPLEXIO_IRQ_SHORT_PACKET_MASK |
+               CAL_CSI2_COMPLEXIO_IRQ_ECC_NO_CORRECTION_MASK;
+
+       /* Enable CIO error IRQs. */
+       cal_write(phy->cal, CAL_HL_IRQENABLE_SET(0),
+                 CAL_HL_IRQ_CIO_MASK(phy->instance));
+       cal_write(phy->cal, CAL_CSI2_COMPLEXIO_IRQENABLE(phy->instance),
+                 cio_err_mask);
+}
+
+static void cal_camerarx_disable_irqs(struct cal_camerarx *phy)
+{
+       /* Disable CIO error irqs */
+       cal_write(phy->cal, CAL_HL_IRQENABLE_CLR(0),
+                 CAL_HL_IRQ_CIO_MASK(phy->instance));
+       cal_write(phy->cal, CAL_CSI2_COMPLEXIO_IRQENABLE(phy->instance), 0);
+}
+
 static int cal_camerarx_start(struct cal_camerarx *phy)
 {
        s64 external_rate;
                return ret;
        }
 
+       cal_camerarx_enable_irqs(phy);
+
        /*
         * CSI-2 PHY Link Initialization Sequence, according to the DRA74xP /
         * DRA75xP / DRA76xP / DRA77xP TRM. The DRA71x / DRA72x and the AM65x /
        ret = v4l2_subdev_call(phy->sensor, video, s_stream, 1);
        if (ret) {
                v4l2_subdev_call(phy->sensor, core, s_power, 0);
+               cal_camerarx_disable_irqs(phy);
                phy_err(phy, "stream on failed in subdev\n");
                return ret;
        }
        unsigned int i;
        int ret;
 
+       cal_camerarx_disable_irqs(phy);
+
        cal_camerarx_power(phy, false);
 
        /* Assert Complex IO Reset */
        camerarx_write(phy, CAL_CSI2_PHY_REG10, reg10);
 }
 
-/*
- * Enable the expected IRQ sources
- */
-void cal_camerarx_enable_irqs(struct cal_camerarx *phy)
-{
-       u32 val;
-
-       const u32 cio_err_mask =
-               CAL_CSI2_COMPLEXIO_IRQ_LANE_ERRORS_MASK |
-               CAL_CSI2_COMPLEXIO_IRQ_FIFO_OVR_MASK |
-               CAL_CSI2_COMPLEXIO_IRQ_SHORT_PACKET_MASK |
-               CAL_CSI2_COMPLEXIO_IRQ_ECC_NO_CORRECTION_MASK;
-
-       /* Enable CIO error irqs */
-       cal_write(phy->cal, CAL_HL_IRQENABLE_SET(0),
-                 CAL_HL_IRQ_CIO_MASK(phy->instance));
-       cal_write(phy->cal, CAL_CSI2_COMPLEXIO_IRQENABLE(phy->instance),
-                 cio_err_mask);
-
-       /* Always enable OCPO error */
-       cal_write(phy->cal, CAL_HL_IRQENABLE_SET(0), CAL_HL_IRQ_OCPO_ERR_MASK);
-
-       /* Enable IRQ_WDMA_END 0/1 */
-       val = 0;
-       cal_set_field(&val, 1, CAL_HL_IRQ_MASK(phy->instance));
-       cal_write(phy->cal, CAL_HL_IRQENABLE_SET(1), val);
-       /* Enable IRQ_WDMA_START 0/1 */
-       val = 0;
-       cal_set_field(&val, 1, CAL_HL_IRQ_MASK(phy->instance));
-       cal_write(phy->cal, CAL_HL_IRQENABLE_SET(2), val);
-       /* Todo: Add VC_IRQ and CSI2_COMPLEXIO_IRQ handling */
-       cal_write(phy->cal, CAL_CSI2_VC_IRQENABLE(0), 0xFF000000);
-}
-
-void cal_camerarx_disable_irqs(struct cal_camerarx *phy)
-{
-       u32 val;
-
-       /* Disable CIO error irqs */
-       cal_write(phy->cal, CAL_HL_IRQENABLE_CLR(0),
-                 CAL_HL_IRQ_CIO_MASK(phy->instance));
-       cal_write(phy->cal, CAL_CSI2_COMPLEXIO_IRQENABLE(phy->instance), 0);
-
-       /* Disable IRQ_WDMA_END 0/1 */
-       val = 0;
-       cal_set_field(&val, 1, CAL_HL_IRQ_MASK(phy->instance));
-       cal_write(phy->cal, CAL_HL_IRQENABLE_CLR(1), val);
-       /* Disable IRQ_WDMA_START 0/1 */
-       val = 0;
-       cal_set_field(&val, 1, CAL_HL_IRQ_MASK(phy->instance));
-       cal_write(phy->cal, CAL_HL_IRQENABLE_CLR(2), val);
-       /* Todo: Add VC_IRQ and CSI2_COMPLEXIO_IRQ handling */
-       cal_write(phy->cal, CAL_CSI2_VC_IRQENABLE(0), 0);
-}
-
 void cal_camerarx_ppi_enable(struct cal_camerarx *phy)
 {
        cal_write(phy->cal, CAL_CSI2_PPI_CTRL(phy->instance),
 
        cal_write(ctx->cal, CAL_WR_DMA_ADDR(ctx->index), dmaaddr);
 }
 
+void cal_ctx_enable_irqs(struct cal_ctx *ctx)
+{
+       /* Enable IRQ_WDMA_END and IRQ_WDMA_START. */
+       cal_write(ctx->cal, CAL_HL_IRQENABLE_SET(1),
+                 CAL_HL_IRQ_MASK(ctx->index));
+       cal_write(ctx->cal, CAL_HL_IRQENABLE_SET(2),
+                 CAL_HL_IRQ_MASK(ctx->index));
+}
+
+void cal_ctx_disable_irqs(struct cal_ctx *ctx)
+{
+       /* Disable IRQ_WDMA_END and IRQ_WDMA_START. */
+       cal_write(ctx->cal, CAL_HL_IRQENABLE_CLR(1),
+                 CAL_HL_IRQ_MASK(ctx->index));
+       cal_write(ctx->cal, CAL_HL_IRQENABLE_CLR(2),
+                 CAL_HL_IRQ_MASK(ctx->index));
+}
+
 /* ------------------------------------------------------------------
  *     IRQ Handling
  * ------------------------------------------------------------------
                        cal_camerarx_i913_errata(cal->phy[i]);
        }
 
+       /*
+        * Enable global interrupts that are not related to a particular
+        * CAMERARAX or context.
+        */
+       cal_write(cal, CAL_HL_IRQENABLE_SET(0), CAL_HL_IRQ_OCPO_ERR_MASK);
+
        return 0;
 }