{
        struct vme_dma_resource *ctrlr;
        struct ca91cx42_dma_entry *entry;
-       int retval = 0;
+       int retval;
        dma_addr_t bus_addr;
        u32 val;
        struct device *dev;
 
        iowrite32(val, bridge->base + DGCS);
 
-       wait_event_interruptible(bridge->dma_queue,
-               ca91cx42_dma_busy(ctrlr->parent));
+       retval = wait_event_interruptible(bridge->dma_queue,
+                                         ca91cx42_dma_busy(ctrlr->parent));
+
+       if (retval) {
+               val = ioread32(bridge->base + DGCS);
+               iowrite32(val | CA91CX42_DGCS_STOP_REQ, bridge->base + DGCS);
+               /* Wait for the operation to abort */
+               wait_event(bridge->dma_queue,
+                          ca91cx42_dma_busy(ctrlr->parent));
+               retval = -EINTR;
+               goto exit;
+       }
 
        /*
         * Read status register, this register is valid until we kick off a
                val = ioread32(bridge->base + DCTL);
        }
 
+exit:
        /* Remove list from running list */
        mutex_lock(&ctrlr->mtx);
        list_del(&list->list);
 
 static int tsi148_dma_list_exec(struct vme_dma_list *list)
 {
        struct vme_dma_resource *ctrlr;
-       int channel, retval = 0;
+       int channel, retval;
        struct tsi148_dma_entry *entry;
        u32 bus_addr_high, bus_addr_low;
        u32 val, dctlreg = 0;
        iowrite32be(dctlreg | TSI148_LCSR_DCTL_DGO, bridge->base +
                TSI148_LCSR_DMA[channel] + TSI148_LCSR_OFFSET_DCTL);
 
-       wait_event_interruptible(bridge->dma_queue[channel],
+       retval = wait_event_interruptible(bridge->dma_queue[channel],
                tsi148_dma_busy(ctrlr->parent, channel));
 
+       if (retval) {
+               iowrite32be(dctlreg | TSI148_LCSR_DCTL_ABT, bridge->base +
+                       TSI148_LCSR_DMA[channel] + TSI148_LCSR_OFFSET_DCTL);
+               /* Wait for the operation to abort */
+               wait_event(bridge->dma_queue[channel],
+                          tsi148_dma_busy(ctrlr->parent, channel));
+               retval = -EINTR;
+               goto exit;
+       }
+
        /*
         * Read status register, this register is valid until we kick off a
         * new transfer.
                retval = -EIO;
        }
 
+exit:
        /* Remove list from running list */
        mutex_lock(&ctrlr->mtx);
        list_del(&list->list);