arm64: dts: qcom: ipq9574: Add CMN PLL node

The CMN PLL clock controller allows selection of an input clock rate
from a defined set of input clock rates. It in-turn supplies fixed
rate output clocks to the hardware blocks that provide the ethernet
functions such as PPE (Packet Process Engine) and connected switch or
PHY, and to GCC.

The reference clock of CMN PLL is routed from XO to the CMN PLL through
the internal WiFi block.
.XO (48 MHZ or 96 MHZ)-->WiFi (multiplier/divider)-->48 MHZ to CMN PLL.

The reference input clock from WiFi to CMN PLL is fully controlled by
the bootstrap pins which select the XO frequency (48 MHZ or 96 MHZ).
Based on this frequency, the divider in the internal Wi-Fi block is
automatically configured by hardware (1 for 48 MHZ, 2 for 96 MHZ), to
ensure output clock to CMN PLL is 48 MHZ.

Signed-off-by: Luo Jie <quic_luoj@quicinc.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20250103-qcom_ipq_cmnpll-v8-4-c89fb4d4849d@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

diff --git a/arch/arm64/boot/dts/qcom/ipq9574-rdp-common.dtsi b/arch/arm64/boot/dts/qcom/ipq9574-rdp-common.dtsi
index 91e104b0f86534ce02349c7b69b36f4c5e602c6d..bb1ff79360d3483ac779642880b18339acdde167 100644 (file)
--- a/arch/arm64/boot/dts/qcom/ipq9574-rdp-common.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq9574-rdp-common.dtsi
@@ -3,7 +3,7 @@
  * IPQ9574 RDP board common device tree source
  *
  * Copyright (c) 2020-2021 The Linux Foundation. All rights reserved.
- * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
+ * Copyright (c) 2023-2024, Qualcomm Innovation Center, Inc. All rights reserved.
  */
 
 /dts-v1/;
@@ -164,6 +164,21 @@
        status = "okay";
 };
 
+/*
+ * The bootstrap pins for the board select the XO clock frequency
+ * (48 MHZ or 96 MHZ used for different RDP type board). This setting
+ * automatically enables the right dividers, to ensure the reference
+ * clock output from WiFi to the CMN PLL is 48 MHZ.
+ */
+&ref_48mhz_clk {
+       clock-div = <1>;
+       clock-mult = <1>;
+};
+
 &xo_board_clk {
        clock-frequency = <24000000>;
 };
+
+&xo_clk {
+       clock-frequency = <48000000>;
+};

diff --git a/arch/arm64/boot/dts/qcom/ipq9574.dtsi b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
index 00ee3290c1812272a5e27e0ab94ce16c8d2eb84d..c543c3492e931ffd2ff1424881db7d8c035159d8 100644 (file)
--- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
@@ -3,10 +3,11 @@
  * IPQ9574 SoC device tree source
  *
  * Copyright (c) 2020-2021 The Linux Foundation. All rights reserved.
- * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
+ * Copyright (c) 2023-2024, Qualcomm Innovation Center, Inc. All rights reserved.
  */
 
 #include <dt-bindings/clock/qcom,apss-ipq.h>
+#include <dt-bindings/clock/qcom,ipq-cmn-pll.h>
 #include <dt-bindings/clock/qcom,ipq9574-gcc.h>
 #include <dt-bindings/interconnect/qcom,ipq9574.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
@@ -19,6 +20,12 @@
        #size-cells = <2>;
 
        clocks {
+               ref_48mhz_clk: ref-48mhz-clk {
+                       compatible = "fixed-factor-clock";
+                       clocks = <&xo_clk>;
+                       #clock-cells = <0>;
+               };
+
                sleep_clk: sleep-clk {
                        compatible = "fixed-clock";
                        #clock-cells = <0>;
@@ -28,6 +35,11 @@
                        compatible = "fixed-clock";
                        #clock-cells = <0>;
                };
+
+               xo_clk: xo-clk {
+                       compatible = "fixed-clock";
+                       #clock-cells = <0>;
+               };
        };
 
        cpus {
@@ -335,6 +347,18 @@
                        status = "disabled";
                };
 
+               cmn_pll: clock-controller@9b000 {
+                       compatible = "qcom,ipq9574-cmn-pll";
+                       reg = <0x0009b000 0x800>;
+                       clocks = <&ref_48mhz_clk>,
+                                <&gcc GCC_CMN_12GPLL_AHB_CLK>,
+                                <&gcc GCC_CMN_12GPLL_SYS_CLK>;
+                       clock-names = "ref", "ahb", "sys";
+                       #clock-cells = <1>;
+                       assigned-clocks = <&cmn_pll CMN_PLL_CLK>;
+                       assigned-clock-rates-u64 = /bits/ 64 <12000000000>;
+               };
+
                qfprom: efuse@a4000 {
                        compatible = "qcom,ipq9574-qfprom", "qcom,qfprom";
                        reg = <0x000a4000 0x5a1>;