======================================================================
Modifications since 1.2.0:
======================================================================
+
+* Misc fixes for xscale boards
+
+* Patch by Robert Schwebel, 8 Oct 2002:
+ Add initial support for csb226 board
+
+* Add second "password" (bootdelaykey2 / bootstopkey2)
+
* Make RAMDisk images work on SMDK2400 / TRAB boards.
* Patch by Pantelis Antoniou, 07 Oct 2002:
E: arsenio@tin.it
D: FADS823 configuration, MPC823 video support, I2C, wireless keyboard, lots more
+N: Robert Schwebel
+E: r.schwebel@pengutronix.de
+D: Support for csb226 board (xscale)
N: Rob Taylor
E: robt@flyingpig.com
D: Port to MBX860T and Sandpoint8240
shannon SA1100
+Robert Schwebel <r.schwebel@pengutronix.de>
+
+ csb226 xscale
+
Alex Züpke <azu@sysgo.de>
lart SA1100
LIST_ARM9="smdk2400 smdk2410 trab"
+#########################################################################
+## Xscale Systems
+#########################################################################
+
+LIST_xscale="lubbock cradle csb226"
+
+
LIST_arm="${LIST_SA} ${LIST_ARM7} ${LIST_ARM9}"
for arg in $@
do
case "$arg" in
- 8xx|824x|8260|4xx|7xx|74xx|SA|ARM7|ARM9|ppc|arm)
+ 8xx|824x|8260|4xx|7xx|74xx|SA|ARM7|ARM9|ppc|arm|xscale)
for target in `eval echo '$LIST_'${arg}`
do
build_target ${target}
lubbock_config : unconfig
@./mkconfig $(@:_config=) arm xscale lubbock
-+cradle_config : unconfig
+cradle_config : unconfig
@./mkconfig $(@:_config=) arm xscale cradle
+csb226_config : unconfig
+ @./mkconfig $(@:_config=) arm xscale csb226
+
#########################################################################
clean:
Configuration depends on the combination of board and CPU type; all
such information is kept in a configuration file
-"include/config_<board_name>.h".
-
+"include/configs/<board_name>.h".
+
Example: For a TQM823L module, all configuration settings are in
-"include/config_TQM823L.h".
+"include/configs/TQM823L.h".
The following options need to be configured:
- CPU Type: Define exactly one of
+
+ PowerPC based CPUs:
+ -------------------
CONFIG_MPC823, CONFIG_MPC850, CONFIG_MPC855, CONFIG_MPC860
or CONFIG_MPC824X, CONFIG_MPC8260
or CONFIG_IOP480
or CONFIG_440
or CONFIG_MPC74xx
+ ARM based CPUs:
+ ---------------
+ CONFIG_SA1110
+ CONFIG_ARM7
+ CONFIG_PXA250
+
+
- Board Type: Define exactly one of
+ PowerPC based boards:
+ ---------------------
+
CONFIG_ADCIOP, CONFIG_ICU862 CONFIG_RPXsuper,
CONFIG_ADS860, CONFIG_IP860, CONFIG_SM850,
CONFIG_AMX860, CONFIG_IPHASE4539, CONFIG_SPD823TS,
CONFIG_IAD210, CONFIG_RPXlite, CONFIG_sbc8260,
CONFIG_EBONY, CONFIG_sacsng
+ ARM based boards:
+ -----------------
+
+ CONFIG_HHP_CRADLE, CONFIG_DNP1110, CONFIG_EP7312,
+ CONFIG_IMPA7, CONFIG_LART, CONFIG_LUBBOCK,
+ CONFIG_SHANNON, CONFIG_SMDK2400, CONFIG_SMDK2410,
+ CONFIG_TRAB
+
- CPU Module Type: (if CONFIG_COGENT is defined)
Define exactly one of
CONFIG_AUTOBOOT_PROMPT
CONFIG_AUTOBOOT_DELAY_STR
CONFIG_AUTOBOOT_STOP_STR
+ CONFIG_AUTOBOOT_DELAY_STR2
+ CONFIG_AUTOBOOT_STOP_STR2
CONFIG_ZERO_BOOTDELAY_CHECK
CONFIG_RESET_TO_RETRY
System Initialization:
----------------------
-In the reset configuration, PPCBoot starts at address 0x00000100.
-Because of the reset configuration for CS0# this is a mirror of the
-onboard Flash memory. To be able to re-map memory PPCBoot then jumps
-to it's link address. To be able to implement the initialization code
-in C, a (small!) initial stack is set up in the internal Dual Ported
-RAM of the MPC8xx. After that, PPCBoot initialises the CPU core, the
-caches and the SIU.
+In the reset configuration, PPCBoot starts at the reset entry point
+(on most PowerPC systens at address 0x00000100). Because of the reset
+configuration for CS0# this is a mirror of the onboard Flash memory.
+To be able to re-map memory PPCBoot then jumps to it's link address.
+To be able to implement the initialization code in C, a (small!)
+initial stack is set up in the internal Dual Ported RAM (in case CPUs
+which provide such a feature like MPC8xx or MPC8260), or in a locked
+part of the data cache. After that, PPCBoot initializes the CPU core,
+the caches and the SIU.
Next, all (potentially) available memory banks are mapped using a
-prelimonary mapping, which puts them on 512 MB boundaries (multiples
-of 0x20000000: SDRAM on 0x00000000 and 0x20000000, Flash on
-0x40000000 and 0x60000000, SRAM on 0x80000000). Then UPM A is
+preliminary mapping. For example, we put them on 512 MB boundaries
+(multiples of 0x20000000: SDRAM on 0x00000000 and 0x20000000, Flash
+on 0x40000000 and 0x60000000, SRAM on 0x80000000). Then UPM A is
programmed for SDRAM access. Using the temporary configuration, a
simple memory test is run that determines the size of the SDRAM
banks.
/* local prototypes */
-void set_led(int led, int color);
-void error_code_halt(int code);
-int init_sio(int led, unsigned long base);
-inline void cradle_outb(unsigned short val, unsigned long base, unsigned long reg);
-inline unsigned char cradle_inb(unsigned long base, unsigned long reg);
-inline void sleep(int i);
+void set_led (int led, int color);
+void error_code_halt (int code);
+int init_sio (int led, unsigned long base);
+inline void cradle_outb (unsigned short val, unsigned long base,
+ unsigned long reg);
+inline unsigned char cradle_inb (unsigned long base, unsigned long reg);
+inline void sleep (int i);
inline void
/**********************************************************/
-sleep(int i)
+sleep (int i)
/**********************************************************/
{
- while (i--)
- {
- udelay(1000000);
- }
+ while (i--) {
+ udelay (1000000);
+ }
}
void
/**********************************************************/
-error_code_halt(int code)
+error_code_halt (int code)
/**********************************************************/
{
- while (1)
- {
- led_code(code, RED);
- sleep(1);
- led_code(0, OFF);
- sleep(1);
- }
+ while (1) {
+ led_code (code, RED);
+ sleep (1);
+ led_code (0, OFF);
+ sleep (1);
+ }
}
void
/**********************************************************/
-led_code(int code, int color)
+led_code (int code, int color)
/**********************************************************/
{
- int i;
-
- code &= 0xf; /* only 4 leds */
-
- for (i = 0; i < 4; i++)
- {
- if (code & (1 << i))
- {
- set_led(i, color);
- }
- else
- {
- set_led(i, OFF);
- }
- }
+ int i;
+
+ code &= 0xf; /* only 4 leds */
+
+ for (i = 0; i < 4; i++) {
+ if (code & (1 << i)) {
+ set_led (i, color);
+ } else {
+ set_led (i, OFF);
+ }
+ }
}
void
/**********************************************************/
-set_led(int led, int color)
+set_led (int led, int color)
/**********************************************************/
{
- int shift = led * 2;
- unsigned long mask = 0x3 << shift;
+ int shift = led * 2;
+ unsigned long mask = 0x3 << shift;
- CRADLE_LED_CLR_REG = mask; /* clear bits */
- CRADLE_LED_SET_REG = (color << shift); /* set bits */
- udelay(5000);
+ CRADLE_LED_CLR_REG = mask; /* clear bits */
+ CRADLE_LED_SET_REG = (color << shift); /* set bits */
+ udelay (5000);
}
inline void
/**********************************************************/
-cradle_outb(unsigned short val, unsigned long base, unsigned long reg)
+cradle_outb (unsigned short val, unsigned long base, unsigned long reg)
/**********************************************************/
{
- *(volatile unsigned short *)(base + (reg*2)) = val;
+ *(volatile unsigned short *) (base + (reg * 2)) = val;
}
inline unsigned char
/**********************************************************/
-cradle_inb(unsigned long base, unsigned long reg)
+cradle_inb (unsigned long base, unsigned long reg)
/**********************************************************/
{
- unsigned short val;
+ unsigned short val;
- val = *(volatile unsigned short *)(base + (reg*2));
- return (val & 0xff);
+ val = *(volatile unsigned short *) (base + (reg * 2));
+ return (val & 0xff);
}
int
/**********************************************************/
-init_sio(int led, unsigned long base)
+init_sio (int led, unsigned long base)
/**********************************************************/
{
- unsigned char val;
-
- set_led(led, YELLOW);
- val = cradle_inb(base, CRADLE_SIO_INDEX);
- val = cradle_inb(base, CRADLE_SIO_INDEX);
- if (val != 0)
- {
- set_led(led, RED);
- return -1;
- }
-
- /* map SCC2 to COM1 */
- cradle_outb(0x01, base, CRADLE_SIO_INDEX);
- cradle_outb(0x00, base, CRADLE_SIO_DATA);
-
- /* enable SCC2 extended regs */
- cradle_outb(0x40, base, CRADLE_SIO_INDEX);
- cradle_outb(0xa0, base, CRADLE_SIO_DATA);
-
- /* enable SCC2 clock multiplier */
- cradle_outb(0x51, base, CRADLE_SIO_INDEX);
- cradle_outb(0x04, base, CRADLE_SIO_DATA);
-
- /* enable SCC2 */
- cradle_outb(0x00, base, CRADLE_SIO_INDEX);
- cradle_outb(0x04, base, CRADLE_SIO_DATA);
-
- /* map SCC2 DMA to channel 0 */
- cradle_outb(0x4f, base, CRADLE_SIO_INDEX);
- cradle_outb(0x09, base, CRADLE_SIO_DATA);
-
- /* read ID from SIO to check operation */
- cradle_outb(0xe4, base, 0x3f8+0x3);
- val = cradle_inb(base, 0x3f8+0x0);
- if ((val & 0xf0) != 0x20)
- {
- set_led(led, RED);
- /* disable SCC2 */
- cradle_outb(0, base, CRADLE_SIO_INDEX);
- cradle_outb(0, base, CRADLE_SIO_DATA);
- return -1;
- }
- /* set back to bank 0 */
- cradle_outb(0, base, 0x3f8+0x3);
- set_led(led, GREEN);
- return 0;
+ unsigned char val;
+
+ set_led (led, YELLOW);
+ val = cradle_inb (base, CRADLE_SIO_INDEX);
+ val = cradle_inb (base, CRADLE_SIO_INDEX);
+ if (val != 0) {
+ set_led (led, RED);
+ return -1;
+ }
+
+ /* map SCC2 to COM1 */
+ cradle_outb (0x01, base, CRADLE_SIO_INDEX);
+ cradle_outb (0x00, base, CRADLE_SIO_DATA);
+
+ /* enable SCC2 extended regs */
+ cradle_outb (0x40, base, CRADLE_SIO_INDEX);
+ cradle_outb (0xa0, base, CRADLE_SIO_DATA);
+
+ /* enable SCC2 clock multiplier */
+ cradle_outb (0x51, base, CRADLE_SIO_INDEX);
+ cradle_outb (0x04, base, CRADLE_SIO_DATA);
+
+ /* enable SCC2 */
+ cradle_outb (0x00, base, CRADLE_SIO_INDEX);
+ cradle_outb (0x04, base, CRADLE_SIO_DATA);
+
+ /* map SCC2 DMA to channel 0 */
+ cradle_outb (0x4f, base, CRADLE_SIO_INDEX);
+ cradle_outb (0x09, base, CRADLE_SIO_DATA);
+
+ /* read ID from SIO to check operation */
+ cradle_outb (0xe4, base, 0x3f8 + 0x3);
+ val = cradle_inb (base, 0x3f8 + 0x0);
+ if ((val & 0xf0) != 0x20) {
+ set_led (led, RED);
+ /* disable SCC2 */
+ cradle_outb (0, base, CRADLE_SIO_INDEX);
+ cradle_outb (0, base, CRADLE_SIO_DATA);
+ return -1;
+ }
+ /* set back to bank 0 */
+ cradle_outb (0, base, 0x3f8 + 0x3);
+ set_led (led, GREEN);
+ return 0;
}
/*
int
/**********************************************************/
-board_post_init(bd_t *bd)
+board_post_init (void)
/**********************************************************/
{
+ return (0);
}
int
/**********************************************************/
-board_init(bd_t *bd)
+board_init (void)
/**********************************************************/
{
- led_code(0xf, YELLOW);
+ DECLARE_GLOBAL_DATA_PTR;
+
+ led_code (0xf, YELLOW);
- /* arch number of HHP Cradle */
- bd->bi_arch_number = 174;
+ /* arch number of HHP Cradle */
+ gd->bd->bi_arch_number = 174;
- /* adress of boot parameters */
- bd->bi_boot_params = 0xa0000100;
+ /* adress of boot parameters */
+ gd->bd->bi_boot_params = 0xa0000100;
- /* Init SIOs to enable SCC2 */
- udelay(100000); // delay makes it look neat
- init_sio(0, CRADLE_SIO1_PHYS);
- udelay(100000);
- init_sio(1, CRADLE_SIO2_PHYS);
- udelay(100000);
- init_sio(2, CRADLE_SIO3_PHYS);
- udelay(100000);
- set_led(3, GREEN);
+ /* Init SIOs to enable SCC2 */
+ udelay (100000); /* delay makes it look neat */
+ init_sio (0, CRADLE_SIO1_PHYS);
+ udelay (100000);
+ init_sio (1, CRADLE_SIO2_PHYS);
+ udelay (100000);
+ init_sio (2, CRADLE_SIO3_PHYS);
+ udelay (100000);
+ set_led (3, GREEN);
- return 1;
+ return 1;
}
int
/**********************************************************/
-dram_init(bd_t *bd)
+dram_init (void)
/**********************************************************/
{
- bd->bi_dram[0].start = PHYS_SDRAM_1;
- bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
- bd->bi_dram[1].start = PHYS_SDRAM_2;
- bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
- bd->bi_dram[2].start = PHYS_SDRAM_3;
- bd->bi_dram[2].size = PHYS_SDRAM_3_SIZE;
- bd->bi_dram[3].start = PHYS_SDRAM_4;
- bd->bi_dram[3].size = PHYS_SDRAM_4_SIZE;
- return PHYS_SDRAM_1_SIZE + PHYS_SDRAM_2_SIZE + PHYS_SDRAM_3_SIZE + PHYS_SDRAM_4_SIZE;
+ DECLARE_GLOBAL_DATA_PTR;
+
+ gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+ gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+ gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
+ gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
+ gd->bd->bi_dram[2].start = PHYS_SDRAM_3;
+ gd->bd->bi_dram[2].size = PHYS_SDRAM_3_SIZE;
+ gd->bd->bi_dram[3].start = PHYS_SDRAM_4;
+ gd->bd->bi_dram[3].size = PHYS_SDRAM_4_SIZE;
+
+ return (PHYS_SDRAM_1_SIZE +
+ PHYS_SDRAM_2_SIZE +
+ PHYS_SDRAM_3_SIZE +
+ PHYS_SDRAM_4_SIZE );
}
switch (info->flash_id & FLASH_TYPEMASK)
{
- case (INTEL_ID_28F320JA3 & FLASH_TYPEMASK):
- printf("28F320JA3 (32Mbit)\n");
+ case (INTEL_ID_28F320J3A & FLASH_TYPEMASK):
+ printf("28F320J3A (32Mbit)\n");
break;
case (INTEL_ID_28F128J3 & FLASH_TYPEMASK):
printf("28F128J3 (128Mbit)\n");
reset_timer_masked();
if (info->protect[sect] == 0) { /* not protected */
- vushort *addr = (vushort *)(info->start[sect]);
+ vu_short *addr = (vu_short *)(info->start[sect]);
*addr = 0x20; /* erase setup */
*addr = 0xD0; /* erase confirm */
static int write_word (flash_info_t *info, ulong dest, ushort data)
{
- vushort *addr = (vushort *)dest, val;
+ vu_short *addr = (vu_short *)dest, val;
int rc = ERR_OK;
int flag;
* handle word aligned part
*/
while (cnt >= 2) {
- data = *((vushort*)src);
+ data = *((vu_short*)src);
if ((rc = write_word(info, wp, data)) != 0) {
return (rc);
}
--- /dev/null
+#
+# (C) Copyright 2000
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = lib$(BOARD).a
+
+OBJS := csb226.o flash.o
+SOBJS := memsetup.o
+
+$(LIB): $(OBJS) $(SOBJS)
+ $(AR) crv $@ $^
+
+clean:
+ rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+ $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+-include .depend
+
+#########################################################################
--- /dev/null
+#
+# Linux-Kernel is expected to be at c000'8000, entry c000'8000
+#
+# we load ourself to c170'0000, the upper 1 MB of second bank
+#
+# download areas is c800'0000
+#
+
+
+#TEXT_BASE = 0xa1700000
+TEXT_BASE = 0xa3000000
+#TEXT_BASE = 0
+
--- /dev/null
+/*
+ * (C) Copyright 2002
+ * Robert Schwebel, Pengutronix, r.schwebel@pengutronix.de
+ * Kyle Harris, Nexus Technologies, Inc., kharris@nexus-tech.net
+ * Marius Groeger, Sysgo Real-Time Solutions GmbH, mgroeger@sysgo.de
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+/* ------------------------------------------------------------------------- */
+
+
+/*
+ * Miscelaneous platform dependent initialisations
+ */
+
+int board_init (void)
+{
+ DECLARE_GLOBAL_DATA_PTR;
+
+ /* memory and cpu-speed are setup before relocation */
+ /* so we do _nothing_ here */
+
+ /* arch number of CSB226 board */
+ gd->bd->bi_arch_number = 89;
+
+ /* adress of boot parameters */
+ gd->bd->bi_boot_params = 0xa0000100;
+
+ return 1;
+}
+
+int dram_init (void)
+{
+ DECLARE_GLOBAL_DATA_PTR;
+
+ gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+ gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+
+ return PHYS_SDRAM_1_SIZE;
+}
--- /dev/null
+/*
+ * (C) Copyright 2002
+ * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+#define FLASH_BANK_SIZE 0x2000000
+#define MAIN_SECT_SIZE 0x40000 /* 2x16 = 256k per sector */
+
+flash_info_t flash_info[CFG_MAX_FLASH_BANKS];
+
+
+/*-----------------------------------------------------------------------
+ */
+
+ulong flash_init(void)
+{
+ int i, j;
+ ulong size = 0;
+
+ for (i = 0; i < CFG_MAX_FLASH_BANKS; i++)
+ {
+ ulong flashbase = 0;
+ flash_info[i].flash_id =
+ (INTEL_MANUFACT & FLASH_VENDMASK) |
+ (INTEL_ID_28F128J3 & FLASH_TYPEMASK);
+ flash_info[i].size = FLASH_BANK_SIZE;
+ flash_info[i].sector_count = CFG_MAX_FLASH_SECT;
+ memset(flash_info[i].protect, 0, CFG_MAX_FLASH_SECT);
+ switch (i)
+ {
+ case 0:
+ flashbase = PHYS_FLASH_1;
+ break;
+ default:
+ panic("configured to many flash banks!\n");
+ break;
+ }
+ for (j = 0; j < flash_info[i].sector_count; j++)
+ {
+ flash_info[i].start[j] = flashbase + j*MAIN_SECT_SIZE;
+ }
+ size += flash_info[i].size;
+ }
+
+ /* Protect monitor and environment sectors
+ */
+ flash_protect(FLAG_PROTECT_SET,
+ CFG_FLASH_BASE,
+ CFG_FLASH_BASE + _armboot_end - _armboot_start,
+ &flash_info[0]);
+
+ flash_protect(FLAG_PROTECT_SET,
+ CFG_ENV_ADDR,
+ CFG_ENV_ADDR + CFG_ENV_SIZE - 1,
+ &flash_info[0]);
+
+ return size;
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info (flash_info_t *info)
+{
+ int i, j;
+
+ for (j=0; j<CFG_MAX_FLASH_BANKS; j++)
+ {
+ switch (info->flash_id & FLASH_VENDMASK)
+ {
+ case (INTEL_MANUFACT & FLASH_VENDMASK):
+ printf("Intel: ");
+ break;
+ default:
+ printf("Unknown Vendor ");
+ break;
+ }
+
+ switch (info->flash_id & FLASH_TYPEMASK)
+ {
+ case (INTEL_ID_28F128J3 & FLASH_TYPEMASK):
+ printf("28F128J3 (128Mbit)\n");
+ break;
+ default:
+ printf("Unknown Chip Type\n");
+ goto Done;
+ break;
+ }
+
+ printf(" Size: %ld MB in %d Sectors\n",
+ info->size >> 20, info->sector_count);
+
+ printf(" Sector Start Addresses:");
+ for (i = 0; i < info->sector_count; i++)
+ {
+ if ((i % 5) == 0)
+ {
+ printf ("\n ");
+ }
+ printf (" %08lX%s", info->start[i],
+ info->protect[i] ? " (RO)" : " ");
+ }
+ printf ("\n");
+ info++;
+ }
+
+Done:
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+int flash_erase (flash_info_t *info, int s_first, int s_last)
+{
+ int flag, prot, sect;
+ int rc = ERR_OK;
+
+ if (info->flash_id == FLASH_UNKNOWN)
+ return ERR_UNKNOWN_FLASH_TYPE;
+
+ if ((s_first < 0) || (s_first > s_last)) {
+ return ERR_INVAL;
+ }
+
+ if ((info->flash_id & FLASH_VENDMASK) !=
+ (INTEL_MANUFACT & FLASH_VENDMASK)) {
+ return ERR_UNKNOWN_FLASH_VENDOR;
+ }
+
+ prot = 0;
+ for (sect=s_first; sect<=s_last; ++sect) {
+ if (info->protect[sect]) {
+ prot++;
+ }
+ }
+ if (prot)
+ return ERR_PROTECTED;
+
+ /*
+ * Disable interrupts which might cause a timeout
+ * here. Remember that our exception vectors are
+ * at address 0 in the flash, and we don't want a
+ * (ticker) exception to happen while the flash
+ * chip is in programming mode.
+ */
+ flag = disable_interrupts();
+
+ /* Start erase on unprotected sectors */
+ for (sect = s_first; sect<=s_last && !ctrlc(); sect++) {
+
+ printf("Erasing sector %2d ... ", sect);
+
+ /* arm simple, non interrupt dependent timer */
+ reset_timer_masked();
+
+ if (info->protect[sect] == 0) { /* not protected */
+ /* vushort *addr = (vushort *)(info->start[sect]); */
+ ushort *addr = (ushort *)(info->start[sect]);
+
+ *addr = 0x20; /* erase setup */
+ *addr = 0xD0; /* erase confirm */
+
+ while ((*addr & 0x80) != 0x80) {
+ if (get_timer_masked() > CFG_FLASH_ERASE_TOUT) {
+ *addr = 0xB0; /* suspend erase */
+ *addr = 0xFF; /* reset to read mode */
+ rc = ERR_TIMOUT;
+ goto outahere;
+ }
+ }
+
+ /* clear status register command */
+ *addr = 0x50;
+ /* reset to read mode */
+ *addr = 0xFF;
+ }
+ printf("ok.\n");
+ }
+ if (ctrlc())
+ printf("User Interrupt!\n");
+
+outahere:
+
+ /* allow flash to settle - wait 10 ms */
+ udelay_masked(10000);
+
+ if (flag)
+ enable_interrupts();
+
+ return rc;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash
+ */
+
+static int write_word (flash_info_t *info, ulong dest, ushort data)
+{
+ /* vushort *addr = (vushort *)dest, val; */
+ ushort *addr = (ushort *)dest, val;
+ int rc = ERR_OK;
+ int flag;
+
+ /* Check if Flash is (sufficiently) erased
+ */
+ if ((*addr & data) != data)
+ return ERR_NOT_ERASED;
+
+ /*
+ * Disable interrupts which might cause a timeout
+ * here. Remember that our exception vectors are
+ * at address 0 in the flash, and we don't want a
+ * (ticker) exception to happen while the flash
+ * chip is in programming mode.
+ */
+ flag = disable_interrupts();
+
+ /* clear status register command */
+ *addr = 0x50;
+
+ /* program set-up command */
+ *addr = 0x40;
+
+ /* latch address/data */
+ *addr = data;
+
+ /* arm simple, non interrupt dependent timer */
+ reset_timer_masked();
+
+ /* wait while polling the status register */
+ while(((val = *addr) & 0x80) != 0x80)
+ {
+ if (get_timer_masked() > CFG_FLASH_WRITE_TOUT) {
+ rc = ERR_TIMOUT;
+ /* suspend program command */
+ *addr = 0xB0;
+ goto outahere;
+ }
+ }
+
+ if(val & 0x1A) { /* check for error */
+ printf("\nFlash write error %02x at address %08lx\n",
+ (int)val, (unsigned long)dest);
+ if(val & (1<<3)) {
+ printf("Voltage range error.\n");
+ rc = ERR_PROG_ERROR;
+ goto outahere;
+ }
+ if(val & (1<<1)) {
+ printf("Device protect error.\n");
+ rc = ERR_PROTECTED;
+ goto outahere;
+ }
+ if(val & (1<<4)) {
+ printf("Programming error.\n");
+ rc = ERR_PROG_ERROR;
+ goto outahere;
+ }
+ rc = ERR_PROG_ERROR;
+ goto outahere;
+ }
+
+outahere:
+ /* read array command */
+ *addr = 0xFF;
+
+ if (flag)
+ enable_interrupts();
+
+ return rc;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash.
+ */
+
+int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+{
+ ulong cp, wp;
+ ushort data;
+ int l;
+ int i, rc;
+
+ wp = (addr & ~1); /* get lower word aligned address */
+
+ /*
+ * handle unaligned start bytes
+ */
+ if ((l = addr - wp) != 0) {
+ data = 0;
+ for (i=0, cp=wp; i<l; ++i, ++cp) {
+ data = (data >> 8) | (*(uchar *)cp << 8);
+ }
+ for (; i<2 && cnt>0; ++i) {
+ data = (data >> 8) | (*src++ << 8);
+ --cnt;
+ ++cp;
+ }
+ for (; cnt==0 && i<2; ++i, ++cp) {
+ data = (data >> 8) | (*(uchar *)cp << 8);
+ }
+
+ if ((rc = write_word(info, wp, data)) != 0) {
+ return (rc);
+ }
+ wp += 2;
+ }
+
+ /*
+ * handle word aligned part
+ */
+ while (cnt >= 2) {
+ /* data = *((vushort*)src); */
+ data = *((ushort*)src);
+ if ((rc = write_word(info, wp, data)) != 0) {
+ return (rc);
+ }
+ src += 2;
+ wp += 2;
+ cnt -= 2;
+ }
+
+ if (cnt == 0) {
+ return ERR_OK;
+ }
+
+ /*
+ * handle unaligned tail bytes
+ */
+ data = 0;
+ for (i=0, cp=wp; i<2 && cnt>0; ++i, ++cp) {
+ data = (data >> 8) | (*src++ << 8);
+ --cnt;
+ }
+ for (; i<2; ++i, ++cp) {
+ data = (data >> 8) | (*(uchar *)cp << 8);
+ }
+
+ return write_word(info, wp, data);
+}
--- /dev/null
+/*
+ * Most of this taken from Redboot hal_platform_setup.h with cleanup
+ *
+ * NOTE: I haven't clean this up considerably, just enough to get it
+ * running. See hal_platform_setup.h for the source. See
+ * board/cradle/memsetup.S for another PXA250 setup that is
+ * much cleaner.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <version.h>
+#include <asm/arch/pxa-regs.h>
+
+DRAM_SIZE: .long CFG_DRAM_SIZE
+
+// wait for coprocessor write complete
+ .macro CPWAIT reg
+ mrc p15,0,\reg,c2,c0,0
+ mov \reg,\reg
+ sub pc,pc,#4
+ .endm
+
+
+.globl memsetup
+memsetup:
+
+ mov r10, lr
+
+ /* Set up GPIO pins first */
+
+ ldr r0, =GPSR0
+ ldr r1, =CFG_GPSR0_VAL
+ str r1, [r0]
+
+ ldr r0, =GPSR1
+ ldr r1, =CFG_GPSR1_VAL
+ str r1, [r0]
+
+ ldr r0, =GPSR2
+ ldr r1, =CFG_GPSR2_VAL
+ str r1, [r0]
+
+ ldr r0, =GPCR0
+ ldr r1, =CFG_GPCR0_VAL
+ str r1, [r0]
+
+ ldr r0, =GPCR1
+ ldr r1, =CFG_GPCR1_VAL
+ str r1, [r0]
+
+ ldr r0, =GPCR2
+ ldr r1, =CFG_GPCR2_VAL
+ str r1, [r0]
+
+ ldr r0, =GPDR0
+ ldr r1, =CFG_GPDR0_VAL
+ str r1, [r0]
+
+ ldr r0, =GPDR1
+ ldr r1, =CFG_GPDR1_VAL
+ str r1, [r0]
+
+ ldr r0, =GPDR2
+ ldr r1, =CFG_GPDR2_VAL
+ str r1, [r0]
+
+ ldr r0, =GAFR0_L
+ ldr r1, =CFG_GAFR0_L_VAL
+ str r1, [r0]
+
+ ldr r0, =GAFR0_U
+ ldr r1, =CFG_GAFR0_U_VAL
+ str r1, [r0]
+
+ ldr r0, =GAFR1_L
+ ldr r1, =CFG_GAFR1_L_VAL
+ str r1, [r0]
+
+ ldr r0, =GAFR1_U
+ ldr r1, =CFG_GAFR1_U_VAL
+ str r1, [r0]
+
+ ldr r0, =GAFR2_L
+ ldr r1, =CFG_GAFR2_L_VAL
+ str r1, [r0]
+
+ ldr r0, =GAFR2_U
+ ldr r1, =CFG_GAFR2_U_VAL
+ str r1, [r0]
+
+ // enable GPIO pins
+ ldr r0, =PSSR
+ ldr r1, =CFG_PSSR_VAL
+ str r1, [r0]
+
+ ldr r3, =MSC1 // low - bank 2 Lubbock Registers / SRAM
+ ldr r2, =CFG_MSC1_VAL // high - bank 3 Ethernet Controller
+ str r2, [r3] // need to set MSC1 before trying to write to the HEX LEDs
+ ldr r2, [r3] // need to read it back to make sure the value latches (see MSC section of manual)
+
+ ldr r1, =LED_BLANK
+ mov r0, #0xFF
+ str r0, [r1] // turn on hex leds
+
+loop:
+ ldr r0, =0xB0070001
+ ldr r1, =_LED
+ str r0, [r1] // hex display
+
+/*********************************************************************
+ Initlialize Memory Controller
+ The sequence below is based on the recommended init steps detailed
+ in the EAS, chapter 5 (Chapter 10, Operating Systems Developers Guide)
+
+
+ pause for 200 uSecs- allow internal clocks to settle
+ *Note: only need this if hard reset... doing it anyway for now
+*/
+
+ @ ---- Wait 200 usec
+ ldr r3, =OSCR @ reset the OS Timer Count to zero
+ mov r2, #0
+ str r2, [r3]
+ ldr r4, =0x300 @ really 0x2E1 is about 200usec, so 0x300 should be plenty
+1:
+ ldr r2, [r3]
+ cmp r4, r2
+ bgt 1b
+
+mem_init:
+ @ get memory controller base address
+ ldr r1, =MEMC_BASE
+
+@****************************************************************************
+@ Step 1
+@
+
+ @ write msc0, read back to ensure data latches
+ @
+ ldr r2, =CFG_MSC0_VAL
+ str r2, [r1, #MSC0_OFFSET]
+ ldr r2, [r1, #MSC0_OFFSET]
+
+ @ write msc1
+ ldr r2, =CFG_MSC1_VAL
+ str r2, [r1, #MSC1_OFFSET]
+ ldr r2, [r1, #MSC1_OFFSET]
+
+ @ write msc2
+ ldr r2, =CFG_MSC2_VAL
+ str r2, [r1, #MSC2_OFFSET]
+ ldr r2, [r1, #MSC2_OFFSET]
+
+ @ write mecr
+ ldr r2, =CFG_MECR_VAL
+ str r2, [r1, #MECR_OFFSET]
+
+ @ write mcmem0
+ ldr r2, =CFG_MCMEM0_VAL
+ str r2, [r1, #MCMEM0_OFFSET]
+
+ @ write mcmem1
+ ldr r2, =CFG_MCMEM1_VAL
+ str r2, [r1, #MCMEM1_OFFSET]
+
+ @ write mcatt0
+ ldr r2, =CFG_MCATT0_VAL
+ str r2, [r1, #MCATT0_OFFSET]
+
+ @ write mcatt1
+ ldr r2, =CFG_MCATT1_VAL
+ str r2, [r1, #MCATT1_OFFSET]
+
+ @ write mcio0
+ ldr r2, =CFG_MCIO0_VAL
+ str r2, [r1, #MCIO0_OFFSET]
+
+ @ write mcio1
+ ldr r2, =CFG_MCIO1_VAL
+ str r2, [r1, #MCIO1_OFFSET]
+
+ @-------------------------------------------------------
+ @ 3rd bullet, Step 1
+ @
+
+ @ get the mdrefr settings
+ ldr r3, =CFG_MDREFR_VAL_100
+
+ @ extract DRI field (we need a valid DRI field)
+ @
+ ldr r2, =0xFFF
+
+ @ valid DRI field in r3
+ @
+ and r3, r3, r2
+
+ @ get the reset state of MDREFR
+ @
+ ldr r4, [r1, #MDREFR_OFFSET]
+
+ @ clear the DRI field
+ @
+ bic r4, r4, r2
+
+ @ insert the valid DRI field loaded above
+ @
+ orr r4, r4, r3
+
+ @ write back mdrefr
+ @
+ str r4, [r1, #MDREFR_OFFSET]
+
+ @ *Note: preserve the mdrefr value in r4 *
+
+@****************************************************************************
+@ Step 2
+@
+ /* This should be for SRAM, why is it commented out??? */
+
+ @ fetch sxcnfg value
+ @
+ @ldr r2, =0
+ @ write back sxcnfg
+ @str r2, [r1, #SXCNFG_OFFSET]
+
+// @if sxcnfg=0, don't program for synch-static memory
+ @cmp r2, #0
+ @beq 1f
+
+ @program sxmrs
+ @ldr r2, =SXMRS_SETTINGS
+ @str r2, [r1, #SXMRS_OFFSET]
+
+
+@****************************************************************************
+@ Step 3
+@
+
+ @ Assumes previous mdrefr value in r4, if not then read current mdrefr
+
+ @ clear the free-running clock bits
+ @ (clear K0Free, K1Free, K2Free
+ @
+ bic r4, r4, #(0x00800000 | 0x01000000 | 0x02000000)
+
+ @ set K1RUN if bank 0 installed
+ @
+ orr r4, r4, #0x00010000
+
+
+
+#ifdef THIS
+@<!<!<!<!<!<!<!<!<!<!<!<!<!<!<!<!<!<!<!<!<!<!<!<!<!<!<!<!<!<!<!<!<!<!<!<!<!<!<!<!<
+@<!<!<!<!<!<!<!<!<!<!<! Begin INSERT 1 <!<!<!<!<!<!<!<!<!<!<!<!<!<!<!<!<!<!<!<
+ @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
+ @ Lubbock: Allow the user to select the {T/R/M} with predetermined
+ @ SDCLK. Based on Table 3-1 in PXA250 and PXA210 Dev Man.
+ @
+ @ * = Must set MDREFR.K1DB2 to halve the MemClk for desired SDCLK[1]
+ @
+ @ S25, S26 used to provide all 400 MHz BIN values for Cotulla (0,0 - 1,3)
+ @ S25, S26 used to provide all 200 MHz BIN values for Sabinal
+ @
+ @ S23: Force the halving of MemClk when deriving SDCLK[1]
+ @ DOT: no override !DOT: halve (if not already forced half)
+// @ *For certain MemClks, SDCLK's derivation is forced to be halved
+ @
+ @ S24: Run/Turbo.
+ @ DOT: Run mode !DOT: Turbo mode
+ @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
+
+ @
+ @ Allow the user to control K1DB2 where applicable
+ @
+ @ Get the value of S23: @ 1 = DOT (unity), 0 = !DOT (halve it)
+ @
+ @ DOT: set K1DB2 (SDCLD = MemClk)
+ @ !DOT: clear K1DB2 (SDCLK = MemClk/2)
+ @
+ @ldr r2, =FPGA_REGS_BASE_PHYSICAL
+
+ bl GET_S23 @ r3, r2 @ get the value of S23 in R0, i put the base adx of fpga in r3
+
+ cmp r3, #0x0 @ is !DOT?
+ orreq r4, r4, #0x00020000 @ SDClk[1] = MemClk/2
+ bicne r4, r4, #0x00020000 @ SDClk[1] = MemClk
+
+ @
+ @ Next, we need to look for S25,S26 selections that necessitate the
+ @ halving of MemClk to derive SDCLK[1]: (S25,S26)={03-0C, 10-13}
+ @ Override above S23-based selection accordingly.
+ @
+ ldr r2, =FPGA_REGS_BASE_PHYSICAL
+ bl GET_S25 @ r0, r2
+ @ get the value of S25 in R0, i put the base adx of fpga in r2
+
+
+
+ ldr r2, =FPGA_REGS_BASE_PHYSICAL
+ BL GET_S26 @ r3, r2
+ @ get the value of S26 in R1, i put the base adx of fpga in r2
+
+ orr r0, r0, r3 @ concatenate S25 & S26 vals
+ and r0, r0, #0xFF
+
+ @ Set K1DB2 for the frequencies that require it
+ @
+ cmp r0, #0x03
+ cmpne r0, #0x04
+ cmpne r0, #0x05
+ cmpne r0, #0x06
+ cmpne r0, #0x07
+ cmpne r0, #0x08
+ cmpne r0, #0x09
+ cmpne r0, #0x0A
+ cmpne r0, #0x0B
+ cmpne r0, #0x0C
+ cmpne r0, #0x10
+ cmpne r0, #0x11
+ cmpne r0, #0x12
+ cmpne r0, #0x13
+ orreq r4, r4, #0x00020000 @ SDCLK[1] = (MemClk)/2 for 03 - 0C @ 10 - 13
+
+ @
+ @ *Must make MSC0&1 adjustments now for MEMClks > 100MHz.
+ @
+ @ Adjust MSC0 for MemClks > 100 MHz
+ @
+ ldreq r0, [r1, #MSC0_OFFSET]
+ ldreq r3, =0x7F007F00
+ biceq r0, r0, r3 @ clear MSC0[14:12, 11:8] (RRR, RDN)
+ ldreq r3, =0x46004600
+ orreq r0, r0, r3 @ set MSC0[14, 10:9] (doubling RRR, RDN)
+ streq r0, [r1, #MSC0_OFFSET]
+ ldreq r0, [r1, #MSC0_OFFSET] @ read it back to ensure that the data latches
+
+ @
+ @ Adjust MSC1.LH for MemClks > 100 MHz
+ @
+ ldreq r0, [r1, #MSC1_OFFSET]
+ ldreq r3, =0x7FF0
+ biceq r0, r0, r3 @ clear MSC1[14:12, 11:8, 7:4] (RRR, RDN, RDF)
+ ldreq r3, =0x4880
+ orreq r0, r0, r3 @ set MSC1[14, 11, 7] (doubling RRR, RDN, RDF)
+ streq r0, [r1, #MSC1_OFFSET]
+ ldreq r0, [r1, #MSC1_OFFSET] @ read it back to ensure that the data latches
+
+ @ @
+ @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
+#endif
+
+@<!<!<!<!<!<!<!<!<!<!<! End INSERT 1 <!<!<!<!<!<!<!<!<!<!<!<!<!<!<!<!<!<!<!<
+@<!<!<!<!<!<!<!<!<!<!<!<!<!<!<!<!<!<!<!<!<!<!<!<!<!<!<!<!<!<!<!<!<!<!<!<!<!<!<!<!<
+
+
+ @ write back mdrefr
+ @
+ str r4, [r1, #MDREFR_OFFSET]
+ ldr r4, [r1, #MDREFR_OFFSET]
+
+ @ deassert SLFRSH
+ @
+ bic r4, r4, #0x00400000
+
+ @ write back mdrefr
+ @
+ str r4, [r1, #MDREFR_OFFSET]
+
+ @ assert E1PIN
+ @
+ orr r4, r4, #0x00008000
+
+ @ write back mdrefr
+ @
+ str r4, [r1, #MDREFR_OFFSET]
+ ldr r4, [r1, #MDREFR_OFFSET]
+ nop
+ nop
+
+
+@****************************************************************************
+@ Step 4
+@
+
+ @ fetch platform value of mdcnfg
+ @
+ ldr r2, =CFG_MDCNFG_VAL
+
+ @ disable all sdram banks
+ @
+ bic r2, r2, #(MDCNFG_DE0 | MDCNFG_DE1)
+ bic r2, r2, #(MDCNFG_DE2 | MDCNFG_DE3)
+
+ @ program banks 0/1 for bus width
+ @
+ bic r2, r2, #MDCNFG_DWID0 @0=32-bit
+
+
+ @ write initial value of mdcnfg, w/o enabling sdram banks
+ @
+ str r2, [r1, #MDCNFG_OFFSET]
+
+@ ****************************************************************************
+@ Step 5
+@
+
+ @ pause for 200 uSecs
+ @
+ ldr r3, =OSCR @reset the OS Timer Count to zero
+ mov r2, #0
+ str r2, [r3]
+ ldr r4, =0x300 @really 0x2E1 is about 200usec, so 0x300 should be plenty
+1:
+ ldr r2, [r3]
+ cmp r4, r2
+ bgt 1b
+
+
+@****************************************************************************
+@ Step 6
+@
+
+ mov r0, #0x78 @turn everything off
+ mcr p15, 0, r0, c1, c0, 0 @(caches off, MMU off, etc.)
+
+
+@ ****************************************************************************
+@ Step 7
+@
+ @ Access memory *not yet enabled* for CBR refresh cycles (8)
+ @ - CBR is generated for all banks
+
+ ldr r2, =CFG_DRAM_BASE
+ str r2, [r2]
+ str r2, [r2]
+ str r2, [r2]
+ str r2, [r2]
+ str r2, [r2]
+ str r2, [r2]
+ str r2, [r2]
+ str r2, [r2]
+
+
+@ ****************************************************************************
+@ Step 8: NOP (enable dcache if you wanna... we dont)
+@
+
+
+@ ****************************************************************************
+@ Step 9
+@
+
+
+ @get memory controller base address
+ @
+ ldr r1, =MEMC_BASE
+
+ @fetch current mdcnfg value
+ @
+ ldr r3, [r1, #MDCNFG_OFFSET]
+
+ @enable sdram bank 0 if installed (must do for any populated bank)
+ @
+ orr r3, r3, #MDCNFG_DE0
+
+ @write back mdcnfg, enabling the sdram bank(s)
+ @
+ str r3, [r1, #MDCNFG_OFFSET]
+
+
+@****************************************************************************
+@ Step 10
+@
+
+ @ write mdmrs
+ @
+ ldr r2, =CFG_MDMRS_VAL
+ str r2, [r1, #MDMRS_OFFSET]
+
+
+@****************************************************************************
+@ Step 11: Final Step
+@
+
+@INITINTC
+ @********************************************************************
+ @ Disable (mask) all interrupts at the interrupt controller
+ @
+
+ @ clear the interrupt level register (use IRQ, not FIQ)
+ @
+ mov r1, #0
+ ldr r2, =ICLR
+ str r1, [r2]
+
+ @ mask all interrupts at the controller
+ @
+ ldr r2, =ICMR
+ str r1, [r2]
+
+
+@INITCLKS
+ @ ********************************************************************
+ @ Disable the peripheral clocks, and set the core clock
+ @ frequency (hard-coding at 398.12MHz for now).
+ @
+
+ @ Turn Off ALL on-chip peripheral clocks for re-configuration
+ @ *Note: See label 'ENABLECLKS' for the re-enabling
+ @
+ ldr r1, =CKEN
+ mov r2, #0
+ str r2, [r1]
+
+
+ @ default value in case no valid rotary switch setting is found
+ ldr r2, =(CCCR_L27 | CCCR_M2 | CCCR_N10) @ DEFAULT: {200/200/100}
+
+
+ @... and write the core clock config register
+ @
+ ldr r1, =CCCR
+ str r2, [r1]
+
+/*
+ @ enable the 32Khz oscillator for RTC and PowerManager
+ @
+ ldr r1, =OSCC
+ mov r2, #OSCC_OON
+ str r2, [r1]
+
+
+ @ NOTE: spin here until OSCC.OOK get set,
+ @ meaning the PLL has settled.
+ @
+60:
+ ldr r2, [r1]
+ ands r2, r2, #1
+ beq 60b
+*/
+
+@OSCC_OON_DONE
+
+
+#ifdef A0_COTULLA
+ @****************************************************************************
+ @ !!! Take care of A0 Errata Sighting #4 --
+ @ after a frequency change, the memory controller must be restarted
+ @
+
+ @ get memory controller base address
+ ldr r1, =MEMC_BASE
+
+ @ get the current state of MDREFR
+ @
+ ldr r2, [r1, #MDREFR_OFFSET]
+
+ @ clear E0PIN, E1PIN
+ @
+ bic r3, r2, #(MDREFR_E0PIN | MDREFR_E1PIN)
+
+ @ write MDREFR with E0PIN, E1PIN cleared (disable sdclk[0,1])
+ @
+ str r3, [r1, #MDREFR_OFFSET]
+
+ @ then write MDREFR with E0PIN, E1PIN set (enable sdclk[0,1])
+ @
+ str r2, [r1, #MDREFR_OFFSET]
+
+ @ get the current state of MDCNFG
+ @
+ ldr r3, [r1, #MDCNFG_OFFSET]
+
+ @ disable all SDRAM banks
+ @
+ bic r3, r3, #(MDCNFG_DE0 | MDCNFG_DE1)
+ bic r3, r3, #(MDCNFG_DE2 | MDCNFG_DE3)
+
+ @ write back MDCNFG
+ @
+ ldr r3, [r1, #MDCNFG_OFFSET]
+
+ @ Access memory not yet enabled for CBR refresh cycles (8)
+ @ - CBR is generated for *all* banks
+ ldr r2, =CFG_DRAM_BASE
+ str r2, [r2]
+ str r2, [r2]
+ str r2, [r2]
+ str r2, [r2]
+ str r2, [r2]
+ str r2, [r2]
+ str r2, [r2]
+ str r2, [r2]
+
+ @ fetch current mdcnfg value
+ @
+ ldr r3, [r1, #MDCNFG_OFFSET]
+
+ @ enable sdram bank 0 if installed
+ @
+ orr r3, r3, #MDCNFG_DE0
+
+ @ write back mdcnfg, enabling the sdram bank(s)
+ @
+ str r3, [r1, #MDCNFG_OFFSET]
+
+ @ write mdmrs
+ @
+ ldr r2, =CFG_MDMRS_VAL
+ str r2, [r1, #MDMRS_OFFSET]
+
+
+
+ // @ errata: don't enable auto power-down
+ @ get current value of mdrefr
+ @ldr r3, [r1, #MDREFR_OFFSET]
+ @ enable auto-power down
+ @orr r3, r3, #MDREFR_APD
+ @write back mdrefr
+ @str r3, [r1, #MDREFR_OFFSET]
+
+#endif A0_Cotulla
+
+
+ ldr r0, =0x000C0dE3
+ ldr r1, =_LED
+ str r0, [r1] // hex display
+
+@ ^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%
+@ ^%^%^%^%^%^%^%^%^% above could be replaced by prememLLI ^%^%^%^%^%^%^%^%^%
+@ ^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%
+
+
+ // Save SDRAM size
+ ldr r1, =DRAM_SIZE
+ str r8, [r1]
+
+ ldr r0, =0xC0DE0006
+ ldr r1, =_LED
+ str r0, [r1] // hex display
+
+ // Interrupt init
+ // Mask all interrupts
+ ldr r0, =ICMR // enable no sources
+ mov r1, #0
+ str r1, [r0]
+
+#define NODEBUG
+#ifdef NODEBUG
+ //Disable software and data breakpoints
+ mov r0,#0
+ mcr p15,0,r0,c14,c8,0 // ibcr0
+ mcr p15,0,r0,c14,c9,0 // ibcr1
+ mcr p15,0,r0,c14,c4,0 // dbcon
+
+ //Enable all debug functionality
+ mov r0,#0x80000000
+ mcr p14,0,r0,c10,c0,0 // dcsr
+
+#endif
+
+ ldr r0, =0xBEEF001D
+ ldr r1, =_LED
+ str r0, [r1] // hex display
+
+ mov pc, r10
+
+@ End memsetup
+
+#ifdef gargelpu
+@ %%%%%%%%%%% Useful subroutines
+GET_S23:
+ @ This macro will read S23 and return its value in r3
+ @ r2 contains the base address of the Lubbock user registers
+ ldr r2, =FPGA_REGS_BASE_PHYSICAL
+
+ //@ read S23's value
+ ldr r3, [r2, #USER_SWITCHES_OFFSET]
+
+ @ mask out irrelevant bits
+ and r3, r3, #0x200
+
+ @ get bit into position 0
+ mov r3, r3, LSR #9
+
+ mov pc, lr
+@ End GET_S23
+
+
+GET_S24:
+ @ This macro will read S24 and return its value in r0
+ @ r2 contains the base address of the Lubbock user registers
+ ldr r2, =FPGA_REGS_BASE_PHYSICAL
+
+ //@ read S24's value
+ ldr r0, [r2, #USER_SWITCHES_OFFSET]
+
+ @ mask out irrelevant bits
+ and r0, r0, #0x100
+
+ @ get bit into position 0
+ mov r0, r0, LSR #8
+
+ mov pc, lr
+@ End GET_S23
+
+
+GET_S25:
+ @ This macro will read rotary S25 and return its value in r0
+ @ r2 contains the base address of the Lubbock user registers
+ @ read the user switches register
+ ldr r0, [r2, #USER_SWITCHES_OFFSET]
+
+ @ mask out irrelevant bits
+ and r0, r0, #0xF0
+
+ mov pc, lr
+@ End subroutine
+
+
+GET_S26:
+ @ This macro will read rotary S26 and return its value in r3
+ @ r2 contains the base address of the Lubbock user registers
+ @ read the user switches register
+ ldr r3, [r2, #USER_SWITCHES_OFFSET]
+
+ @ mask out irrelevant bits
+ and r3, r3, #0x0F
+
+ mov pc, lr
+@ End subroutine GET_S26
+
+#endif /* gargelpu */
+
reset_timer_masked();
if (info->protect[sect] == 0) { /* not protected */
- vushort *addr = (vushort *)(info->start[sect]);
+ vu_short *addr = (vu_short *)(info->start[sect]);
*addr = 0x20; /* erase setup */
*addr = 0xD0; /* erase confirm */
static int write_word (flash_info_t *info, ulong dest, ushort data)
{
- vushort *addr = (vushort *)dest, val;
+ vu_short *addr = (vu_short *)dest, val;
int rc = ERR_OK;
int flag;
* handle word aligned part
*/
while (cnt >= 2) {
- data = *((vushort*)src);
+ data = *((vu_short*)src);
if ((rc = write_word(info, wp, data)) != 0) {
return (rc);
}
* Miscelaneous platform dependent initialisations
*/
-int board_init(bd_t *bd)
+int board_init (void)
{
- /* memory and cpu-speed are setup before relocation */
- /* so we do _nothing_ here */
+ DECLARE_GLOBAL_DATA_PTR;
- /* arch number of Lubbock-Board */
- bd->bi_arch_number = 89;
+ /* memory and cpu-speed are setup before relocation */
+ /* so we do _nothing_ here */
- /* adress of boot parameters */
- bd->bi_boot_params = 0xa0000100;
+ /* arch number of Lubbock-Board */
+ gd->bd->bi_arch_number = 89;
- return 1;
+ /* adress of boot parameters */
+ gd->bd->bi_boot_params = 0xa0000100;
+
+ return 1;
}
-int dram_init(bd_t *bd)
+int dram_init (void)
{
- bd->bi_dram[0].start = PHYS_SDRAM_1;
- bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
- bd->bi_dram[1].start = PHYS_SDRAM_2;
- bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
- bd->bi_dram[2].start = PHYS_SDRAM_3;
- bd->bi_dram[2].size = PHYS_SDRAM_3_SIZE;
- bd->bi_dram[3].start = PHYS_SDRAM_4;
- bd->bi_dram[3].size = PHYS_SDRAM_4_SIZE;
- return PHYS_SDRAM_1_SIZE + PHYS_SDRAM_2_SIZE + PHYS_SDRAM_3_SIZE + PHYS_SDRAM_4_SIZE;
+ DECLARE_GLOBAL_DATA_PTR;
+
+ gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+ gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+ gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
+ gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
+ gd->bd->bi_dram[2].start = PHYS_SDRAM_3;
+ gd->bd->bi_dram[2].size = PHYS_SDRAM_3_SIZE;
+ gd->bd->bi_dram[3].start = PHYS_SDRAM_4;
+ gd->bd->bi_dram[3].size = PHYS_SDRAM_4_SIZE;
+ return PHYS_SDRAM_1_SIZE + PHYS_SDRAM_2_SIZE + PHYS_SDRAM_3_SIZE +
+ PHYS_SDRAM_4_SIZE;
}
--- /dev/null
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+ . = 0x00000000;
+
+ . = ALIGN(4);
+ .text :
+ {
+ cpu/xscale/start.o (.text)
+ *(.text)
+ }
+
+ . = ALIGN(4);
+ .rodata : { *(.rodata) }
+
+ . = ALIGN(4);
+ .data : { *(.data) }
+
+ . = ALIGN(4);
+ .got : { *(.got) }
+
+ . = ALIGN(4);
+ .bss : { *(.bss) }
+
+ armboot_end = .;
+}
-/*
- * (C) Copyright 2001
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+/***********************************************************************
+ *
+M* Modul: lwmon.c
+M*
+M* Content: LWMON specific ppcboot commands.
+ *
+ * (C) Copyright 2001, 2002
+ * DENX Software Engineering
+ * Wolfgang Denk, wd@denx.de
+ * All rights reserved.
+ *
+D* Design: wd@denx.de
+C* Coding: wd@denx.de
+V* Verification: dzu@denx.de
*
* See file CREDITS for list of people who contributed to this
* project.
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
- */
+ ***********************************************************************/
+/*---------------------------- Headerfiles ----------------------------*/
#include <common.h>
#include <mpc8xx.h>
#include <commproc.h>
#include <linux/types.h>
#include <linux/string.h> /* for strdup */
-/* ------------------------------------------------------------------------- */
-
+/*------------------------ Local prototypes ---------------------------*/
static long int dram_size (long int, long int *, long int);
-/* ------------------------------------------------------------------------- */
+/*--------------------- Local macros and constants --------------------*/
#define _NOT_USED_ 0xFFFFFFFF
/*
#endif
};
-/* ------------------------------------------------------------------------- */
-
-
/*
* Check Board Identity:
*
*/
+/***********************************************************************
+F* Function: int checkboard (void) P*A*Z*
+ *
+P* Parameters: none
+P*
+P* Returnvalue: int - 0 is always returned
+ *
+Z* Intention: This function is the checkboard() method implementation
+Z* for the lwmon board. Only a standard message is printed.
+ *
+D* Design: wd@denx.de
+C* Coding: wd@denx.de
+V* Verification: dzu@denx.de
+ ***********************************************************************/
int checkboard (void)
{
puts ("Board: Litronic Monitor IV\n");
return (0);
}
-/* ------------------------------------------------------------------------- */
-
+/***********************************************************************
+F* Function: long int initdram (int board_type) P*A*Z*
+ *
+P* Parameters: int board_type
+P* - Usually type of the board - ignored here.
+P*
+P* Returnvalue: long int
+P* - Size of initialized memory
+ *
+Z* Intention: This function is the initdram() method implementation
+Z* for the lwmon board.
+Z* The memory controller is initialized to access the
+Z* DRAM.
+ *
+D* Design: wd@denx.de
+C* Coding: wd@denx.de
+V* Verification: dzu@denx.de
+ ***********************************************************************/
long int initdram (int board_type)
{
volatile immap_t *immr = (immap_t *) CFG_IMMR;
return (size_b0);
}
-/* ------------------------------------------------------------------------- */
-
-/*
- * Check memory range for valid RAM. A simple memory test determines
- * the actually available RAM size between addresses `base' and
- * `base + maxsize'. Some (not all) hardware errors are detected:
- * - short between address lines
- * - short between data lines
- */
-
+/***********************************************************************
+F* Function: static long int dram_size (long int mamr_value,
+F* long int *base,
+F* long int maxsize) P*A*Z*
+ *
+P* Parameters: long int mamr_value
+P* - Value for MAMR for the test
+P* long int *base
+P* - Base address for the test
+P* long int maxsize
+P* - Maximum size to test for
+P*
+P* Returnvalue: long int
+P* - Size of probed memory
+ *
+Z* Intention: Check memory range for valid RAM. A simple memory test
+Z* determines the actually available RAM size between
+Z* addresses `base' and `base + maxsize'. Some (not all)
+Z* hardware errors are detected:
+Z* - short between address lines
+Z* - short between data lines
+ *
+D* Design: wd@denx.de
+C* Coding: wd@denx.de
+V* Verification: dzu@denx.de
+ ***********************************************************************/
static long int dram_size (long int mamr_value, long int *base, long int maxsize)
{
volatile immap_t *immr = (immap_t *) CFG_IMMR;
# define PB_ENET_TENA ((uint)0x00002000) /* PB 18 */
#endif
+/***********************************************************************
+F* Function: int board_pre_init (void) P*A*Z*
+ *
+P* Parameters: none
+P*
+P* Returnvalue: int
+P* - 0 is always returned.
+ *
+Z* Intention: This function is the board_pre_init() method implementation
+Z* for the lwmon board.
+Z* Disable Ethernet TENA on Port B.
+ *
+D* Design: wd@denx.de
+C* Coding: wd@denx.de
+V* Verification: dzu@denx.de
+ ***********************************************************************/
int board_pre_init (void)
{
volatile immap_t *immr = (immap_t *) CFG_IMMR;
/* ------------------------------------------------------------------------- */
+/***********************************************************************
+F* Function: void reset_phy (void) P*A*Z*
+ *
+P* Parameters: none
+P*
+P* Returnvalue: none
+ *
+Z* Intention: Reset the PHY. In the lwmon case we do this by the
+Z* signaling the PIC I/O expander.
+ *
+D* Design: wd@denx.de
+C* Coding: wd@denx.de
+V* Verification: dzu@denx.de
+ ***********************************************************************/
void reset_phy (void)
{
uchar c;
udelay (1000);
}
-/*-----------------------------------------------------------------------
- * Keyboard Controller
- */
+
+/*------------------------- Keyboard controller -----------------------*/
/* command codes */
#define KEYBD_CMD_READ_KEYS 0x01
#define KEYBD_CMD_READ_VERSION 0x02
#define KEYBD_SET_DEBUGMODE '#' /* Magic key to enable debug output */
+/***********************************************************************
+F* Function: int misc_init_r (void) P*A*Z*
+ *
+P* Parameters: none
+P*
+P* Returnvalue: int
+P* - 0 is always returned, even in the case of a keyboard
+P* error.
+ *
+Z* Intention: This function is the misc_init_r() method implementation
+Z* for the lwmon board.
+Z* The keyboard controller is initialized and the result
+Z* of a read copied to the environment variable "keybd".
+Z* If KEYBD_SET_DEBUGMODE is defined, a check is made for
+Z* this key, and if found display to the LCD will be enabled.
+Z* The keys in "keybd" are checked against the magic
+Z* keycommands defined in the environment.
+Z* See also key_match().
+ *
+D* Design: wd@denx.de
+C* Coding: wd@denx.de
+V* Verification: dzu@denx.de
+ ***********************************************************************/
int misc_init_r (void)
{
uchar kbd_data[KEYBD_DATALEN];
return (0);
}
-/*-----------------------------------------------------------------------
- * Check if pressed key(s) match magic sequence,
- * and return the command string associated with that key(s).
- *
- * If no key press was decoded, NULL is returned.
- *
- * Note: the first character of the argument will be overwritten with
- * the "magic charcter code" of the decoded key(s), or '\0'.
- *
- *
- * Note: the string points to static environment data and must be
- * saved before you call any function that modifies the environment.
- */
#ifdef CONFIG_PREBOOT
static uchar kbd_magic_prefix[] = "key_magic";
static uchar kbd_command_prefix[] = "key_cmd";
+/***********************************************************************
+F* Function: static uchar *key_match (uchar *kbd_data) P*A*Z*
+ *
+P* Parameters: uchar *kbd_data
+P* - The keys to match against our magic definitions
+P*
+P* Returnvalue: uchar *
+P* - != NULL: Pointer to the corresponding command(s)
+P* NULL: No magic is about to happen
+ *
+Z* Intention: Check if pressed key(s) match magic sequence,
+Z* and return the command string associated with that key(s).
+Z*
+Z* If no key press was decoded, NULL is returned.
+Z*
+Z* Note: the first character of the argument will be
+Z* overwritten with the "magic charcter code" of the
+Z* decoded key(s), or '\0'.
+Z*
+Z* Note: the string points to static environment data
+Z* and must be saved before you call any function that
+Z* modifies the environment.
+ *
+D* Design: wd@denx.de
+C* Coding: wd@denx.de
+V* Verification: dzu@denx.de
+ ***********************************************************************/
static uchar *key_match (uchar *kbd_data)
{
uchar compare[KEYBD_DATALEN-1];
}
#endif /* CONFIG_PREBOOT */
-/*-----------------------------------------------------------------------
- * Board Special Commands: PIC read/write
- */
+/*---------------Board Special Commands: PIC read/write ---------------*/
+
#if (CONFIG_COMMANDS & CFG_CMD_BSP)
+/***********************************************************************
+F* Function: int do_pic (cmd_tbl_t *cmdtp, int flag,
+F* int argc, char *argv[]) P*A*Z*
+ *
+P* Parameters: cmd_tbl_t *cmdtp
+P* - Pointer to our command table entry
+P* int flag
+P* - If the CMD_FLAG_REPEAT bit is set, then this call is
+P* a repetition
+P* int argc
+P* - Argument count
+P* char *argv[]
+P* - Array of the actual arguments
+P*
+P* Returnvalue: int
+P* - 0 The command was handled successfully
+P* 1 An error occurred
+ *
+Z* Intention: Implement the "pic [read|write]" commands.
+Z* The read subcommand takes one argument, the register,
+Z* whereas the write command takes two, the register and
+Z* the new value.
+ *
+D* Design: wd@denx.de
+C* Coding: wd@denx.de
+V* Verification: dzu@denx.de
+ ***********************************************************************/
int do_pic (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
uchar reg, val;
return 1;
}
-/* Read Keyboard status */
+/***********************************************************************
+F* Function: int do_kbd (cmd_tbl_t *cmdtp, int flag,
+F* int argc, char *argv[]) P*A*Z*
+ *
+P* Parameters: cmd_tbl_t *cmdtp
+P* - Pointer to our command table entry
+P* int flag
+P* - If the CMD_FLAG_REPEAT bit is set, then this call is
+P* a repetition
+P* int argc
+P* - Argument count
+P* char *argv[]
+P* - Array of the actual arguments
+P*
+P* Returnvalue: int
+P* - 0 is always returned.
+ *
+Z* Intention: Implement the "kbd" command.
+Z* The keyboard status is read. The result is printed on
+Z* the console and written into the "keybd" environment
+Z* variable.
+ *
+D* Design: wd@denx.de
+C* Coding: wd@denx.de
+V* Verification: dzu@denx.de
+ ***********************************************************************/
int do_kbd (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
uchar kbd_data[KEYBD_DATALEN];
/* Read and set LSB switch */
#define CFG_PC_TXD1_ENA 0x0008
+/***********************************************************************
+F* Function: int do_lsb (cmd_tbl_t *cmdtp, int flag,
+F* int argc, char *argv[]) P*A*Z*
+ *
+P* Parameters: cmd_tbl_t *cmdtp
+P* - Pointer to our command table entry
+P* int flag
+P* - If the CMD_FLAG_REPEAT bit is set, then this call is
+P* a repetition
+P* int argc
+P* - Argument count
+P* char *argv[]
+P* - Array of the actual arguments
+P*
+P* Returnvalue: int
+P* - 0 The command was handled successfully
+P* 1 An error occurred
+ *
+Z* Intention: Implement the "lsb [on|off]" commands.
+Z* The lsb is switched according to the first parameter by
+Z* by signaling the PIC I/O expander.
+Z* Called with no arguments, the current setting is
+Z* printed.
+ *
+D* Design: wd@denx.de
+C* Coding: wd@denx.de
+V* Verification: dzu@denx.de
+ ***********************************************************************/
int do_lsb (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
uchar val;
#endif /* CFG_CMD_BSP */
-/*-----------------------------------------------------------------------
- * Utilities
- */
-
+/*----------------------------- Utilities -----------------------------*/
+/***********************************************************************
+F* Function: uchar pic_read (uchar reg) P*A*Z*
+ *
+P* Parameters: uchar reg
+P* - Register to read
+P*
+P* Returnvalue: uchar
+P* - Value read from register
+ *
+Z* Intention: Read a register from the PIC I/O expander.
+ *
+D* Design: wd@denx.de
+C* Coding: wd@denx.de
+V* Verification: dzu@denx.de
+ ***********************************************************************/
uchar pic_read (uchar reg)
{
return (i2c_reg_read (CFG_I2C_PICIO_ADDR, reg));
}
+/***********************************************************************
+F* Function: void pic_write (uchar reg, uchar val) P*A*Z*
+ *
+P* Parameters: uchar reg
+P* - Register to read
+P* uchar val
+P* - Value to write
+P*
+P* Returnvalue: none
+ *
+Z* Intention: Write to a register on the PIC I/O expander.
+ *
+D* Design: wd@denx.de
+C* Coding: wd@denx.de
+V* Verification: dzu@denx.de
+ ***********************************************************************/
void pic_write (uchar reg, uchar val)
{
i2c_reg_write (CFG_I2C_PICIO_ADDR, reg, val);
}
-/*-----------------------------------------------------------------------
- * Board Control Functions
- */
+/*---------------------- Board Control Functions ----------------------*/
+/***********************************************************************
+F* Function: void board_poweroff (void) P*A*Z*
+ *
+P* Parameters: none
+P*
+P* Returnvalue: none
+ *
+Z* Intention: Turn off the battery power and loop endless, so this
+Z* should better be the last function you call...
+ *
+D* Design: wd@denx.de
+C* Coding: wd@denx.de
+V* Verification: dzu@denx.de
+ ***********************************************************************/
void board_poweroff (void)
{
/* Turn battery off */
#include <environment.h>
#include <cmd_nvedit.h>
#include <linux/stddef.h>
+#include <asm/byteorder.h>
#if (CONFIG_COMMANDS & CFG_CMD_NET)
#include <net.h>
#endif
{
int abort = 0;
uint64_t etime = endtick(bootdelay);
- char* delaykey = getenv ("bootdelaykey");
- u_int delaykey_len;
- char* stopkey = getenv ("bootstopkey");
- u_int stopkey_len;
+ struct
+ {
+ char* str;
+ u_int len;
+ int retry;
+ }
+ delaykey [] =
+ {
+ { str: getenv ("bootdelaykey"), retry: 1 },
+ { str: getenv ("bootdelaykey2"), retry: 1 },
+ { str: getenv ("bootstopkey"), retry: 0 },
+ { str: getenv ("bootstopkey2"), retry: 0 },
+ };
+
char presskey [MAX_DELAY_STOP_STR];
- u_int presskey_len;
- u_int presskey_max;
+ u_int presskey_len = 0;
+ u_int presskey_max = 0;
u_int i;
# ifdef CONFIG_AUTOBOOT_PROMPT
# endif
# ifdef CONFIG_AUTOBOOT_DELAY_STR
- if (delaykey == NULL)
- delaykey = CONFIG_AUTOBOOT_DELAY_STR;
+ if (delaykey[0].str == NULL)
+ delaykey[0].str = CONFIG_AUTOBOOT_DELAY_STR;
+# endif
+# ifdef CONFIG_AUTOBOOT_DELAY_STR2
+ if (delaykey[1].str == NULL)
+ delaykey[1].str = CONFIG_AUTOBOOT_DELAY_STR2;
# endif
# ifdef CONFIG_AUTOBOOT_STOP_STR
- if (stopkey == NULL)
- stopkey = CONFIG_AUTOBOOT_STOP_STR;
+ if (delaykey[2].str == NULL)
+ delaykey[2].str = CONFIG_AUTOBOOT_STOP_STR;
+# endif
+# ifdef CONFIG_AUTOBOOT_STOP_STR2
+ if (delaykey[3].str == NULL)
+ delaykey[3].str = CONFIG_AUTOBOOT_STOP_STR2;
# endif
- delaykey_len = delaykey == NULL ? 0 : strlen (delaykey);
- stopkey_len = stopkey == NULL ? 0 : strlen (stopkey);
-
- delaykey_len = delaykey_len > MAX_DELAY_STOP_STR ?
- MAX_DELAY_STOP_STR : delaykey_len;
- stopkey_len = stopkey_len > MAX_DELAY_STOP_STR ?
- MAX_DELAY_STOP_STR : stopkey_len;
+ for (i = 0; i < sizeof(delaykey) / sizeof(delaykey[0]); i ++) {
+ delaykey[i].len = delaykey[i].str == NULL ?
+ 0 : strlen (delaykey[i].str);
+ delaykey[i].len = delaykey[i].len > MAX_DELAY_STOP_STR ?
+ MAX_DELAY_STOP_STR : delaykey[i].len;
- presskey_max = delaykey_len < stopkey_len ? stopkey_len : delaykey_len;
- presskey_len = 0;
+ presskey_max = presskey_max > delaykey[i].len ?
+ presskey_max : delaykey[i].len;
# if DEBUG_BOOTKEYS
- printf("delay key:<%s>\n",delaykey?delaykey:"NULL");
- printf("stop key:<%s>\n",stopkey?stopkey:"NULL");
+ printf("%s key:<%s>\n",
+ delaykey[i].retry ? "delay" : "stop",
+ delaykey[i].str ? delaykey[i].str : "NULL");
# endif
+ }
/* In order to keep up with incoming data, check timeout only
* when catch up.
*/
while (!abort && get_ticks() <= etime) {
- /* abort if matched all of one of the keys */
- if (delaykey_len > 0 && presskey_len >= delaykey_len &&
- memcmp (presskey + presskey_len - delaykey_len,
- delaykey,
- delaykey_len) == 0) {
+ for (i = 0; i < sizeof(delaykey) / sizeof(delaykey[0]); i ++) {
+ if (delaykey[i].len > 0 &&
+ presskey_len >= delaykey[i].len &&
+ memcmp (presskey + presskey_len - delaykey[i].len,
+ delaykey[i].str,
+ delaykey[i].len) == 0) {
# if DEBUG_BOOTKEYS
- printf("got delaykey\n");
-# endif
- abort = 1;
- }
- if (stopkey_len > 0 && presskey_len >= stopkey_len &&
- memcmp (presskey + presskey_len - stopkey_len,
- stopkey,
- stopkey_len) == 0) {
-# if DEBUG_BOOTKEYS
- printf("got stopkey\n");
+ printf("got %skey\n",
+ delaykey[i].retry ? "delay" : "stop");
# endif
+
# ifdef CONFIG_BOOT_RETRY_TIME
- /* don't retry auto boot */
- retry_time = -1;
+ /* don't retry auto boot */
+ if (! delaykey[i].retry)
+ retry_time = -1;
# endif
- abort = 1;
+ abort = 1;
+ }
}
+
if (tstc()) {
if (presskey_len < presskey_max) {
presskey [presskey_len ++] = getc();
#include <common.h>
#include <asm/arch/pxa-regs.h>
-#include <asm/ptregs.h>
extern void reset_cpu (ulong addr);
-#include <common.h>
+#include <config.h>
#include <version.h>
.globl _start
CONFIG_AUTOBOOT_PROMPT
CONFIG_AUTOBOOT_DELAY_STR
CONFIG_AUTOBOOT_STOP_STR
+ CONFIG_AUTOBOOT_DELAY_STR2
+ CONFIG_AUTOBOOT_STOP_STR2
- bootdelaykey environment variable
- bootstopkey environment variable
+ bootdelaykey environment variable
+ bootstopkey environment variable
+ bootdelaykey2 environment variable
+ bootstopkey2 environment variable
These options give more control over stopping autoboot. When
they are used a specific character or string is required to
character of a key string does not appear in the rest of the
string.
+ Using the CONFIG_AUTOBOOT_DELAY_STR2 / bootdelaykey2 and/or
+ CONFIG_AUTOBOOT_STOP_STR2 / bootstopkey #defines and/or
+ environment variables you can specify a second, alternate
+ string (which allows you to haw two "password" strings).
+
CONFIG_ZERO_BOOTDELAY_CHECK
If this option is defined, you can stop the autoboot process
/*
. Configures the PHY through the MII Management interface
*/
+#ifndef CONFIG_SMC91111_EXT_PHY
static void smc_phy_configure(void);
+#endif /* !CONFIG_SMC91111_EXT_PHY */
/*
. This is a separate procedure to handle the receipt of a packet, to
MII Management Interface
*/
+#ifndef CONFIG_SMC91111_EXT_PHY
static word smc_read_phy_register(byte phyreg);
static void smc_write_phy_register(byte phyreg, word phydata);
+#endif /* !CONFIG_SMC91111_EXT_PHY */
static int poll4int( byte mask, int timeout ) {
return 0;
}
+#if 0 /* dead code? -- wd */
#ifdef USE_32_BIT
void
insl32(r,b,l)
}
}
#endif
+#endif
/*-------------------------------------------------------------
.
/*------------------------------------------------------------
. Reads a register from the MII Management serial interface
.-------------------------------------------------------------*/
+#ifndef CONFIG_SMC91111_EXT_PHY
static word smc_read_phy_register(byte phyreg)
{
int oldBank;
smc_dump_mii_stream(bits, sizeof bits);
#endif
}
+#endif /* !CONFIG_SMC91111_EXT_PHY */
/*------------------------------------------------------------
. Waits the specified number of milliseconds - kernel friendly
.-------------------------------------------------------------*/
+#ifndef CONFIG_SMC91111_EXT_PHY
static void smc_wait_ms(unsigned int ms)
{
udelay(ms*1000);
}
+#endif /* !CONFIG_SMC91111_EXT_PHY */
. Configures the specified PHY using Autonegotiation. Calls
. smc_phy_fixed() if the user has requested a certain config.
.-------------------------------------------------------------*/
+#ifndef CONFIG_SMC91111_EXT_PHY
static void smc_phy_configure()
{
int timeout;
smc_phy_configure_exit:
}
+#endif /* !CONFIG_SMC91111_EXT_PHY */
#if SMC_DEBUG > 2
#define CFG_ENV_IS_IN_FLASH 1
#define CFG_ENV_ADDR 0x00020000 /* absolute address for now */
#define CFG_ENV_SIZE 0x20000 /* 8K ouch, this may later be */
-#endif
/******************************************************************************
*
* Verify timings on all
*/
#define CFG_MSC0_VAL 0x000023FA /* flash bank (cs0) */
-//#define CFG_MSC1_VAL 0x00003549 /* SuperIO bank (cs2) */
+/*#define CFG_MSC1_VAL 0x00003549 / * SuperIO bank (cs2) */
#define CFG_MSC1_VAL 0x0000354c /* SuperIO bank (cs2) */
#define CFG_MSC2_VAL 0x00001224 /* Ethernet bank (cs4) */
#ifdef REDBOOT_WAY
--- /dev/null
+/*
+ * (C) Copyright 2000, 2001, 2002
+ * Robert Schwebel, Pengutronix, r.schwebel@pengutronix.de.
+ *
+ * Configuration for the Cogent CSB226 board. For details see
+ * http://www.cogcomp.com/csb_csb226.htm
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * include/configs/csb226.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * If we are developing, we might want to start ppcboot from ram
+ * so we MUST NOT initialize critical regs like mem-timing ...
+ */
+#undef CONFIG_INIT_CRITICAL /* undef for developing */
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+#define CONFIG_PXA250 1 /* This is an PXA250 CPU */
+#define CONFIG_CSB226 1 /* on a CSB226 board */
+
+#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
+ /* for timer/console/ethernet */
+/*
+ * Size of malloc() pool; this lives below the uppermost 128 KiB which are
+ * used for the RAM copy of the ppcboot code
+ *
+ + FIXME: the documentation says that this has to be CFG_MALLOC_LEN ???
+ */
+#define CONFIG_MALLOC_SIZE (CFG_ENV_SIZE + 128*1024)
+
+/*
+ * Hardware drivers
+ */
+
+/*
+ * select serial console configuration
+ */
+#define CONFIG_FFUART 1 /* we use FFUART on CSB226 */
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+
+#define CONFIG_BAUDRATE 115200
+
+#define CONFIG_COMMANDS (CONFIG_CMD_DFL & ~CFG_CMD_NET)
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+#define CONFIG_BOOTDELAY 10
+#define CONFIG_BOOTARGS "root=ramfs devfs=mount console=ttySA0,115200"
+#define CONFIG_ETHADDR FF:FF:FF:FF:FF:FF
+#define CONFIG_NETMASK 255.255.255.0
+#define CONFIG_IPADDR 192.168.1.56
+#define CONFIG_SERVERIP 192.168.1.2
+#define CONFIG_BOOTCOMMAND "FIXME"
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */
+#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
+#endif
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP /* undef to save memory */
+#define CFG_PROMPT "=> " /* Monitor Command Prompt */
+#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS 16 /* max number of command args */
+#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
+
+#define CFG_MEMTEST_START 0xa0400000 /* memtest works on */
+#define CFG_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */
+
+#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */
+
+#define CFG_LOAD_ADDR 0xa8000000 /* default load address */
+ /* RS: where is this documented? */
+
+#define CFG_HZ 3686400 /* incrementer freq: 3.6864 MHz */
+ /* RS: the oscillator is actually 3680130?? */
+#define CFG_CPUSPEED 0x141 /* set core clock to 200/200/100 MHz */
+
+ /* valid baudrates */
+#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
+
+/*
+ * Stack sizes
+ *
+ * The stack sizes are set up in start.S using the settings below
+ */
+#define CONFIG_STACKSIZE (128*1024) /* regular stack */
+#ifdef CONFIG_USE_IRQ
+#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */
+#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */
+#endif
+
+/*
+ * Physical Memory Map
+ */
+#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
+#define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */
+#define PHYS_SDRAM_1_SIZE 0x02000000 /* 32 MB */
+
+#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */
+#define PHYS_FLASH_SIZE 0x02000000 /* 32 MB */
+
+#define CFG_DRAM_BASE 0xa0000000
+#define CFG_DRAM_SIZE 0x04000000
+
+#define CFG_FLASH_BASE PHYS_FLASH_1
+
+/* #define FPGA_REGS_BASE_PHYSICAL 0x08000000 */ /* we don't need this on CSB226...? */
+
+/*
+ * GPIO settings
+ */
+#define CFG_GPSR0_VAL 0x00008000
+#define CFG_GPSR1_VAL 0x00FC0382
+#define CFG_GPSR2_VAL 0x0001FFFF
+#define CFG_GPCR0_VAL 0x00000000
+#define CFG_GPCR1_VAL 0x00000000
+#define CFG_GPCR2_VAL 0x00000000
+#define CFG_GPDR0_VAL 0x0060A800
+#define CFG_GPDR1_VAL 0x00FF0382
+#define CFG_GPDR2_VAL 0x0001C000
+#define CFG_GAFR0_L_VAL 0x98400000
+#define CFG_GAFR0_U_VAL 0x00002950
+#define CFG_GAFR1_L_VAL 0x000A9558
+#define CFG_GAFR1_U_VAL 0x0005AAAA
+#define CFG_GAFR2_L_VAL 0xA0000000
+#define CFG_GAFR2_U_VAL 0x00000002
+
+#define CFG_PSSR_VAL 0x20
+
+/*
+ * Memory settings
+ */
+#define CFG_MSC0_VAL 0x23F223F2
+#define CFG_MSC1_VAL 0x3FF1A441
+#define CFG_MSC2_VAL 0x7FF17FF1
+#define CFG_MDCNFG_VAL 0x00001AC9
+#define CFG_MDREFR_VAL 0x000BC018
+#define CFG_MDREFR_VAL_100 0x00018018
+#define CFG_MDMRS_VAL 0x00000000
+
+/*
+ * PCMCIA and CF Interfaces
+ */
+#define CFG_MECR_VAL 0x00000000
+#define CFG_MCMEM0_VAL 0x00010504
+#define CFG_MCMEM1_VAL 0x00010504
+#define CFG_MCATT0_VAL 0x00010504
+#define CFG_MCATT1_VAL 0x00010504
+#define CFG_MCIO0_VAL 0x00004715
+#define CFG_MCIO1_VAL 0x00004715
+
+#define _LED 0x08000010
+#define LED_BLANK (0x08000040)
+
+/*
+ * FLASH and environment organization
+ */
+#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
+#define CFG_MAX_FLASH_SECT 128 /* max number of sect. on one chip */
+
+/* timeout values are in ticks */
+#define CFG_FLASH_ERASE_TOUT (2*CFG_HZ) /* Timeout for Flash Erase */
+#define CFG_FLASH_WRITE_TOUT (2*CFG_HZ) /* Timeout for Flash Write */
+
+/* FIXME */
+#define CFG_ENV_IS_IN_FLASH 1
+#define CFG_ENV_ADDR (PHYS_FLASH_1 + 0x1C000)
+ /* Addr of Environment Sector */
+#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
+
+
+/*
+ * FPGA Offsets
+ */
+/*
+#define WHOAMI_OFFSET 0x00
+#define HEXLED_OFFSET 0x10
+#define BLANKLED_OFFSET 0x40
+#define DISCRETELED_OFFSET 0x40
+#define CNFG_SWITCHES_OFFSET 0x50
+#define USER_SWITCHES_OFFSET 0x60
+#define MISC_WR_OFFSET 0x80
+#define MISC_RD_OFFSET 0x90
+#define INT_MASK_OFFSET 0xC0
+#define INT_CLEAR_OFFSET 0xD0
+#define GP_OFFSET 0x100
+*/
+
+#endif /* __CONFIG_H */
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */
-#if 0
#define CONFIG_WATCHDOG 1 /* watchdog enabled */
-#endif
#undef CONFIG_STATUS_LED /* Status LED disabled */
/*
* Hardware (CPM) I2C driver configuration
*/
-# define CFG_I2C_SPEED 100000 /* 100 kHz is supposed to work */
+# define CFG_I2C_SPEED 93000 /* 93 kHz is supposed to work */
# define CFG_I2C_SLAVE 0xFE
#endif /* CONFIG_HARD_I2C */
#define CFG_PIO_MODE 0 /* IDE interface in PIO Mode 0 */
-#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
+#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
#define CFG_FLASH_ERASE_TOUT 180000 /* Timeout for Flash Erase (in ms) */
#define CFG_FLASH_WRITE_TOUT 600 /* Timeout for Flash Write (in ms) */
-#if 0
-/* Start port with environment in flash; switch to EEPROM later */
+#if 1
+/* Put environment in flash which is much faster to boot */
#define CFG_ENV_IS_IN_FLASH 1
#define CFG_ENV_ADDR 0x407E0000 /* Address of Environment Sector */
-#define CFG_ENV_SIZE 0x1000 /* Total Size of Environment */
+#define CFG_ENV_SIZE 0x2000 /* Total Size of Environment */
#define CFG_ENV_SECT_SIZE 0x20000 /* we have BIG sectors only :-( */
#else
-/* Final version: environment in EEPROM */
+/* Environment in EEPROM */
#define CFG_ENV_IS_IN_EEPROM 1
#define CFG_ENV_OFFSET 0
#define CFG_ENV_SIZE 2048
projects / users / rw / ppcboot.git / commitdiff