drm/radeon: Use RMW accessors for changing LNKCTL2

Convert open coded RMW accesses for LNKCTL2 to use
pcie_capability_clear_and_set_word() which makes its easier to
understand what the code tries to do.

LNKCTL2 is not really owned by any driver because it is a collection of
control bits that PCI core might need to touch. RMW accessors already
have support for proper locking for a selected set of registers
(LNKCTL2 is not yet among them but likely will be in the future) to
avoid losing concurrent updates.

Acked-by: Alex Deucher <alexander.deucher@amd.com>
Suggested-by: Lukas Wunner <lukas@wunner.de>
Signed-off-by: Ilpo Järvinen <ilpo.jarvinen@linux.intel.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/radeon/cik.c b/drivers/gpu/drm/radeon/cik.c
index 10be30366c2bf8e33eda0888d970c80106f9107c..b5e96a8fc2c16248ed0f016bc2987dc0524d9fc1 100644 (file)
--- a/drivers/gpu/drm/radeon/cik.c
+++ b/drivers/gpu/drm/radeon/cik.c
@@ -9592,28 +9592,18 @@ static void cik_pcie_gen3_enable(struct radeon_device *rdev)
                                                                   PCI_EXP_LNKCTL_HAWD);
 
                                /* linkctl2 */
-                               pcie_capability_read_word(root, PCI_EXP_LNKCTL2,
-                                                         &tmp16);
-                               tmp16 &= ~(PCI_EXP_LNKCTL2_ENTER_COMP |
-                                          PCI_EXP_LNKCTL2_TX_MARGIN);
-                               tmp16 |= (bridge_cfg2 &
-                                         (PCI_EXP_LNKCTL2_ENTER_COMP |
-                                          PCI_EXP_LNKCTL2_TX_MARGIN));
-                               pcie_capability_write_word(root,
-                                                          PCI_EXP_LNKCTL2,
-                                                          tmp16);
-
-                               pcie_capability_read_word(rdev->pdev,
-                                                         PCI_EXP_LNKCTL2,
-                                                         &tmp16);
-                               tmp16 &= ~(PCI_EXP_LNKCTL2_ENTER_COMP |
-                                          PCI_EXP_LNKCTL2_TX_MARGIN);
-                               tmp16 |= (gpu_cfg2 &
-                                         (PCI_EXP_LNKCTL2_ENTER_COMP |
-                                          PCI_EXP_LNKCTL2_TX_MARGIN));
-                               pcie_capability_write_word(rdev->pdev,
-                                                          PCI_EXP_LNKCTL2,
-                                                          tmp16);
+                               pcie_capability_clear_and_set_word(root, PCI_EXP_LNKCTL2,
+                                                                  PCI_EXP_LNKCTL2_ENTER_COMP |
+                                                                  PCI_EXP_LNKCTL2_TX_MARGIN,
+                                                                  bridge_cfg2 |
+                                                                  (PCI_EXP_LNKCTL2_ENTER_COMP |
+                                                                   PCI_EXP_LNKCTL2_TX_MARGIN));
+                               pcie_capability_clear_and_set_word(rdev->pdev, PCI_EXP_LNKCTL2,
+                                                                  PCI_EXP_LNKCTL2_ENTER_COMP |
+                                                                  PCI_EXP_LNKCTL2_TX_MARGIN,
+                                                                  gpu_cfg2 |
+                                                                  (PCI_EXP_LNKCTL2_ENTER_COMP |
+                                                                   PCI_EXP_LNKCTL2_TX_MARGIN));
 
                                tmp = RREG32_PCIE_PORT(PCIE_LC_CNTL4);
                                tmp &= ~LC_SET_QUIESCE;
@@ -9627,15 +9617,15 @@ static void cik_pcie_gen3_enable(struct radeon_device *rdev)
        speed_cntl &= ~LC_FORCE_DIS_SW_SPEED_CHANGE;
        WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl);
 
-       pcie_capability_read_word(rdev->pdev, PCI_EXP_LNKCTL2, &tmp16);
-       tmp16 &= ~PCI_EXP_LNKCTL2_TLS;
+       tmp16 = 0;
        if (speed_cap == PCIE_SPEED_8_0GT)
                tmp16 |= PCI_EXP_LNKCTL2_TLS_8_0GT; /* gen3 */
        else if (speed_cap == PCIE_SPEED_5_0GT)
                tmp16 |= PCI_EXP_LNKCTL2_TLS_5_0GT; /* gen2 */
        else
                tmp16 |= PCI_EXP_LNKCTL2_TLS_2_5GT; /* gen1 */
-       pcie_capability_write_word(rdev->pdev, PCI_EXP_LNKCTL2, tmp16);
+       pcie_capability_clear_and_set_word(rdev->pdev, PCI_EXP_LNKCTL2,
+                                          PCI_EXP_LNKCTL2_TLS, tmp16);
 
        speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
        speed_cntl |= LC_INITIATE_LINK_SPEED_CHANGE;

diff --git a/drivers/gpu/drm/radeon/si.c b/drivers/gpu/drm/radeon/si.c
index 93f197d96d8f7ea084db4d18fb279ff27a40d6b7..15759c8ca5b7ba1babbbf68545bb862a2889bb33 100644 (file)
--- a/drivers/gpu/drm/radeon/si.c
+++ b/drivers/gpu/drm/radeon/si.c
@@ -7174,28 +7174,18 @@ static void si_pcie_gen3_enable(struct radeon_device *rdev)
                                                                   PCI_EXP_LNKCTL_HAWD);
 
                                /* linkctl2 */
-                               pcie_capability_read_word(root, PCI_EXP_LNKCTL2,
-                                                         &tmp16);
-                               tmp16 &= ~(PCI_EXP_LNKCTL2_ENTER_COMP |
-                                          PCI_EXP_LNKCTL2_TX_MARGIN);
-                               tmp16 |= (bridge_cfg2 &
-                                         (PCI_EXP_LNKCTL2_ENTER_COMP |
-                                          PCI_EXP_LNKCTL2_TX_MARGIN));
-                               pcie_capability_write_word(root,
-                                                          PCI_EXP_LNKCTL2,
-                                                          tmp16);
-
-                               pcie_capability_read_word(rdev->pdev,
-                                                         PCI_EXP_LNKCTL2,
-                                                         &tmp16);
-                               tmp16 &= ~(PCI_EXP_LNKCTL2_ENTER_COMP |
-                                          PCI_EXP_LNKCTL2_TX_MARGIN);
-                               tmp16 |= (gpu_cfg2 &
-                                         (PCI_EXP_LNKCTL2_ENTER_COMP |
-                                          PCI_EXP_LNKCTL2_TX_MARGIN));
-                               pcie_capability_write_word(rdev->pdev,
-                                                          PCI_EXP_LNKCTL2,
-                                                          tmp16);
+                               pcie_capability_clear_and_set_word(root, PCI_EXP_LNKCTL2,
+                                                                  PCI_EXP_LNKCTL2_ENTER_COMP |
+                                                                  PCI_EXP_LNKCTL2_TX_MARGIN,
+                                                                  bridge_cfg2 &
+                                                                  (PCI_EXP_LNKCTL2_ENTER_COMP |
+                                                                   PCI_EXP_LNKCTL2_TX_MARGIN));
+                               pcie_capability_clear_and_set_word(rdev->pdev, PCI_EXP_LNKCTL2,
+                                                                  PCI_EXP_LNKCTL2_ENTER_COMP |
+                                                                  PCI_EXP_LNKCTL2_TX_MARGIN,
+                                                                  gpu_cfg2 &
+                                                                  (PCI_EXP_LNKCTL2_ENTER_COMP |
+                                                                   PCI_EXP_LNKCTL2_TX_MARGIN));
 
                                tmp = RREG32_PCIE_PORT(PCIE_LC_CNTL4);
                                tmp &= ~LC_SET_QUIESCE;
@@ -7209,15 +7199,15 @@ static void si_pcie_gen3_enable(struct radeon_device *rdev)
        speed_cntl &= ~LC_FORCE_DIS_SW_SPEED_CHANGE;
        WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl);
 
-       pcie_capability_read_word(rdev->pdev, PCI_EXP_LNKCTL2, &tmp16);
-       tmp16 &= ~PCI_EXP_LNKCTL2_TLS;
+       tmp16 = 0;
        if (speed_cap == PCIE_SPEED_8_0GT)
                tmp16 |= PCI_EXP_LNKCTL2_TLS_8_0GT; /* gen3 */
        else if (speed_cap == PCIE_SPEED_5_0GT)
                tmp16 |= PCI_EXP_LNKCTL2_TLS_5_0GT; /* gen2 */
        else
                tmp16 |= PCI_EXP_LNKCTL2_TLS_2_5GT; /* gen1 */
-       pcie_capability_write_word(rdev->pdev, PCI_EXP_LNKCTL2, tmp16);
+       pcie_capability_clear_and_set_word(rdev->pdev, PCI_EXP_LNKCTL2,
+                                          PCI_EXP_LNKCTL2_TLS, tmp16);
 
        speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
        speed_cntl |= LC_INITIATE_LINK_SPEED_CHANGE;