]> www.infradead.org Git - users/jedix/linux-maple.git/commitdiff
arm64: dts: ti: k3-j721s2: Add PCIe ctrl node to scm_conf region
authorAndrew Davis <afd@ti.com>
Wed, 2 Apr 2025 11:32:00 +0000 (17:02 +0530)
committerNishanth Menon <nm@ti.com>
Fri, 18 Apr 2025 18:28:12 +0000 (13:28 -0500)
This region is used for controlling the function of the PCIe IP. It is
compatible with "ti,j784s4-pcie-ctrl", add this here and use it with
the PCIe node.

Signed-off-by: Andrew Davis <afd@ti.com>
[j-choudhary@ti.com: Add changes to k3-am68-sk-base-board-pcie1-ep.dtso]
Signed-off-by: Jayesh Choudhary <j-choudhary@ti.com>
Reviewed-by: Siddharth Vadapalli <s-vadapalli@ti.com>
Link: https://lore.kernel.org/r/20250402113201.151195-5-j-choudhary@ti.com
Signed-off-by: Nishanth Menon <nm@ti.com>
arch/arm64/boot/dts/ti/k3-am68-sk-base-board-pcie1-ep.dtso
arch/arm64/boot/dts/ti/k3-j721s2-evm-pcie1-ep.dtso
arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi

index 455736e378ccfe1d82dbdd470b15e17e639d389f..ba521d6611449c6f0b30b50c711057d160bd2091 100644 (file)
@@ -48,6 +48,6 @@
                dma-coherent;
                phys = <&serdes0_pcie_link>;
                phy-names = "pcie-phy";
-               ti,syscon-pcie-ctrl = <&scm_conf 0x074>;
+               ti,syscon-pcie-ctrl = <&pcie1_ctrl 0x0>;
        };
 };
index 5ff390915b75b938fbf568feac665778af13318d..8c2cd99cf2b42baddcb2b5fec6244741ba05f62f 100644 (file)
@@ -38,7 +38,7 @@
                reg-names = "intd_cfg", "user_cfg", "reg", "mem";
                interrupt-names = "link_state";
                interrupts = <GIC_SPI 330 IRQ_TYPE_EDGE_RISING>;
-               ti,syscon-pcie-ctrl = <&scm_conf 0x074>;
+               ti,syscon-pcie-ctrl = <&pcie1_ctrl 0x0>;
                max-link-speed = <3>;
                num-lanes = <1>;
                power-domains = <&k3_pds 276 TI_SCI_PD_EXCLUSIVE>;
index 92bf48fdbeba45ecca8c854db5f72fd3666239c5..c0c2b95d4652bbe91bf6982f0a21324f8a461a63 100644 (file)
                        #phy-cells = <1>;
                };
 
+               pcie1_ctrl: pcie-ctrl@74 {
+                       compatible = "ti,j784s4-pcie-ctrl", "syscon";
+                       reg = <0x74 0x4>;
+               };
+
                serdes_ln_ctrl: mux-controller@80 {
                        compatible = "reg-mux";
                        reg = <0x80 0x10>;
                interrupt-names = "link_state";
                interrupts = <GIC_SPI 330 IRQ_TYPE_EDGE_RISING>;
                device_type = "pci";
-               ti,syscon-pcie-ctrl = <&scm_conf 0x074>;
+               ti,syscon-pcie-ctrl = <&pcie1_ctrl 0x0>;
                max-link-speed = <3>;
                num-lanes = <4>;
                power-domains = <&k3_pds 276 TI_SCI_PD_EXCLUSIVE>;