This region is used for controlling the function of the PCIe IP. It is
compatible with "ti,j784s4-pcie-ctrl", add this here and use it with
the PCIe node.
Signed-off-by: Andrew Davis <afd@ti.com>
[j-choudhary@ti.com: Add changes to k3-am68-sk-base-board-pcie1-ep.dtso]
Signed-off-by: Jayesh Choudhary <j-choudhary@ti.com>
Reviewed-by: Siddharth Vadapalli <s-vadapalli@ti.com>
Link: https://lore.kernel.org/r/20250402113201.151195-5-j-choudhary@ti.com
Signed-off-by: Nishanth Menon <nm@ti.com>
dma-coherent;
phys = <&serdes0_pcie_link>;
phy-names = "pcie-phy";
- ti,syscon-pcie-ctrl = <&scm_conf 0x074>;
+ ti,syscon-pcie-ctrl = <&pcie1_ctrl 0x0>;
};
};
reg-names = "intd_cfg", "user_cfg", "reg", "mem";
interrupt-names = "link_state";
interrupts = <GIC_SPI 330 IRQ_TYPE_EDGE_RISING>;
- ti,syscon-pcie-ctrl = <&scm_conf 0x074>;
+ ti,syscon-pcie-ctrl = <&pcie1_ctrl 0x0>;
max-link-speed = <3>;
num-lanes = <1>;
power-domains = <&k3_pds 276 TI_SCI_PD_EXCLUSIVE>;
#phy-cells = <1>;
};
+ pcie1_ctrl: pcie-ctrl@74 {
+ compatible = "ti,j784s4-pcie-ctrl", "syscon";
+ reg = <0x74 0x4>;
+ };
+
serdes_ln_ctrl: mux-controller@80 {
compatible = "reg-mux";
reg = <0x80 0x10>;
interrupt-names = "link_state";
interrupts = <GIC_SPI 330 IRQ_TYPE_EDGE_RISING>;
device_type = "pci";
- ti,syscon-pcie-ctrl = <&scm_conf 0x074>;
+ ti,syscon-pcie-ctrl = <&pcie1_ctrl 0x0>;
max-link-speed = <3>;
num-lanes = <4>;
power-domains = <&k3_pds 276 TI_SCI_PD_EXCLUSIVE>;