* Misc minor bug fixes, like cache line size for 82xx systems

* Made Sandpoint8240 compile
  Patch by Jim Thompson, 5 Nov 2001
* Improving LCD driver
* Improving LWMON keyboard handling

diff --git a/CHANGELOG b/CHANGELOG
index 3b1dba746a8f0c108fdddd6d608ea7fe6e63635e..1b21e087ef2e2cdab0300e585f3f1847524a2401 100644 (file)
--- a/CHANGELOG
+++ b/CHANGELOG
@@ -59,8 +59,13 @@ Modifications for 1.1.0:
 * Add LCD driver for MPC823;
   changed initialization sequence to get display early.
 
+* Made Sandpoint8240 compile
+  Patch by Jim Thompson, 5 Nov 2001
+
 * Minor code reordering, cleanup and reformatting
 
+* Misc minor bug fixes, like cache line size for 82xx systems
+
 * Fix bug in cpu/mpc8xx/i2c.c: when used to read environment from
   EEPROM, it tries to access serial console before port was
   initialized
@@ -105,7 +110,8 @@ Modifications for 1.1.0:
   Patch by Thomas Lange, 18 Oct 2001
 
 * Extend LWMON keyboard driver to allow for more than one key-coded
-  pre-boot command (we now support an unlimited number of keys)
+  pre-boot command (we now support an unlimited number of keys);
+  added special "debug mode" which enables LCD display early
 
 * Added "hush" shell (from Busybox) as alternative command line
   interpreter, thus enabling powerful command line syntax like

diff --git a/README b/README
index ab27123d4910d0ab185246291902760700a9a8f7..e6fd1c5475ee815f4f62814dfbe4cfa4d62b93ca 100644 (file)
--- a/README
+++ b/README
@@ -314,7 +314,7 @@ The following options need to be configured:
                withing "Boot Delay" after reset.
 
                CONFIG_BOOTARGS
-               This can be used to pass arguments to the bootm command. 
+               This can be used to pass arguments to the bootm command.
                The value of CONFIG_BOOTARGS goes into the environment
                value "bootargs".
 
@@ -469,13 +469,56 @@ The following options need to be configured:
 - Video support:
                CONFIG_VIDEO
 
-                Define this to enable  video  support  (for  instance
-               output to LCD).
+                Define this to enable video support (for output to
+                video).
 
                CONFIG_VIDEO_CT69000
 
                Enable Chips & Technologies 69000 Video chip
 
+- LCD Support: CONFIG_LCD
+
+                Define this to enable LCD support (for output to LCD
+                display); also select one of the supported displays
+                by defining one of these:
+
+               CONFIG_NEC_NL6648AC33:
+
+                        NEC NL6648AC33-18. Active, color, single scan.
+
+               CONFIG_NEC_NL6648BC20
+
+                        NEC NL6648BC20-08. 6.5", 640x480.
+                       Active, color, single scan.
+
+               CONFIG_SHARP_16x9
+
+                       Sharp 320x240. Active, color, single scan.
+                       It isn't 16x9, and I am not sure what it is.
+
+               CONFIG_SHARP_LQ64D341
+
+                       Sharp LQ64D341 display, 640x480.
+                       Active, color, single scan.
+
+               CONFIG_HLD1045
+
+                       HLD1045 display, 640x480.
+                       Active, color, single scan.
+
+               CONFIG_OPTREX_BW
+
+                       Optrex   CBL50840-2 NF-FW 99 22 M5
+                       or
+                       Hitachi  LMG6912RPFC-00T
+                       or
+                       Hitachi  SP14Q002
+
+                       320x240. Black & white.
+
+                Normally display is black on white background; define
+                CFG_WHITE_ON_BLACK to get it inverted.
+
 - Ethernet address:
                CONFIG_ETHADDR
                CONFIG_ETH2ADDR
@@ -564,7 +607,7 @@ The following options need to be configured:
                 version information (PPCBOOT_VERSION)
 
 - Vendor Parameter Protection:
-                
+
                 PPCBoot considers the values of the environment
                 variables "serial#" (Board Serial Number) and
                 "ethaddr" (Ethernet Address) to bb parameters that
@@ -642,7 +685,7 @@ The following options need to be configured:
                 If undefined, you get the old, much simpler behaviour
                with a somewhat smapper memory footprint.
 
-               
+
                CFG_PROMPT_HUSH_PS2
 
                 This defines the secondary prompt string, which is

diff --git a/board/lwmon/README.keybd b/board/lwmon/README.keybd
index 926b2e609b2e6a76daec490c2fd4de8c99b83d58..5abc2d337e07aec48ffc905a35c789a347ffa0c4 100644 (file)
--- a/board/lwmon/README.keybd
+++ b/board/lwmon/README.keybd
@@ -35,7 +35,10 @@ Tasten (-kombinationen) festgelegt werden:
 
 Ist "magic_keys" NICHT definiert, so wird nur die in der Environment-
 Variablen "key_magic" codierte  Tasten  (-kombination)  geprüft,  und
-ggf. der Inhalt der Environment-Variablen "key_cmd" ausgeführt.
+ggf.  der  Inhalt der Environment-Variablen "key_cmd" ausgeführt (ge-
+nauer: der Inhalt von "key_cmd" wird der Variablen "preboot" zugewie-
+sen, die ausgeführt wird, unmittelbar bevor die interaktive Kommando-
+interpretation beginnt).
 
 Enthält "magic_keys" z. B.  die  Zeichenkette  "0123CB*",  so  werden
 nacheinander folgende Aktionen ausgeführt:
@@ -52,6 +55,13 @@ nacheinander folgende Aktionen ausgef
        key_magicA      ==>     key_cmdA
        key_magic*      ==>     key_cmd*
 
+Hinweis: sobald ein aktivierter Tastencode erkannt  wurde,  wird  die
+Bearbeitung  abgebrochen; es wird daher höchstens eines der definier-
+ten Kommandos ausgeführt, wobei die Priorität durch  die  Suchreihen-
+folge  festgelegt wird, also durch die Reihenfolge der Zeichen in der
+Varuiablen "magic_keys".
+
+
 Die Codierung der Tasten, die beim Booten gedrückt werden müssen, um
 eine Funktion auszulösen, erfolgt nach der Tastaturtabelle.
 
@@ -74,3 +84,44 @@ Praktisch k
 somit stets ohne jede User-Interaktion automatisch booten, außer,
 wenn die beiden Tasten "F1" und "F2" beim Booten gedrückt werden:
 dann würde ein Boot-Delay von 30 Sekunden eingefügt.
+
+
+Hinweis: dem Zeichen '#' kommt innerhalb von "magic_keys" eine beson-
+dere Bedeutung zu: die dadurch definierte  Key-Sequenz  schaltet  den
+Monitor in den "Debug-Modus" - das bedeutet zunächst, daß alle weite-
+ren  Meldungen  von  PPCBoot  über das LCD-Display ausgegeben werden;
+außerdem kann man durch das mit dieser  Tastenkombination  verknüpfte
+Kommando  z. B. die Linux-Bootmeldungen ebenfalls auf das LCD-Display
+legen, so daß der Boot-Vorgang direkt und  ohne  weitere  Hilfsmittel
+analysiert werden kann.
+
+Beispiel:
+
+In PPCBoot werden folgende Environment-Variablen  gesetzt  und  abge-
+speichert:
+
+(1)    => setenv magic_keys 01234#X
+(2)    => setenv key_cmd# setenv addfb setenv bootargs \\$(bootargs) console=tty0 console=ttyS1,\\$(baudrate)
+(3)    => setenv nfsargs setenv bootargs root=/dev/nfs rw nfsroot=\$(serverip):\$(rootpath)
+(4)    => setenv addip setenv bootargs \$(bootargs) ip=\$(ipaddr):\$(serverip):\$(gatewayip):\$(netmask):\$(hostname)::off panic=1
+(5)    => setenv addfb setenv bootargs \$(bootargs) console=ttyS1,\$(baudrate)
+(6)    => setenv bootcmd bootp\;run nfsargs\;run addip\;run addfb\;bootm
+
+Hierbei wird die Linux Commandline (in der Variablen  "bootargs")  im
+Boot-Kommando  "bootcmd"  (6)  schrittweise zusammengesetzt: zunächst
+werden die für Root-Filesystem über NFS erforderlichen  Optionen  ge-
+setzt  ("run  nfsargs", vgl. (3)), dann die Netzwerkkonfiguration an-
+gefügt ("run addip", vgl. (4)),  und  schließlich  die  Systemconsole
+definiert ("run addfb").
+
+Dabei wird im Normalfall die Definition (5) verwendt; wurde llerdings
+beim Reset die entsprechende Taste gedrückt gehalten, so  wird  diese
+Definition  bei der Ausführung des in (2) definierten Kommandos über-
+schrieben, so daß Linux die Bootmeldungen auch über das  Framebuffer-
+Device (=LCD-Display) ausgibt.
+
+Beachten Sie die Verdoppelung der '\'-Escapes in der  Definition  von
+"key_cmd#" - diese ist erforderlich, weil der String _zweimal_ inter-
+pretiert  wird:  das  erste  Mal  bei der Eingabe von "key_cmd#", das
+zweite Mal, wenn der String (als  Inhalt  von  "preboot")  ausgeführt
+wird.

diff --git a/board/lwmon/lwmon.c b/board/lwmon/lwmon.c
index e8159d8cc0930026e43f6cfb4222254768da7c03..8fc8c43ffdf2382884fdf17e255f01f7cfb12683 100644 (file)
--- a/board/lwmon/lwmon.c
+++ b/board/lwmon/lwmon.c
@@ -297,15 +297,15 @@ void      reset_phy(void)
 /* maximum number of "magic" key codes that can be assigned */
 
 static uchar kbd_addr = CFG_I2C_KEYBD_ADDR;
-static uchar kbd_data [KEYBD_DATALEN];
-static uchar keybd_env[2*KEYBD_DATALEN+1];
 
-#ifdef CONFIG_PREBOOT
 static uchar *key_match (uchar *);
-#endif
+
+#define        KEYBD_SET_DEBUGMODE     '#'     /* Magic key to enable debug output */
 
 void misc_init_r (bd_t *bd)
 {
+       uchar kbd_data [KEYBD_DATALEN];
+       uchar keybd_env[2*KEYBD_DATALEN+1];
        uchar val, errcd;
        uchar *str;
        int i;
@@ -334,6 +334,16 @@ void misc_init_r (bd_t *bd)
                return;
        }
 
+        /*
+         * Now we know that we have a working  keyboard,  so  disable
+         * all output to the LCD except when a key press is detected.
+        */
+
+       if ((console_assign (stdout, "serial") < 0) ||
+           (console_assign (stderr, "serial") < 0) ) {
+               printf ("Can't assign serial port as output device\n");
+       }
+
        /* Read Version */
        val = KEYBD_CMD_READ_VERSION;
        i2c_write (&kbd_addr, 1, &val, 1);
@@ -350,19 +360,33 @@ void misc_init_r (bd_t *bd)
        }
        setenv ("keybd", keybd_env);
 
+       str = strdup (key_match(kbd_data));             /* decode keys */
+#ifdef KEYBD_SET_DEBUGMODE
+       if (kbd_data[0] == KEYBD_SET_DEBUGMODE) {       /* set debug mode */
+               if ((console_assign (stdout, "lcd") < 0) ||
+                   (console_assign (stderr, "lcd") < 0) ) {
+                       printf ("Can't assign LCD display as output device\n");
+               }
+       }
+#endif /* KEYBD_SET_DEBUGMODE */
 #ifdef CONFIG_PREBOOT  /* automatically configure "preboot" command on key match */
-       str = strdup (key_match(kbd_data));
        setenv ("preboot", str); /* set or delete definition */
+#endif /* CONFIG_PREBOOT */
        if (str != NULL) {
                free (str);
        }
-#endif /* CONFIG_PREBOOT */
 }
 
 /*-----------------------------------------------------------------------
  * Check if pressed key(s) match magic sequence,
  * and return the command string associated with that key(s).
  *
+ * If no key press was decoded, NULL is returned.
+ *
+ * Note: the first character of the argument will be overwritten with
+ * the "magic charcter code" of the decoded key(s), or '\0'.
+ *
+ *
  * Note: the string points to static environment data and must be
  * saved before you call any function that modifies the environment.
  */
@@ -452,12 +476,14 @@ static uchar *key_match (uchar *kbd_data)
                        printf ("### Set PREBOOT to $(%s): \"%s\"\n",
                                cmd_name, cmd ? cmd : "<<NULL>>");
 #endif
+                       *kbd_data = *suffix;
                        return (cmd);
                }
        }
 #if 0
        printf ("### Delete PREBOOT\n");
 #endif
+       *kbd_data = '\0';
        return (NULL);
 }
 #endif /* CONFIG_PREBOOT */
@@ -502,6 +528,8 @@ int do_pic (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[])
 /* Read Keyboard status */
 int do_kbd (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[])
 {
+       uchar kbd_data [KEYBD_DATALEN];
+       uchar keybd_env[2*KEYBD_DATALEN+1];
        uchar val;
        int i;
 

diff --git a/board/sandpoint/flash.c b/board/sandpoint/flash.c
index 83acd42113496807e51c4d368ad8b39688207a2d..fca01831254b8a58c93eb4574c99b9a03a398164 100644 (file)
--- a/board/sandpoint/flash.c
+++ b/board/sandpoint/flash.c
@@ -33,7 +33,9 @@ flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips    */
  * Functions
  */
 static int write_word (flash_info_t *info, ulong dest, ulong data);
+#if 0
 static void flash_get_offsets (ulong base, flash_info_t *info);
+#endif /* 0 */
 
 /*flash command address offsets*/
 
@@ -46,7 +48,9 @@ static void flash_get_offsets (ulong base, flash_info_t *info);
 /*-----------------------------------------------------------------------
  */
 
+#if 0
 static int byte_parity_odd(unsigned char x) __attribute__ ((const));
+#endif /* 0 */
 static unsigned long flash_id(unsigned char mfct, unsigned char chip) __attribute__ ((const));
 
 typedef struct
@@ -55,8 +59,7 @@ typedef struct
   unsigned short intval;
 } map_entry;
 
-
-
+#if 0
 static int
 byte_parity_odd(unsigned char x)
 {
@@ -65,6 +68,7 @@ byte_parity_odd(unsigned char x)
   x ^= x >> 1;
   return (x & 0x1) != 0;
 }
+#endif /* 0 */
 
 
 
@@ -169,6 +173,7 @@ flash_init(void)
     return flash_info[0].size;
 }
 
+#if 0
 static void
 flash_get_offsets (ulong base, flash_info_t *info)
 {
@@ -202,6 +207,7 @@ flash_get_offsets (ulong base, flash_info_t *info)
     }
 
 }
+#endif /* 0 */
 
 /*-----------------------------------------------------------------------
  */

diff --git a/board/sandpoint/serial.c b/board/sandpoint/serial.c
index e09dac063cebd5358a21d966c401e8f0acbfd754..3db2e2fbcc774dd15c3376521618284f9982849c 100644 (file)
--- a/board/sandpoint/serial.c
+++ b/board/sandpoint/serial.c
@@ -40,8 +40,8 @@ serial_init (unsigned long dummy, int baudrate)
 {
   init_data_t * const idata = IDATA;
   const int clock_divisor = 115200/baudrate;
-  /* initialise_ns87308(); */
-  idata->console_addr = NS16550_init(0, clock_divisor);
+  /* initialize_ns87308(); */
+  idata->console_addr = (void *)NS16550_init(0, clock_divisor);
 }
 
 void

diff --git a/include/bmp_logo.h b/include/bmp_logo.h
index c72287a16ee78abca4be135b5617fe8ab52a645f..265f744d0e345619ea3eccdda16292b0a099824e 100644 (file)
--- a/include/bmp_logo.h
+++ b/include/bmp_logo.h
@@ -11,982 +11,1938 @@
 
 #define BMP_LOGO_WIDTH         160
 #define BMP_LOGO_HEIGHT                96
-#define BMP_LOGO_COLORS                3
+#define BMP_LOGO_COLORS                31
 #define BMP_LOGO_OFFSET                16
 
 unsigned short bmp_logo_palette[] = {
-#ifndef        CFG_WHITE_ON_BLACK
-       0x0343, /* grey */
-       0x0fb3, /* yellow */
-       0x0fff, /* white */
-#else
-       0x0CCC, /* light grey */ 
-       0x0FB3, /* yellow */
-       0x0000, /* black */
-#endif
+       0x0343,  0x0454,  0x0565,  0x0565,  0x0676,  0x0787,  0x0898,  0x0999,
+       0x0AAA,  0x0ABA,  0x0BCB,  0x0CCC,  0x0DDD,  0x0EEE,  0x0FFF,  0x0FB3,
+       0x0FB4,  0x0FC4,  0x0FC5,  0x0FC6,  0x0FD7,  0x0FD8,  0x0FD9,  0x0FDA,
+       0x0FEA,  0x0FEB,  0x0FEC,  0x0FFD,  0x0FFE,  0x0FFF,  0x0FFF,  
 };
 
 unsigned char bmp_logo_bitmap[] = {
-       18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18,
-       18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 16,
-       16, 16, 16, 16, 16, 16, 16, 18, 18, 18, 18, 18, 18, 18, 18, 18,
-       18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18,
-       18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18,
-       18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18,
-       18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18,
-       18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18,
-       18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18,
-       18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18,
-       18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18,
-       18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 16,
-       16, 16, 16, 16, 16, 16, 16, 18, 18, 18, 18, 18, 18, 18, 18, 18,
-       18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18,
-       18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18,
-       18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18,
-       18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18,
-       18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18,
-       18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18,
-       18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18,
-       18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18,
-       18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 16,
-       16, 16, 16, 16, 16, 16, 16, 18, 18, 18, 18, 18, 18, 18, 18, 18,
-       18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18,
-       18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18,
-       18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18,
-       18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18,
-       18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18,
-       18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18,
-       18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18,
-       18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18,
-       18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 16,
-       16, 16, 16, 16, 16, 16, 16, 18, 18, 18, 18, 18, 18, 18, 18, 18,
-       18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18,
-       18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18,
-       18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18,
-       18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18,
-       18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18,
-       18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18,
-       18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18,
-       18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18,
-       18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 16,
-       16, 16, 16, 16, 16, 16, 16, 18, 18, 18, 18, 18, 18, 18, 18, 18,
-       18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18,
-       18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18,
-       18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18,
-       18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18,
-       18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18,
-       18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18,
-       18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18,
-       18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18,
-       18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 16,
-       16, 16, 16, 16, 16, 16, 16, 18, 18, 18, 18, 18, 18, 18, 18, 18,
-       18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18,
-       18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18,
-       18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18,
-       18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18,
-       18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18,
-       18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18,
-       18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18,
-       18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18,
-       18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 16,
-       16, 16, 16, 16, 16, 16, 16, 18, 18, 18, 18, 18, 18, 18, 18, 18,
-       18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18,
-       18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18,
-       18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18,
-       18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18,
-       18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18,
-       18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18,
-       18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18,
-       18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18,
-       18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 16,
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+       0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+       0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+       0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+       0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+       0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x16, 0x10, 0x10,
+       0x10, 0x14, 0x13, 0x10, 0x10, 0x10, 0x2E, 0x2E,
+
 };
 
 #endif /* __BMP_LOGO_H__ */

diff --git a/include/config_CU824.h b/include/config_CU824.h
index 1155b6f2df084b05f39cc78c5bb941366ede9f0e..1e8d8830faeb3656ffbc9bcc1ef3f5f4ee8f7a5f 100644 (file)
--- a/include/config_CU824.h
+++ b/include/config_CU824.h
@@ -49,9 +49,9 @@
 #define CONFIG_BAUDRATE                9600
 #define CFG_BAUDRATE_TABLE     { 9600, 19200, 38400, 57600, 115200 }
 
-#define CONFIG_CLOCKS_IN_MHZ   1       /* clocks passsed to Linux in MHz */
+#define CONFIG_CLOCKS_IN_MHZ   1       /* clocks passsed to Linux in MHz       */
 
-#define CONFIG_BOOTCOMMAND     "bootm FE020000"        /* autoboot command */
+#define CONFIG_BOOTCOMMAND     "bootm FE020000"        /* autoboot command     */
 #define CONFIG_BOOTDELAY       5
 
 #define CONFIG_COMMANDS                CONFIG_CMD_DFL
@@ -93,8 +93,8 @@
 #define CFG_MONITOR_LEN            (256 << 10) /* Reserve 256 kB for Monitor   */
 #define CFG_MALLOC_LEN     (128 << 10) /* Reserve 128 kB for malloc()  */
 
-#define CFG_MEMTEST_START   0x00004000 /* memtest works on      */
-#define CFG_MEMTEST_END            0x02000000  /* 0 ... 32 MB in DRAM   */
+#define CFG_MEMTEST_START   0x00004000 /* memtest works on             */
+#define CFG_MEMTEST_END            0x02000000  /* 0 ... 32 MB in DRAM          */
 
        /* Maximum amount of RAM.
         */
@@ -143,7 +143,7 @@
 
        /* Bit-field values for MCCR2.
         */
-#define CFG_REFINT         430     /* Refresh interval               */
+#define CFG_REFINT         430     /* Refresh interval                 */
 
        /* Burst To Precharge. Bits of this value go to MCCR3 and MCCR4.
         */
@@ -151,16 +151,16 @@
 
        /* Bit-field values for MCCR3.
         */
-#define CFG_REFREC         2       /* Refresh to activate interval   */
-#define CFG_RDLAT          3       /* Data latancy from read command */
+#define CFG_REFREC         2       /* Refresh to activate interval     */
+#define CFG_RDLAT          3       /* Data latancy from read command   */
 
        /* Bit-field values for MCCR4.
         */
-#define CFG_PRETOACT       2       /* Precharge to activate interval */
-#define CFG_ACTTOPRE       5       /* Activate to Precharge interval */
-#define CFG_SDMODE_CAS_LAT  2      /* SDMODE CAS latancy             */
-#define CFG_SDMODE_WRAP            0       /* SDMODE wrap type               */
-#define CFG_SDMODE_BURSTLEN 2      /* SDMODE Burst length            */
+#define CFG_PRETOACT       2       /* Precharge to activate interval   */
+#define CFG_ACTTOPRE       5       /* Activate to Precharge interval   */
+#define CFG_SDMODE_CAS_LAT  2      /* SDMODE CAS latancy               */
+#define CFG_SDMODE_WRAP            0       /* SDMODE wrap type                 */
+#define CFG_SDMODE_BURSTLEN 2      /* SDMODE Burst length              */
 #define CFG_ACTORW         2
 #define CFG_REGISTERD_TYPE_BUFFER 1
 
@@ -229,11 +229,11 @@
 /*-----------------------------------------------------------------------
  * FLASH organization
  */
-#define CFG_MAX_FLASH_BANKS    2       /* Max number of flash banks         */
-#define CFG_MAX_FLASH_SECT     39      /* Max number of sectors in one bank */
+#define CFG_MAX_FLASH_BANKS    2       /* Max number of flash banks            */
+#define CFG_MAX_FLASH_SECT     39      /* Max number of sectors in one bank    */
 
-#define CFG_FLASH_ERASE_TOUT   120000  /* Timeout for Flash Erase (in ms)   */
-#define CFG_FLASH_WRITE_TOUT   500     /* Timeout for Flash Write (in ms)   */
+#define CFG_FLASH_ERASE_TOUT   120000  /* Timeout for Flash Erase (in ms)      */
+#define CFG_FLASH_WRITE_TOUT   500     /* Timeout for Flash Write (in ms)      */
 
        /* Warining: environment is not EMBEDDED in the ppcboot code.
         * It's stored in flash separately.
@@ -241,28 +241,29 @@
 #define CFG_ENV_IS_IN_FLASH        1
 #if 0
 #define CFG_ENV_ADDR           0xFF008000
-#define CFG_ENV_SIZE           0x8000  /* Size of the Environment Sector    */
+#define CFG_ENV_SIZE           0x8000  /* Size of the Environment Sector       */
 #else
 #define CFG_ENV_ADDR           0xFFFC0000
-#define CFG_ENV_SIZE           0x4000  /* Size of the Environment */
-#define CFG_ENV_OFFSET         0       /* starting right at the beginning */
-#define CFG_ENV_SECT_SIZE      0x40000 /* Size of the Environment Sector    */
+#define CFG_ENV_SIZE           0x4000  /* Size of the Environment              */
+#define CFG_ENV_OFFSET         0       /* starting right at the beginning      */
+#define CFG_ENV_SECT_SIZE      0x40000 /* Size of the Environment Sector       */
 #endif
 
 /*-----------------------------------------------------------------------
  * Cache Configuration
  */
-#define CFG_CACHELINE_SIZE  16
-
-
+#define CFG_CACHELINE_SIZE     32
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#  define CFG_CACHELINE_SHIFT  5       /* log base 2 of the above value        */
+#endif
 
 /*
  * Internal Definitions
  *
  * Boot Flags
  */
-#define BOOTFLAG_COLD          0x01    /* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM          0x02    /* Software reboot                  */
+#define BOOTFLAG_COLD          0x01    /* Normal Power-On: Boot from FLASH     */
+#define BOOTFLAG_WARM          0x02    /* Software reboot                      */
 
 
 #endif /* __CONFIG_H */

diff --git a/include/config_IP860.h b/include/config_IP860.h
index 22418c4fe337f89ab2b547d6f0b299e7926b71d0..1468cb157d6399b56b11f53cfa50fa5ee738d3f2 100644 (file)
--- a/include/config_IP860.h
+++ b/include/config_IP860.h
@@ -363,35 +363,35 @@
  */
 #ifndef __ASSEMBLY__
 typedef        struct ip860_bcsr_s {
-       uchar   shmem_addr;     /* +00 shared memory address register   */
-       uchar   reserved0;
-       uchar   mbox_addr;      /* +02 mailbox address register         */
-       uchar   reserved1;
-       uchar   vme_int_mask;   /* +04 VME Bus interrupt mask register  */
-       uchar   reserved2;
-       uchar   vme_int_pend;   /* +06 VME interrupt pending register   */
-       uchar   reserved3;
-       uchar   bd_int_mask;    /* +08 board interrupt mask register    */
-       uchar   reserved4;
-       uchar   bd_int_pend;    /* +0A board interrupt pending register */
-       uchar   reserved5;
-       uchar   bd_ctrl;        /* +0C board control register           */
-       uchar   reserved6;
-       uchar   bd_status;      /* +0E board status  register           */
-       uchar   reserved7;
-       uchar   vme_irq;        /* +10 VME interrupt request register   */
-       uchar   reserved8;
-       uchar   vme_ivec;       /* +12 VME interrupt vector register    */
-       uchar   reserved9;
-       uchar   cli_mbox;       /* +14 clear mailbox irq                */
-       uchar   reservedA;
-       uchar   rtc;            /* +16 RTC control register             */
-       uchar   reservedB;
-       uchar   mbox_data;      /* +18 mailbox read/write register      */
-       uchar   reservedC;
-       uchar   wd_trigger;     /* +1A Watchdog trigger register        */
-       uchar   reservedD;
-       uchar   rmw_req;        /* +1C RMW request register             */
+       unsigned char   shmem_addr;     /* +00 shared memory address register   */
+       unsigned char   reserved0;
+       unsigned char   mbox_addr;      /* +02 mailbox address register         */
+       unsigned char   reserved1;
+       unsigned char   vme_int_mask;   /* +04 VME Bus interrupt mask register  */
+       unsigned char   reserved2;
+       unsigned char   vme_int_pend;   /* +06 VME interrupt pending register   */
+       unsigned char   reserved3;
+       unsigned char   bd_int_mask;    /* +08 board interrupt mask register    */
+       unsigned char   reserved4;
+       unsigned char   bd_int_pend;    /* +0A board interrupt pending register */
+       unsigned char   reserved5;
+       unsigned char   bd_ctrl;        /* +0C board control register           */
+       unsigned char   reserved6;
+       unsigned char   bd_status;      /* +0E board status  register           */
+       unsigned char   reserved7;
+       unsigned char   vme_irq;        /* +10 VME interrupt request register   */
+       unsigned char   reserved8;
+       unsigned char   vme_ivec;       /* +12 VME interrupt vector register    */
+       unsigned char   reserved9;
+       unsigned char   cli_mbox;       /* +14 clear mailbox irq                */
+       unsigned char   reservedA;
+       unsigned char   rtc;            /* +16 RTC control register             */
+       unsigned char   reservedB;
+       unsigned char   mbox_data;      /* +18 mailbox read/write register      */
+       unsigned char   reservedC;
+       unsigned char   wd_trigger;     /* +1A Watchdog trigger register        */
+       unsigned char   reservedD;
+       unsigned char   rmw_req;        /* +1C RMW request register             */
 } ip860_bcsr_t;
 #endif /* __ASSEMBLY__ */
 

diff --git a/include/config_MPC8260ADS.h b/include/config_MPC8260ADS.h
index e08cdb5b8cabfd09df882e928d8992413ce61b9a..031531b431c9b3dd068a61b22b74d6f1419d633a 100644 (file)
--- a/include/config_MPC8260ADS.h
+++ b/include/config_MPC8260ADS.h
@@ -38,8 +38,8 @@
  * (easy to change)
  */
 
-#define CONFIG_MPC8260         1       /* This is an MPC8260 CPU       */
-#define CONFIG_MPC8260ADS      1       /* ...on motorola ads board     */
+#define CONFIG_MPC8260         1       /* This is an MPC8260 CPU   */
+#define CONFIG_MPC8260ADS      1       /* ...on motorola ads board */
 
 /* allow serial and ethaddr to be overwritten */
 #define CONFIG_ENV_OVERWRITE
@@ -58,7 +58,7 @@
  */
 #undef CONFIG_CONS_ON_SMC              /* define if console on SMC */
 #define CONFIG_CONS_ON_SCC             /* define if console on SCC */
-#undef CONFIG_CONS_NONE                /* define if console on something else*/
+#undef CONFIG_CONS_NONE                /* define if console on something else */
 #define CONFIG_CONS_INDEX      1       /* which serial channel for console */
 
 /*
@@ -72,36 +72,36 @@
  * defined elsewhere (as for the console), or CFG_CMD_NET must be removed
  * from CONFIG_COMMANDS to remove support for networking.
  */
-#undef CONFIG_ETHER_ON_SCC             /* define if ether on SCC       */
-#define CONFIG_ETHER_ON_FCC            /* define if ether on FCC       */
+#undef CONFIG_ETHER_ON_SCC             /* define if ether on SCC   */
+#define CONFIG_ETHER_ON_FCC            /* define if ether on FCC   */
 #undef CONFIG_ETHER_NONE               /* define if ether on something else */
-#define CONFIG_ETHER_INDEX     2       /* which channel for ether      */
+#define CONFIG_ETHER_INDEX     2       /* which channel for ether  */
 
 /* other options */
-#define CONFIG_I2C             1       /* To enable I2C support        */
+#define CONFIG_I2C             1               /* To enable I2C support    */
 
 #define CONFIG_8260_CLKIN      66666666        /* in Hz */
 #define CONFIG_BAUDRATE                115200
 
 #define CONFIG_COMMANDS                (CFG_CMD_ALL & ~( \
-                                       CFG_CMD_BEDBUG  | \
-                                       CFG_CMD_BSP     | \
-                                       CFG_CMD_DATE    | \
-                                       CFG_CMD_EEPROM  | \
-                                       CFG_CMD_FDC     | \
-                                       CFG_CMD_IDE     | \
-                                       CFG_CMD_KGDB    | \
-                                       CFG_CMD_MII     | \
-                                       CFG_CMD_PCI     | \
-                                       CFG_CMD_PCMCIA  | \
-                                       CFG_CMD_SCSI    ) )
+                                CFG_CMD_BEDBUG | \
+                                CFG_CMD_BSP    | \
+                                CFG_CMD_DATE   | \
+                                CFG_CMD_EEPROM | \
+                                CFG_CMD_FDC    | \
+                                CFG_CMD_IDE    | \
+                                CFG_CMD_KGDB   | \
+                                CFG_CMD_MII    | \
+                                CFG_CMD_PCI    | \
+                                CFG_CMD_PCMCIA | \
+                                CFG_CMD_SCSI   ) )
 
 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
 #include <cmd_confdefs.h>
 
 
-#define CONFIG_BOOTDELAY       5       /* autoboot after 5 seconds     */
-#define CONFIG_BOOTCOMMAND     "bootm 100000" /* autoboot command*/
+#define CONFIG_BOOTDELAY       5       /* autoboot after 5 seconds */
+#define CONFIG_BOOTCOMMAND     "bootm 100000"  /* autoboot command */
 #define CONFIG_BOOTARGS                "root=/dev/ram rw"
 
 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
@@ -117,18 +117,18 @@
 /*
  * Miscellaneous configurable options
  */
-#define CFG_LONGHELP                   /* undef to save memory         */
-#define CFG_PROMPT     "=> "           /* Monitor Command Prompt       */
+#define CFG_LONGHELP                   /* undef to save memory     */
+#define CFG_PROMPT     "=> "           /* Monitor Command Prompt   */
 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define CFG_CBSIZE     1024            /* Console I/O Buffer Size      */
+#define CFG_CBSIZE     1024            /* Console I/O Buffer Size  */
 #else
-#define CFG_CBSIZE     256             /* Console I/O Buffer Size      */
+#define CFG_CBSIZE     256                     /* Console I/O Buffer Size  */
 #endif
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define CFG_MAXARGS    16              /* max number of command args   */
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)  /* Print Buffer Size */
+#define CFG_MAXARGS    16                      /* max number of command args   */
 #define CFG_BARGSIZE   CFG_CBSIZE      /* Boot Argument Buffer Size    */
 
-#define CFG_MEMTEST_START      0x00100000      /* memtest works on     */
+#define CFG_MEMTEST_START      0x00100000      /* memtest works on */
 #define CFG_MEMTEST_END                0x00f00000      /* 1 ... 15 MB in DRAM  */
 
 #define CONFIG_CLOCKS_IN_MHZ   1       /* clocks passsed to Linux in MHz */
@@ -142,11 +142,11 @@
 
 #define CFG_FLASH_BASE         0xff800000
 #define FLASH_BASE             0xff800000
-#define CFG_MAX_FLASH_BANKS    1   /* max num of memory banks      */
-#define CFG_MAX_FLASH_SECT     32  /* max num of sects on one chip */
+#define CFG_MAX_FLASH_BANKS    1       /* max num of memory banks      */
+#define CFG_MAX_FLASH_SECT     32      /* max num of sects on one chip */
 #define CFG_FLASH_SIZE         8
-#define CFG_FLASH_ERASE_TOUT   8000 /* Timeout for Flash Erase (in ms)    */
-#define CFG_FLASH_WRITE_TOUT   5    /* Timeout for Flash Write (in ms)    */
+#define CFG_FLASH_ERASE_TOUT   8000    /* Timeout for Flash Erase (in ms)    */
+#define CFG_FLASH_WRITE_TOUT   5       /* Timeout for Flash Write (in ms)    */
 
 /* this is stuff came out of the Motorola docs */
 #define CFG_DEFAULT_IMMR       0x0F010000
@@ -163,7 +163,7 @@
 
 #define CFG_INIT_RAM_ADDR      CFG_IMMR
 #define CFG_INIT_RAM_END       0x4000  /* End of used area in DPRAM    */
-#define CFG_INIT_DATA_SIZE     128  /* size in bytes reserved for initial data */
+#define CFG_INIT_DATA_SIZE     128     /* size in bytes reserved for initial data */
 #define CFG_INIT_DATA_OFFSET   (CFG_INIT_RAM_END - CFG_INIT_DATA_SIZE)
 #define CFG_INIT_SP_OFFSET     CFG_INIT_DATA_OFFSET
 
@@ -185,54 +185,54 @@
 #define CFG_HRCW_SLAVE7 0
 
 #define BOOTFLAG_COLD  0x01    /* Normal Power-On: Boot from FLASH  */
-#define BOOTFLAG_WARM  0x02    /* Software reboot                   */
+#define BOOTFLAG_WARM  0x02    /* Software reboot           */
 
 #define CFG_MONITOR_BASE    TEXT_BASE
 #if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
 #   define CFG_RAMBOOT
 #endif
 
-#define CFG_MONITOR_LEN            (256 << 10)     /* Reserve 256 kB for Monitor   */
-#define CFG_MALLOC_LEN     (128 << 10)     /* Reserve 128 kB for malloc()  */
-#define CFG_BOOTMAPSZ      (8 << 20)       /* Initial Memory map for Linux */
+#define CFG_MONITOR_LEN                (256 << 10)     /* Reserve 256 kB for Monitor   */
+#define CFG_MALLOC_LEN         (128 << 10)     /* Reserve 128 kB for malloc()  */
+#define CFG_BOOTMAPSZ          (8 << 20)       /* Initial Memory map for Linux */
 
 #ifndef CFG_RAMBOOT
-#  define CFG_ENV_IS_IN_FLASH  1
-#    define CFG_ENV_ADDR       (CFG_MONITOR_BASE + 0x40000)
-#    define CFG_ENV_SECT_SIZE  0x40000
+#  define CFG_ENV_IS_IN_FLASH  1
+#    define CFG_ENV_ADDR       (CFG_MONITOR_BASE + 0x40000)
+#    define CFG_ENV_SECT_SIZE  0x40000
 #else
-#  define CFG_ENV_IS_IN_NVRAM  1
-#  define CFG_ENV_ADDR        (CFG_MONITOR_BASE - 0x1000)
-#  define CFG_ENV_SIZE        0x200
-#endif /* CFG_RAMBOOT */
+#  define CFG_ENV_IS_IN_NVRAM  1
+#  define CFG_ENV_ADDR         (CFG_MONITOR_BASE - 0x1000)
+#  define CFG_ENV_SIZE         0x200
+#endif                                                 /* CFG_RAMBOOT */
 
 
-#define CFG_CACHELINE_SIZE  32     /* For MPC8260 CPU */
+#define CFG_CACHELINE_SIZE     32      /* For MPC8260 CPU */
 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#  define CFG_CACHELINE_SHIFT    5     /* log base 2 of the above value */
+#  define CFG_CACHELINE_SHIFT  5       /* log base 2 of the above value */
 #endif
 
 
-#define CFG_HID0_INIT  0
-#define CFG_HID0_FINAL (HID0_ICE | HID0_IFEM | HID0_ABE )
+#define CFG_HID0_INIT          0
+#define CFG_HID0_FINAL         (HID0_ICE | HID0_IFEM | HID0_ABE )
 
-#define CFG_HID2           0
+#define CFG_HID2               0
 
-#define CFG_SYPCR          0xFFFFFFC3
-#define CFG_BCR                    0x100C0000
-#define CFG_SIUMCR         0x0A200000
-#define CFG_SCCR           0x00000000
-#define CFG_BR0_PRELIM     0xFF801801
-#define CFG_OR0_PRELIM     0xFF800836
-#define CFG_BR1_PRELIM     0x04501801
-#define CFG_OR1_PRELIM     0xFFFF8010
+#define CFG_SYPCR              0xFFFFFFC3
+#define CFG_BCR                        0x100C0000
+#define CFG_SIUMCR             0x0A200000
+#define CFG_SCCR               0x00000000
+#define CFG_BR0_PRELIM         0xFF801801
+#define CFG_OR0_PRELIM         0xFF800836
+#define CFG_BR1_PRELIM         0x04501801
+#define CFG_OR1_PRELIM         0xFFFF8010
 
-#define CFG_RMR                    0
-#define CFG_TMCNTSC    (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
-#define CFG_PISCR      (PISCR_PS|PISCR_PTF|PISCR_PTE)
-#define CFG_RCCR       0
-#define CFG_PSDMR      0x016EB452
-#define CFG_MPTPR      0x00001900
-#define CFG_PSRT       0x00000021
+#define CFG_RMR                        0
+#define CFG_TMCNTSC            (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
+#define CFG_PISCR              (PISCR_PS|PISCR_PTF|PISCR_PTE)
+#define CFG_RCCR               0
+#define CFG_PSDMR              0x016EB452
+#define CFG_MPTPR              0x00001900
+#define CFG_PSRT               0x00000021
 
-#endif /* __CONFIG_H */
+#endif /* __CONFIG_H */

diff --git a/include/config_NX823.h b/include/config_NX823.h
index 0206657fa250bb88903f085d90b55653c132c365..c1558392c1766b58a4abe216eb8c8f3c553d4c33 100644 (file)
--- a/include/config_NX823.h
+++ b/include/config_NX823.h
@@ -15,7 +15,7 @@
  *
  * This program is distributed in the hope that it will be useful,
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.         See the
  * GNU General Public License for more details.
  *
  * You should have received a copy of the GNU General Public License
@@ -36,31 +36,31 @@
  * (easy to change)
  */
 
-#define CONFIG_MPC823          1       /* This is a MPC823 CPU         */
-#define CONFIG_NX823           1       /* ...on a NEXUS 823  module    */
+#define CONFIG_MPC823          1       /* This is a MPC823 CPU     */
+#define CONFIG_NX823           1       /* ...on a NEXUS 823  module    */
 
 /*#define  CONFIG_VIDEO                1 */
 
-#define CONFIG_8xx_GCLK_FREQ   MPC8XX_SPEED            
-#define        CONFIG_8xx_CONS_SMC1    1       /* Console is on SMC1           */
+#define CONFIG_8xx_GCLK_FREQ   MPC8XX_SPEED
+#define CONFIG_8xx_CONS_SMC1   1       /* Console is on SMC1       */
 #undef CONFIG_8xx_CONS_SMC2
 #undef CONFIG_8xx_CONS_NONE
-#define CONFIG_BAUDRATE        57600   /* console baudrate = 115kbps   */
-#define CONFIG_BOOTDELAY       2       /* autoboot after 2 seconds     */
-#define        CONFIG_BOOTARGS         "ramdisk=8000 "\
+#define CONFIG_BAUDRATE 57600  /* console baudrate = 115kbps   */
+#define CONFIG_BOOTDELAY       2       /* autoboot after 2 seconds */
+#define CONFIG_BOOTARGS                "ramdisk=8000 "\
                                "root=/dev/nfs rw nfsroot=10.77.77.250:/ppcroot "\
                                "nfsaddrs=10.77.77.20:10.77.77.250"
 #define CONFIG_BOOTCOMMAND     "bootm 400e0000"
 
-#define CONFIG_LOADS_ECHO              1       /* echo on for serial download  */
-#undef CFG_LOADS_BAUD_CHANGE   /* don't allow baudrate change  */
-#undef CONFIG_WATCHDOG                 /* watchdog disabled, for now           */
+#define CONFIG_LOADS_ECHO      1       /* echo on for serial download  */
+#undef CFG_LOADS_BAUD_CHANGE           /* don't allow baudrate change  */
+#undef CONFIG_WATCHDOG                 /* watchdog disabled, for now       */
 #define CONFIG_BOOTP_MASK      (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
-#define CONFIG_COMMANDS  (CONFIG_CMD_DFL | CFG_CMD_AUTOSCRIPT)
+#define CONFIG_COMMANDS                (CONFIG_CMD_DFL | CFG_CMD_AUTOSCRIPT)
 #define CONFIG_AUTOSCRIPT
 
 /* call various generic functions */
-#define CONFIG_MISC_INIT_R                     
+#define CONFIG_MISC_INIT_R
 
 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
 #include <cmd_confdefs.h>
@@ -68,23 +68,23 @@
 /*
  * Miscellaneous configurable options
  */
-#define        CFG_LONGHELP                    /* undef to save memory         */
-#define        CFG_PROMPT      "=> "           /* Monitor Command Prompt       */
+#define CFG_LONGHELP                   /* undef to save memory     */
+#define CFG_PROMPT             "=> "   /* Monitor Command Prompt   */
 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define        CFG_CBSIZE      1024            /* Console I/O Buffer Size      */
+#define CFG_CBSIZE             1024    /* Console I/O Buffer Size  */
 #else
-#define        CFG_CBSIZE      256             /* Console I/O Buffer Size      */
+#define CFG_CBSIZE             256     /* Console I/O Buffer Size  */
 #endif
-#define        CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define        CFG_MAXARGS     16              /* max number of command args   */
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)  /* Print Buffer Size */
+#define CFG_MAXARGS            16      /* max number of command args   */
 #define CFG_BARGSIZE   CFG_CBSIZE      /* Boot Argument Buffer Size    */
 
-#define CFG_MEMTEST_START      0x0400000       /* memtest works on     */
-#define CFG_MEMTEST_END        0x0C00000       /* 4 ... 12 MB in DRAM  */
+#define CFG_MEMTEST_START      0x0400000       /* memtest works on */
+#define CFG_MEMTEST_END                0x0C00000       /* 4 ... 12 MB in DRAM  */
 
-#define        CFG_LOAD_ADDR           0x100000        /* default load address */
+#define CFG_LOAD_ADDR          0x100000        /* default load address */
 
-#define        CFG_HZ                  1000            /* decrementer freq: 1 ms ticks */
+#define CFG_HZ                 1000    /* decrementer freq: 1 ms ticks */
 
 #define CFG_BAUDRATE_TABLE     { 9600, 19200, 38400, 57600, 115200 }
 
@@ -101,59 +101,59 @@
 /*-----------------------------------------------------------------------
  * Definitions for initial stack pointer and data area (in DPRAM)
  */
-#define CFG_INIT_RAM_ADDR              CFG_IMMR
-#define        CFG_INIT_RAM_END                0x2F00  /* End of used area in DPRAM    */
-#define        CFG_INIT_DATA_SIZE      64  /* size in bytes reserved for initial data */
+#define CFG_INIT_RAM_ADDR      CFG_IMMR
+#define CFG_INIT_RAM_END       0x2F00  /* End of used area in DPRAM    */
+#define CFG_INIT_DATA_SIZE     64      /* size in bytes reserved for initial data */
 #define CFG_INIT_DATA_OFFSET   (CFG_INIT_RAM_END - CFG_INIT_DATA_SIZE)
-#define        CFG_INIT_SP_OFFSET      CFG_INIT_DATA_OFFSET
+#define CFG_INIT_SP_OFFSET     CFG_INIT_DATA_OFFSET
 
 /*-----------------------------------------------------------------------
  * Start addresses for the final memory configuration
  * (Set up by the startup code)
  * Please note that CFG_SDRAM_BASE _must_ start at 0
  */
-#define        CFG_SDRAM_BASE          0x00000000
+#define CFG_SDRAM_BASE         0x00000000
 #define CFG_FLASH_BASE         0x40000000
-#define        CFG_MONITOR_LEN (128 << 10)     /* Reserve 128 kB for Monitor   */
+#define CFG_MONITOR_LEN        (128 << 10)     /* Reserve 128 kB for Monitor   */
 #define CFG_MONITOR_BASE       CFG_FLASH_BASE
-#define        CFG_MALLOC_LEN          (128 << 10)     /* Reserve 128 kB for malloc()  */
+#define CFG_MALLOC_LEN         (128 << 10)     /* Reserve 128 kB for malloc()  */
 
 /*
  * For booting Linux, the board info and command line data
  * have to be in the first 8 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
-#define        CFG_BOOTMAPSZ           (8 << 20)       /* Initial Memory map for Linux */
+#define CFG_BOOTMAPSZ          (8 << 20)       /* Initial Memory map for Linux */
 
 /*-----------------------------------------------------------------------
  * FLASH organization
  */
-#define CFG_MAX_FLASH_BANKS    1               /* max number of memory banks           */
-#define CFG_MAX_FLASH_SECT             128     /* max number of sectors on one chip    */
+#define CFG_MAX_FLASH_BANKS    1       /* max number of memory banks       */
+#define CFG_MAX_FLASH_SECT     128     /* max number of sectors on one chip    */
 
-#define CFG_FLASH_ERASE_TOUT   120000  /* Timeout for Flash Erase (in ms)      */
-#define CFG_FLASH_WRITE_TOUT   500             /* Timeout for Flash Write (in ms)      */
+#define CFG_FLASH_ERASE_TOUT   120000  /* Timeout for Flash Erase (in ms)  */
+#define CFG_FLASH_WRITE_TOUT   500     /* Timeout for Flash Write (in ms)  */
 
 #define CFG_ENV_IS_IN_FLASH    1
 #define xEMBED
-#ifdef  EMBED
-#define CFG_ENV_SIZE                           0x200                   /* FIXME How big when embedded?? */
-#define CFG_ENV_ADDR                           CFG_MONITOR_BASE        
+#ifdef EMBED
+#define CFG_ENV_SIZE           0x200   /* FIXME How big when embedded?? */
+#define CFG_ENV_ADDR           CFG_MONITOR_BASE
 #else
-#define CFG_ENV_ADDR                           0x40020000      /* absolute address for now   */
-#define CFG_ENV_SIZE                           0x20000         /* 8K ouch, this may later be */
+#define CFG_ENV_ADDR           0x40020000      /* absolute address for now   */
+#define CFG_ENV_SIZE           0x20000 /* 8K ouch, this may later be */
 #endif
 
-#define CFG_FLASH_SN_BASE              0x4001fff0      /* programmer automagically puts        */
-#define CFG_FLASH_SN_SECTOR    0x40000000      /* a serial number here                         */      
-#define CFG_FLASH_SN_BYTES             8                                
+#define CFG_FLASH_SN_BASE      0x4001fff0      /* programmer automagically puts    */
+#define CFG_FLASH_SN_SECTOR    0x40000000      /* a serial number here             */
+#define CFG_FLASH_SN_BYTES     8
 
 /*-----------------------------------------------------------------------
  * Cache Configuration
  */
-#define CFG_CACHELINE_SIZE             16      /* For all MPC8xx CPUs                  */
+#define CFG_CACHELINE_SIZE     16      /* For all MPC8xx CPUs          */
 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define CFG_CACHELINE_SHIFT    4       /* log base 2 of the above value        */
+#define CFG_CACHELINE_SHIFT    4       /* log base 2 of the above value    */
 #endif
 
 /*-----------------------------------------------------------------------
@@ -203,9 +203,9 @@
  * interrupt status bit
  */
 #define MPC8XX_SPEED   66666666L
-#define MPC8XX_XIN     32768       /* 32.768 kHz crystal */
+#define MPC8XX_XIN     32768   /* 32.768 kHz crystal */
 #define MPC8XX_FACT            (MPC8XX_SPEED/MPC8XX_XIN)
-#define CFG_PLPRCR_MF  ((MPC8XX_FACT-1) << PLPRCR_MF_SHIFT)  
+#define CFG_PLPRCR_MF  ((MPC8XX_FACT-1) << PLPRCR_MF_SHIFT)
 #define CFG_PLPRCR             (CFG_PLPRCR_MF | PLPRCR_TEXPS | PLPRCR_TMIST)
 
 /*-----------------------------------------------------------------------
@@ -221,7 +221,7 @@
                         SCCR_DFALCD00)
 
 /*-----------------------------------------------------------------------
- * 
+ *
  *-----------------------------------------------------------------------
  *
  */
@@ -233,7 +233,7 @@
  * BR0 and OR0 (FLASH)
  */
 
-#define FLASH_BASE0_PRELIM     0x40000000      /* FLASH bank #0        */
+#define FLASH_BASE0_PRELIM     0x40000000      /* FLASH bank #0    */
 
 /* used to re-map FLASH both when starting from SRAM or FLASH:
  * restrict access enough to keep SRAM working (if any)
@@ -253,8 +253,8 @@
 /*
  * BR1/2 and OR1/2 (SDRAM)
  */
-#define SDRAM_BASE1_PRELIM     0x00000000      /* SDRAM bank #0        */
-#define SDRAM_BASE2_PRELIM     0x20000000      /* SDRAM bank #1        */
+#define SDRAM_BASE1_PRELIM     0x00000000      /* SDRAM bank #0    */
+#define SDRAM_BASE2_PRELIM     0x20000000      /* SDRAM bank #1    */
 #define SDRAM_MAX_SIZE         0x04000000      /* max 64 MB per bank   */
 
 /* SDRAM timing: Multiplexed addresses, drive GPL5 high on first cycle */
@@ -267,7 +267,7 @@
 
 /* IO and memory mapped stuff */
 #define NX823_IO_OR_AM         0xFFFF0000      /* mask for IO addresses */
-#define NX823_IO_BASE          0xFF000000      /* start of IO  */
+#define NX823_IO_BASE          0xFF000000      /* start of IO  */
 #define GPOUT_OFFSET           (3<<16)
 #define QUART_OFFSET           (4<<16)
 #define VIDAC_OFFSET           (5<<16)
@@ -277,24 +277,24 @@
 /*
  * BR3 and OR3 (general purpose output latches)
  */
-#define GPOUT_BASE     (NX823_IO_BASE + GPOUT_OFFSET)  
-#define GPOUT_TIMING   (OR_CSNT_SAM | OR_TRLX | OR_BI)         
+#define GPOUT_BASE     (NX823_IO_BASE + GPOUT_OFFSET)
+#define GPOUT_TIMING   (OR_CSNT_SAM | OR_TRLX | OR_BI)
 #define CFG_OR3_PRELIM (NX823_IO_OR_AM | GPOUT_TIMING)
 #define CFG_BR3_PRELIM (GPOUT_BASE | BR_V)
 
 /*
  * BR4 and OR4 (QUART)
  */
-#define QUART_BASE     (NX823_IO_BASE + QUART_OFFSET)  
-#define QUART_TIMING   (OR_ACS_DIV4 | OR_SCY_3_CLK | OR_CSNT_SAM | OR_TRLX)    
+#define QUART_BASE     (NX823_IO_BASE + QUART_OFFSET)
+#define QUART_TIMING   (OR_ACS_DIV4 | OR_SCY_3_CLK | OR_CSNT_SAM | OR_TRLX)
 #define CFG_OR4_PRELIM (NX823_IO_OR_AM | QUART_TIMING | OR_BI)
 #define CFG_BR4_PRELIM (QUART_BASE | BR_PS_8 | BR_V)
 
 /*
  * BR5 and OR5 (Video DAC)
  */
-#define VIDAC_BASE     (NX823_IO_BASE + VIDAC_OFFSET)  
-#define VIDAC_TIMING   (OR_ACS_DIV4 | OR_SCY_3_CLK | OR_CSNT_SAM | OR_EHTR)    
+#define VIDAC_BASE     (NX823_IO_BASE + VIDAC_OFFSET)
+#define VIDAC_TIMING   (OR_ACS_DIV4 | OR_SCY_3_CLK | OR_CSNT_SAM | OR_EHTR)
 #define CFG_OR5_PRELIM (NX823_IO_OR_AM | VIDAC_TIMING | OR_BI)
 #define CFG_BR5_PRELIM (VIDAC_BASE | BR_PS_8 | BR_V)
 
@@ -302,8 +302,8 @@
  * BR6 and OR6 (CPLD)
  * FIXME timing not verified for CPLD
  */
-#define CPLD_BASE      (NX823_IO_BASE + CPLD_OFFSET)   
-#define CPLD_TIMING    (OR_ACS_DIV4 | OR_SCY_3_CLK | OR_CSNT_SAM | OR_EHTR)    
+#define CPLD_BASE      (NX823_IO_BASE + CPLD_OFFSET)
+#define CPLD_TIMING    (OR_ACS_DIV4 | OR_SCY_3_CLK | OR_CSNT_SAM | OR_EHTR)
 #define CFG_OR6_PRELIM (NX823_IO_OR_AM | CPLD_TIMING | OR_BI)
 #define CFG_BR6_PRELIM (CPLD_BASE | BR_PS_8 | BR_V )
 
@@ -311,7 +311,7 @@
  * BR7 and OR7 (SED1386)
  * FIXME timing not verified for SED controller
  */
-#define SED1386_BASE   0xF7000000      
+#define SED1386_BASE   0xF7000000
 #define CFG_OR7_PRELIM (0xFF000000 | OR_BI | OR_SETA)
 #define CFG_BR7_PRELIM (SED1386_BASE | BR_PS_16 | BR_V )
 
@@ -320,15 +320,15 @@
  */
 
 /* periodic timer for refresh */
-#define CFG_MAMR_PTA   97              /* start with divider for 100 MHz       */
+#define CFG_MAMR_PTA   97              /* start with divider for 100 MHz   */
 
 /* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit    */
-#define CFG_MPTPR_2BK_4K       MPTPR_PTP_DIV16         /* setting for 2 banks  */
-#define CFG_MPTPR_1BK_4K       MPTPR_PTP_DIV32         /* setting for 1 bank   */
+#define CFG_MPTPR_2BK_4K       MPTPR_PTP_DIV16 /* setting for 2 banks  */
+#define CFG_MPTPR_1BK_4K       MPTPR_PTP_DIV32 /* setting for 1 bank   */
 
 /* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit                */
-#define CFG_MPTPR_2BK_8K       MPTPR_PTP_DIV8                  /* setting for 2 banks  */
-#define CFG_MPTPR_1BK_8K       MPTPR_PTP_DIV16         /* setting for 1 bank   */
+#define CFG_MPTPR_2BK_8K       MPTPR_PTP_DIV8  /* setting for 2 banks  */
+#define CFG_MPTPR_1BK_8K       MPTPR_PTP_DIV16 /* setting for 1 bank   */
 
 /*
  * MAMR settings for SDRAM
@@ -349,13 +349,12 @@
  *
  * Boot Flags
  */
-#define BOOTFLAG_COLD  0x01            /* Normal Power-On: Boot from FLASH     */
-#define BOOTFLAG_WARM  0x02            /* Software reboot                      */
+#define BOOTFLAG_COLD  0x01    /* Normal Power-On: Boot from FLASH */
+#define BOOTFLAG_WARM  0x02    /* Software reboot          */
 
-#define CONFIG_ENV_OVERWRITE           /* allow changes to ethaddr (for now)   */
+#define CONFIG_ENV_OVERWRITE   /* allow changes to ethaddr (for now)   */
 #define CONFIG_ETHADDR         00:10:20:30:40:50
 #define CONFIG_IPADDR          10.77.77.20
 #define CONFIG_SERVERIP                10.77.77.250
 
-#endif /* __CONFIG_H */
-
+#endif                                                 /* __CONFIG_H */

diff --git a/include/config_PM826.h b/include/config_PM826.h
index 51cca4ec4bb014731f7a682a219f9857e56042e2..68ec62e342c9c7ffab73fd9f2952b558cd153832 100644 (file)
--- a/include/config_PM826.h
+++ b/include/config_PM826.h
@@ -243,6 +243,9 @@
  * Cache Configuration
  */
 #define CFG_CACHELINE_SIZE      32      /* For MPC8260 CPU              */
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#  define CFG_CACHELINE_SHIFT  5       /* log base 2 of the above value */
+#endif
 
 /*-----------------------------------------------------------------------
  * HIDx - Hardware Implementation-dependent Registers                    2-11

diff --git a/include/config_Sandpoint8240.h b/include/config_Sandpoint8240.h
index f9b22d7f1de94f8242b306073e873836ae1eadb4..44a79c03dc2ef483c3515a0084481869e148d563 100644 (file)
--- a/include/config_Sandpoint8240.h
+++ b/include/config_Sandpoint8240.h
@@ -1,5 +1,25 @@
-
-
+/*
+ * (C) Copyright 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
 
 /* ------------------------------------------------------------------------- */
 
@@ -10,7 +30,6 @@
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
-
 /*
  * High Level Configuration Options
  * (easy to change)
@@ -123,7 +142,7 @@
 #define CFG_REGISTERD_TYPE_BUFFER   1
 
 /* memory bank settings*/
-/* only bits 20-29 are actually used from these vales to set the stare/end address
+/* only bits 20-29 are actually used from these vales to set the start/end address
    the upper two bits will be 0, and the lower 20 bits will be set to
    0x00000 for a start address, or 0xfffff for an end address*/
 
@@ -156,6 +175,31 @@
                                        /* currently accessed page in memory    */
                                        /* see 8240 book for details            */
 
+/* SDRAM 0 - 256MB */
+#define CFG_IBAT0L     (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CFG_IBAT0U     (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+
+/* stack in DCACHE @ 1GB (no backing mem) */
+#define CFG_IBAT1L     (0x40000000 | BATL_PP_00 )
+#define CFG_IBAT1U     (0x40000000 | BATU_BL_128K )
+
+/* PCI memory */
+#define CFG_IBAT2L     (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
+#define CFG_IBAT2U     (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP)
+
+/* Flash, config addrs, etc */
+#define CFG_IBAT3L     (0xF0000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
+#define CFG_IBAT3U     (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
+
+#define CFG_DBAT0L     CFG_IBAT0L
+#define CFG_DBAT0U     CFG_IBAT0U
+#define CFG_DBAT1L     CFG_IBAT1L
+#define CFG_DBAT1U     CFG_IBAT1U
+#define CFG_DBAT2L     CFG_IBAT2L
+#define CFG_DBAT2U     CFG_IBAT2U
+#define CFG_DBAT3L     CFG_IBAT3L
+#define CFG_DBAT3U     CFG_IBAT3U
+
 /*
  * For booting Linux, the board info and command line data
  * have to be in the first 8 MB of memory, since this is
@@ -174,8 +218,10 @@
 /*-----------------------------------------------------------------------
  * Cache Configuration
  */
-#define CFG_CACHELINE_SIZE     16      /* For all MPC8xx CPUs                  */
-
+#define CFG_CACHELINE_SIZE     32      /* For MPC8240 CPU                      */
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#  define CFG_CACHELINE_SHIFT  5       /* log base 2 of the above value */
+#endif
 
 
 /*

diff --git a/include/config_TQM823L.h b/include/config_TQM823L.h
index 1967abcaeb506b6982e30c81b5a3055c3ddb15f6..18b295c09a432858562960913ab1d255533b4d42 100644 (file)
--- a/include/config_TQM823L.h
+++ b/include/config_TQM823L.h
@@ -38,6 +38,9 @@
 #define CONFIG_MPC823          1       /* This is a MPC823 CPU         */
 #define CONFIG_TQM823L         1       /* ...on a TQM8xxL module       */
 
+#define CONFIG_LCD             1       /* use LCD controller ...       */
+#define CONFIG_NEC_NL6648BC20  1       /* and NEC NL6648BC20 display   */
+
 #define        CONFIG_8xx_CONS_SMC1    1       /* Console is on SMC1           */
 #undef CONFIG_8xx_CONS_SMC2
 #undef CONFIG_8xx_CONS_NONE
@@ -64,7 +67,11 @@
 
 #undef CONFIG_WATCHDOG                 /* watchdog disabled            */
 
-#define        CONFIG_STATUS_LED       1       /* Status LED enabled           */
+#ifdef CONFIG_LCD
+# undef         CONFIG_STATUS_LED              /* disturbs display             */
+#else
+# define CONFIG_STATUS_LED     1       /* Status LED enabled           */
+#endif /* CONFIG_LCD */
 
 #undef CONFIG_CAN_DRIVER               /* CAN Driver support disabled  */
 

diff --git a/include/config_TQM8260.h b/include/config_TQM8260.h
index cd71ecee39f1d43c7c391ef4ae0e7a7e0f86c54f..2d0e559ee9789628f43772f83b5b8b5ab9a5352d 100644 (file)
--- a/include/config_TQM8260.h
+++ b/include/config_TQM8260.h
@@ -262,6 +262,9 @@
  * Cache Configuration
  */
 #define CFG_CACHELINE_SIZE      32      /* For MPC8260 CPU              */
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+# define CFG_CACHELINE_SHIFT   5       /* log base 2 of the above value */
+#endif
 
 /*-----------------------------------------------------------------------
  * HIDx - Hardware Implementation-dependent Registers                    2-11

diff --git a/include/config_cogent_mpc8260.h b/include/config_cogent_mpc8260.h
index 63c96e2368a4f83e691cb132b2927e2110dcf7e5..b0d3fde5d87b0b20ba3dbbbcaa1c8dd9281982ff 100644 (file)
--- a/include/config_cogent_mpc8260.h
+++ b/include/config_cogent_mpc8260.h
@@ -253,7 +253,7 @@
  */
 #define CFG_CACHELINE_SIZE     32      /* For MPC8260 CPU              */
 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define CFG_CACHELINE_SHIFT    5       /* log base 2 of the above value*/
+# define CFG_CACHELINE_SHIFT   5       /* log base 2 of the above value*/
 #endif
 
 /*-----------------------------------------------------------------------

diff --git a/include/config_sbc8260.h b/include/config_sbc8260.h
index f328b38de49323ada24fa669f2379d7ce77837fe..ccebdfba7d515034796c6a0ac3ca07bc3a611329 100644 (file)
--- a/include/config_sbc8260.h
+++ b/include/config_sbc8260.h
@@ -423,28 +423,28 @@
 /*-----------------------------------------------------------------------
  * FLASH and environment organization
  */
-#define CFG_MAX_FLASH_BANKS   1              /* max number of memory banks         */
-#define CFG_MAX_FLASH_SECT    16      /* max number of sectors on one chip  */
+#define CFG_MAX_FLASH_BANKS    1       /* max number of memory banks           */
+#define CFG_MAX_FLASH_SECT     16      /* max number of sectors on one chip    */
 
-#define CFG_FLASH_ERASE_TOUT  8000    /* Timeout for Flash Erase (in ms)    */
-#define CFG_FLASH_WRITE_TOUT  1              /* Timeout for Flash Write (in ms)    */
+#define CFG_FLASH_ERASE_TOUT   8000    /* Timeout for Flash Erase (in ms)      */
+#define CFG_FLASH_WRITE_TOUT   1       /* Timeout for Flash Write (in ms)      */
 
 #ifndef CFG_RAMBOOT
-#  define CFG_ENV_IS_IN_FLASH  1
+#  define CFG_ENV_IS_IN_FLASH  1
 
 #  ifdef CFG_ENV_IN_OWN_SECT
-#    define CFG_ENV_ADDR       (CFG_MONITOR_BASE + 0x40000)
-#    define CFG_ENV_SECT_SIZE  0x40000
+#    define CFG_ENV_ADDR        (CFG_MONITOR_BASE + 0x40000)
+#    define CFG_ENV_SECT_SIZE   0x40000
 #  else
 #    define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_MONITOR_LEN - CFG_ENV_SECT_SIZE)
-#    define CFG_ENV_SIZE       0x1000  /* Total Size of Environment Sector */
-#    define CFG_ENV_SECT_SIZE  0x10000 /* see README - env sect real size */
+#    define CFG_ENV_SIZE        0x1000 /* Total Size of Environment Sector     */
+#    define CFG_ENV_SECT_SIZE   0x10000 /* see README - env sect real size     */
 #  endif /* CFG_ENV_IN_OWN_SECT */
 
 #else
-#  define CFG_ENV_IS_IN_NVRAM  1
-#  define CFG_ENV_ADDR        (CFG_MONITOR_BASE - 0x1000)
-#  define CFG_ENV_SIZE        0x200
+#  define CFG_ENV_IS_IN_NVRAM   1
+#  define CFG_ENV_ADDR         (CFG_MONITOR_BASE - 0x1000)
+#  define CFG_ENV_SIZE         0x200
 #endif /* CFG_RAMBOOT */
 
 /*-----------------------------------------------------------------------
@@ -453,7 +453,7 @@
 #define CFG_CACHELINE_SIZE     32      /* For MPC8260 CPU */
 
 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#  define CFG_CACHELINE_SHIFT    5     /* log base 2 of the above value */
+# define CFG_CACHELINE_SHIFT   5       /* log base 2 of the above value */
 #endif
 
 /*-----------------------------------------------------------------------

diff --git a/include/ppcboot.h b/include/ppcboot.h
index 5ac6835f5aecd724920ca91f7a951ab6fdcc5c83..936ae452bdee90a85b5a0390ac548c293246a3f4 100644 (file)
--- a/include/ppcboot.h
+++ b/include/ppcboot.h
@@ -386,16 +386,17 @@ void      watchdog_reset(void);
 #if defined(CONFIG_8260)
 void   get_8260_clks (void);
 void   prt_8260_clks (void);
-#elif defined(CONFIG_8xx)      || \
-      defined(CONFIG_IOP480)   || \
-      defined(CONFIG_4xx)      || \
+#elif defined(CONFIG_4xx)      || \
+      defined(CONFIG_8xx)      || \
       defined(CONFIG_CU824)    || \
       defined(CONFIG_EVB64260) || \
-      defined(CONFIG_MOUSSE)
+      defined(CONFIG_IOP480)   || \
+      defined(CONFIG_MOUSSE)   || \
+      defined(CONFIG_SANDPOINT)
 ulong  get_gclk_freq (void);
-ulong get_OPB_freq (void);
+ulong  get_OPB_freq (void);
 #ifdef CONFIG_4xx
-ulong get_PCI_freq (void);
+ulong  get_PCI_freq (void);
 #endif
 #endif