drm/amd/display: Add monitor patch to read psr cap again

[Why & How]
According to the vendor’s requirement, after each OUI write,
the PSR cap must be read; otherwise, the vendor will default
to using PSRSU. But its PSR cap indicates that it only supports
PSR1.

Reviewed-by: Wenjing Liu <wenjing.liu@amd.com>
Signed-off-by: Paul Hsieh <Paul.Hsieh@amd.com>
Signed-off-by: Ivan Lipski <ivan.lipski@amd.com>
Tested-by: Dan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/dc_types.h b/drivers/gpu/drm/amd/display/dc/dc_types.h
index 619834a328a37b308a6552bc519d979e9b723ac9..b5aa03a3e39cf48fa3b165d9f7996d97dca259e3 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dc_types.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_types.h
@@ -1217,6 +1217,7 @@ struct dc_panel_config {
                bool rc_disable;
                bool rc_allow_static_screen;
                bool rc_allow_fullscreen_VPB;
+               bool read_psrcap_again;
                unsigned int replay_enable_option;
        } psr;
        /* ABM */

diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c b/drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c
index 8b7b87b21c2e97e937612f536b6d64d0551780e4..5e806edbb9f610fd061d2e75a72f779115b8b401 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c
+++ b/drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c
@@ -703,6 +703,20 @@ bool edp_setup_psr(struct dc_link *link,
        if (!link)
                return false;
 
+       /* This is a workaround: some vendors require the source to
+        * read the PSR cap; otherwise, the vendor's PSR feature will
+        * fall back to its default behavior, causing a misconfiguration
+        * of this feature.
+        */
+       if (link->panel_config.psr.read_psrcap_again) {
+               dm_helpers_dp_read_dpcd(
+                       link->ctx,
+                       link,
+                       DP_PSR_SUPPORT,
+                       &link->dpcd_caps.psr_info.psr_version,
+                       sizeof(link->dpcd_caps.psr_info.psr_version));
+       }
+
        //Clear PSR cfg
        memset(&psr_configuration, 0, sizeof(psr_configuration));
        dm_helpers_dp_write_dpcd(