ARM: 9267/1: Define Armv8 registers in AArch32 state

AArch32 Instruction Set Attribute Register 6 (ID_ISAR6_EL1) and AArch32
Processor Feature Register 2 (ID_PFR2_EL1) identifies some new features
for the Armv8 architecture. This registers will be utilized to add
hwcaps for those cpu features.

These registers are marked as reserved for Armv7 and should be a RAZ.

Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Amit Daniel Kachhap <amit.kachhap@arm.com>
Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>

diff --git a/arch/arm/include/asm/cputype.h b/arch/arm/include/asm/cputype.h
index 775cac3c02bb0a31facb970e16feef83f86c6632..0163c3e78a67fe4a075d6a5ecd0c77f969114b96 100644 (file)
--- a/arch/arm/include/asm/cputype.h
+++ b/arch/arm/include/asm/cputype.h
@@ -25,6 +25,8 @@
 #define CPUID_EXT_ISAR3        0x6c
 #define CPUID_EXT_ISAR4        0x70
 #define CPUID_EXT_ISAR5        0x74
+#define CPUID_EXT_ISAR6        0x7c
+#define CPUID_EXT_PFR2 0x90
 #else
 #define CPUID_EXT_PFR0 "c1, 0"
 #define CPUID_EXT_PFR1 "c1, 1"
@@ -40,6 +42,8 @@
 #define CPUID_EXT_ISAR3        "c2, 3"
 #define CPUID_EXT_ISAR4        "c2, 4"
 #define CPUID_EXT_ISAR5        "c2, 5"
+#define CPUID_EXT_ISAR6        "c2, 7"
+#define CPUID_EXT_PFR2 "c3, 4"
 #endif
 
 #define MPIDR_SMP_BITMASK (0x3 << 30)