arm64: dts: qcom: sdm630: correct QFPROM byte offsets

The NVMEM bindings expect that 'bits' property holds offset and size of
region within a byte, so it applies a constraint of <0, 7> for the
offset.  Using 25 as HSTX trim offset is within 4-byte QFPROM word, but
outside of the byte:

  sdm630-sony-xperia-nile-discovery.dtb: qfprom@780000: hstx-trim@240:bits:0:0: 25 is greater than the maximum of 7
  sdm630-sony-xperia-nile-discovery.dtb: qfprom@780000: gpu-speed-bin@41a0:bits:0:0: 21 is greater than the maximum of 7

Align the offsets to match the bindings.

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220505113802.243301-6-krzysztof.kozlowski@linaro.org

diff --git a/arch/arm64/boot/dts/qcom/sdm630.dtsi b/arch/arm64/boot/dts/qcom/sdm630.dtsi
index a42f14ca63ab99e797c63f46253c576cbce1d8f9..38a7741cdea4bd5131332f92ab8f62e3bd3e24c0 100644 (file)
--- a/arch/arm64/boot/dts/qcom/sdm630.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm630.dtsi
@@ -559,13 +559,13 @@
                        #size-cells = <1>;
 
                        qusb2_hstx_trim: hstx-trim@240 {
-                               reg = <0x240 0x1>;
-                               bits = <25 3>;
+                               reg = <0x243 0x1>;
+                               bits = <1 3>;
                        };
 
                        gpu_speed_bin: gpu-speed-bin@41a0 {
-                               reg = <0x41a0 0x1>;
-                               bits = <21 7>;
+                               reg = <0x41a2 0x1>;
+                               bits = <5 7>;
                        };
                };