dev->dev = &pdev->dev;
 
        rdev = pci_get_domain_bus_and_slot(0, 0, PCI_DEVFN(0, 0));
-       if (!rdev || !pci_match_id(pmc_pci_ids, rdev))
+       if (!rdev || !pci_match_id(pmc_pci_ids, rdev)) {
+               pci_dev_put(rdev);
                return -ENODEV;
+       }
 
        dev->cpu_id = rdev->device;
        err = pci_write_config_dword(rdev, AMD_PMC_SMU_INDEX_ADDRESS, AMD_PMC_BASE_ADDR_LO);
        if (err) {
                dev_err(dev->dev, "error writing to 0x%x\n", AMD_PMC_SMU_INDEX_ADDRESS);
+               pci_dev_put(rdev);
                return pcibios_err_to_errno(err);
        }
 
        err = pci_read_config_dword(rdev, AMD_PMC_SMU_INDEX_DATA, &val);
-       if (err)
+       if (err) {
+               pci_dev_put(rdev);
                return pcibios_err_to_errno(err);
+       }
 
        base_addr_lo = val & AMD_PMC_BASE_ADDR_HI_MASK;
 
        err = pci_write_config_dword(rdev, AMD_PMC_SMU_INDEX_ADDRESS, AMD_PMC_BASE_ADDR_HI);
        if (err) {
                dev_err(dev->dev, "error writing to 0x%x\n", AMD_PMC_SMU_INDEX_ADDRESS);
+               pci_dev_put(rdev);
                return pcibios_err_to_errno(err);
        }
 
        err = pci_read_config_dword(rdev, AMD_PMC_SMU_INDEX_DATA, &val);
-       if (err)
+       if (err) {
+               pci_dev_put(rdev);
                return pcibios_err_to_errno(err);
+       }
 
        base_addr_hi = val & AMD_PMC_BASE_ADDR_LO_MASK;
        pci_dev_put(rdev);