]> www.infradead.org Git - users/jedix/linux-maple.git/commitdiff
net: dsa: mv88e6xxx: Separate C22 and C45 transactions
authorAndrew Lunn <andrew@lunn.ch>
Mon, 9 Jan 2023 15:30:51 +0000 (16:30 +0100)
committerJakub Kicinski <kuba@kernel.org>
Tue, 10 Jan 2023 23:53:37 +0000 (15:53 -0800)
The global2 SMI MDIO bus driver can perform both C22 and C45
transfers. Create separate functions for each and register the C45
versions using the new API calls where appropriate. Update the SERDES
code to make use of these new accessors.

Signed-off-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Michael Walle <michael@walle.cc>
Reviewed-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
drivers/net/dsa/mv88e6xxx/chip.c
drivers/net/dsa/mv88e6xxx/chip.h
drivers/net/dsa/mv88e6xxx/global2.c
drivers/net/dsa/mv88e6xxx/global2.h
drivers/net/dsa/mv88e6xxx/phy.c
drivers/net/dsa/mv88e6xxx/phy.h
drivers/net/dsa/mv88e6xxx/serdes.c

index 07f1391c64e7d5ee019969f7f98ea49f6a91fb07..1168ea75f5f5e2df7395469e6c2e117b1dfbeb3b 100644 (file)
@@ -3884,6 +3884,24 @@ static int mv88e6xxx_mdio_read(struct mii_bus *bus, int phy, int reg)
        return err ? err : val;
 }
 
+static int mv88e6xxx_mdio_read_c45(struct mii_bus *bus, int phy, int devad,
+                                  int reg)
+{
+       struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv;
+       struct mv88e6xxx_chip *chip = mdio_bus->chip;
+       u16 val;
+       int err;
+
+       if (!chip->info->ops->phy_read_c45)
+               return -EOPNOTSUPP;
+
+       mv88e6xxx_reg_lock(chip);
+       err = chip->info->ops->phy_read_c45(chip, bus, phy, devad, reg, &val);
+       mv88e6xxx_reg_unlock(chip);
+
+       return err ? err : val;
+}
+
 static int mv88e6xxx_mdio_write(struct mii_bus *bus, int phy, int reg, u16 val)
 {
        struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv;
@@ -3900,6 +3918,23 @@ static int mv88e6xxx_mdio_write(struct mii_bus *bus, int phy, int reg, u16 val)
        return err;
 }
 
+static int mv88e6xxx_mdio_write_c45(struct mii_bus *bus, int phy, int devad,
+                                   int reg, u16 val)
+{
+       struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv;
+       struct mv88e6xxx_chip *chip = mdio_bus->chip;
+       int err;
+
+       if (!chip->info->ops->phy_write_c45)
+               return -EOPNOTSUPP;
+
+       mv88e6xxx_reg_lock(chip);
+       err = chip->info->ops->phy_write_c45(chip, bus, phy, devad, reg, val);
+       mv88e6xxx_reg_unlock(chip);
+
+       return err;
+}
+
 static int mv88e6xxx_mdio_register(struct mv88e6xxx_chip *chip,
                                   struct device_node *np,
                                   bool external)
@@ -3938,6 +3973,8 @@ static int mv88e6xxx_mdio_register(struct mv88e6xxx_chip *chip,
 
        bus->read = mv88e6xxx_mdio_read;
        bus->write = mv88e6xxx_mdio_write;
+       bus->read_c45 = mv88e6xxx_mdio_read_c45;
+       bus->write_c45 = mv88e6xxx_mdio_write_c45;
        bus->parent = chip->dev;
 
        if (!external) {
@@ -4149,8 +4186,10 @@ static const struct mv88e6xxx_ops mv88e6097_ops = {
        .ip_pri_map = mv88e6085_g1_ip_pri_map,
        .irl_init_all = mv88e6352_g2_irl_init_all,
        .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
-       .phy_read = mv88e6xxx_g2_smi_phy_read,
-       .phy_write = mv88e6xxx_g2_smi_phy_write,
+       .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
+       .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
+       .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
+       .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
        .port_set_link = mv88e6xxx_port_set_link,
        .port_sync_link = mv88e6185_port_sync_link,
        .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
@@ -4198,8 +4237,10 @@ static const struct mv88e6xxx_ops mv88e6123_ops = {
        .ip_pri_map = mv88e6085_g1_ip_pri_map,
        .irl_init_all = mv88e6352_g2_irl_init_all,
        .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
-       .phy_read = mv88e6xxx_g2_smi_phy_read,
-       .phy_write = mv88e6xxx_g2_smi_phy_write,
+       .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
+       .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
+       .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
+       .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
        .port_set_link = mv88e6xxx_port_set_link,
        .port_sync_link = mv88e6xxx_port_sync_link,
        .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
@@ -4279,8 +4320,10 @@ static const struct mv88e6xxx_ops mv88e6141_ops = {
        .get_eeprom = mv88e6xxx_g2_get_eeprom8,
        .set_eeprom = mv88e6xxx_g2_set_eeprom8,
        .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
-       .phy_read = mv88e6xxx_g2_smi_phy_read,
-       .phy_write = mv88e6xxx_g2_smi_phy_write,
+       .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
+       .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
+       .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
+       .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
        .port_set_link = mv88e6xxx_port_set_link,
        .port_sync_link = mv88e6xxx_port_sync_link,
        .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
@@ -4343,8 +4386,10 @@ static const struct mv88e6xxx_ops mv88e6161_ops = {
        .ip_pri_map = mv88e6085_g1_ip_pri_map,
        .irl_init_all = mv88e6352_g2_irl_init_all,
        .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
-       .phy_read = mv88e6xxx_g2_smi_phy_read,
-       .phy_write = mv88e6xxx_g2_smi_phy_write,
+       .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
+       .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
+       .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
+       .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
        .port_set_link = mv88e6xxx_port_set_link,
        .port_sync_link = mv88e6xxx_port_sync_link,
        .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
@@ -4426,8 +4471,10 @@ static const struct mv88e6xxx_ops mv88e6171_ops = {
        .ip_pri_map = mv88e6085_g1_ip_pri_map,
        .irl_init_all = mv88e6352_g2_irl_init_all,
        .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
-       .phy_read = mv88e6xxx_g2_smi_phy_read,
-       .phy_write = mv88e6xxx_g2_smi_phy_write,
+       .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
+       .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
+       .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
+       .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
        .port_set_link = mv88e6xxx_port_set_link,
        .port_sync_link = mv88e6xxx_port_sync_link,
        .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
@@ -4472,8 +4519,10 @@ static const struct mv88e6xxx_ops mv88e6172_ops = {
        .get_eeprom = mv88e6xxx_g2_get_eeprom16,
        .set_eeprom = mv88e6xxx_g2_set_eeprom16,
        .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
-       .phy_read = mv88e6xxx_g2_smi_phy_read,
-       .phy_write = mv88e6xxx_g2_smi_phy_write,
+       .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
+       .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
+       .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
+       .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
        .port_set_link = mv88e6xxx_port_set_link,
        .port_sync_link = mv88e6xxx_port_sync_link,
        .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
@@ -4527,8 +4576,10 @@ static const struct mv88e6xxx_ops mv88e6175_ops = {
        .ip_pri_map = mv88e6085_g1_ip_pri_map,
        .irl_init_all = mv88e6352_g2_irl_init_all,
        .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
-       .phy_read = mv88e6xxx_g2_smi_phy_read,
-       .phy_write = mv88e6xxx_g2_smi_phy_write,
+       .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
+       .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
+       .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
+       .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
        .port_set_link = mv88e6xxx_port_set_link,
        .port_sync_link = mv88e6xxx_port_sync_link,
        .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
@@ -4573,8 +4624,10 @@ static const struct mv88e6xxx_ops mv88e6176_ops = {
        .get_eeprom = mv88e6xxx_g2_get_eeprom16,
        .set_eeprom = mv88e6xxx_g2_set_eeprom16,
        .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
-       .phy_read = mv88e6xxx_g2_smi_phy_read,
-       .phy_write = mv88e6xxx_g2_smi_phy_write,
+       .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
+       .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
+       .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
+       .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
        .port_set_link = mv88e6xxx_port_set_link,
        .port_sync_link = mv88e6xxx_port_sync_link,
        .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
@@ -4673,8 +4726,10 @@ static const struct mv88e6xxx_ops mv88e6190_ops = {
        .get_eeprom = mv88e6xxx_g2_get_eeprom8,
        .set_eeprom = mv88e6xxx_g2_set_eeprom8,
        .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
-       .phy_read = mv88e6xxx_g2_smi_phy_read,
-       .phy_write = mv88e6xxx_g2_smi_phy_write,
+       .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
+       .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
+       .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
+       .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
        .port_set_link = mv88e6xxx_port_set_link,
        .port_sync_link = mv88e6xxx_port_sync_link,
        .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
@@ -4736,8 +4791,10 @@ static const struct mv88e6xxx_ops mv88e6190x_ops = {
        .get_eeprom = mv88e6xxx_g2_get_eeprom8,
        .set_eeprom = mv88e6xxx_g2_set_eeprom8,
        .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
-       .phy_read = mv88e6xxx_g2_smi_phy_read,
-       .phy_write = mv88e6xxx_g2_smi_phy_write,
+       .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
+       .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
+       .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
+       .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
        .port_set_link = mv88e6xxx_port_set_link,
        .port_sync_link = mv88e6xxx_port_sync_link,
        .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
@@ -4799,8 +4856,10 @@ static const struct mv88e6xxx_ops mv88e6191_ops = {
        .get_eeprom = mv88e6xxx_g2_get_eeprom8,
        .set_eeprom = mv88e6xxx_g2_set_eeprom8,
        .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
-       .phy_read = mv88e6xxx_g2_smi_phy_read,
-       .phy_write = mv88e6xxx_g2_smi_phy_write,
+       .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
+       .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
+       .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
+       .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
        .port_set_link = mv88e6xxx_port_set_link,
        .port_sync_link = mv88e6xxx_port_sync_link,
        .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
@@ -4862,8 +4921,10 @@ static const struct mv88e6xxx_ops mv88e6240_ops = {
        .get_eeprom = mv88e6xxx_g2_get_eeprom16,
        .set_eeprom = mv88e6xxx_g2_set_eeprom16,
        .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
-       .phy_read = mv88e6xxx_g2_smi_phy_read,
-       .phy_write = mv88e6xxx_g2_smi_phy_write,
+       .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
+       .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
+       .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
+       .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
        .port_set_link = mv88e6xxx_port_set_link,
        .port_sync_link = mv88e6xxx_port_sync_link,
        .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
@@ -4925,8 +4986,10 @@ static const struct mv88e6xxx_ops mv88e6250_ops = {
        .get_eeprom = mv88e6xxx_g2_get_eeprom16,
        .set_eeprom = mv88e6xxx_g2_set_eeprom16,
        .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
-       .phy_read = mv88e6xxx_g2_smi_phy_read,
-       .phy_write = mv88e6xxx_g2_smi_phy_write,
+       .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
+       .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
+       .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
+       .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
        .port_set_link = mv88e6xxx_port_set_link,
        .port_sync_link = mv88e6xxx_port_sync_link,
        .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
@@ -4964,8 +5027,10 @@ static const struct mv88e6xxx_ops mv88e6290_ops = {
        .get_eeprom = mv88e6xxx_g2_get_eeprom8,
        .set_eeprom = mv88e6xxx_g2_set_eeprom8,
        .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
-       .phy_read = mv88e6xxx_g2_smi_phy_read,
-       .phy_write = mv88e6xxx_g2_smi_phy_write,
+       .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
+       .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
+       .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
+       .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
        .port_set_link = mv88e6xxx_port_set_link,
        .port_sync_link = mv88e6xxx_port_sync_link,
        .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
@@ -5029,8 +5094,10 @@ static const struct mv88e6xxx_ops mv88e6320_ops = {
        .get_eeprom = mv88e6xxx_g2_get_eeprom16,
        .set_eeprom = mv88e6xxx_g2_set_eeprom16,
        .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
-       .phy_read = mv88e6xxx_g2_smi_phy_read,
-       .phy_write = mv88e6xxx_g2_smi_phy_write,
+       .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
+       .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
+       .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
+       .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
        .port_set_link = mv88e6xxx_port_set_link,
        .port_sync_link = mv88e6xxx_port_sync_link,
        .port_set_rgmii_delay = mv88e6320_port_set_rgmii_delay,
@@ -5074,8 +5141,10 @@ static const struct mv88e6xxx_ops mv88e6321_ops = {
        .get_eeprom = mv88e6xxx_g2_get_eeprom16,
        .set_eeprom = mv88e6xxx_g2_set_eeprom16,
        .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
-       .phy_read = mv88e6xxx_g2_smi_phy_read,
-       .phy_write = mv88e6xxx_g2_smi_phy_write,
+       .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
+       .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
+       .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
+       .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
        .port_set_link = mv88e6xxx_port_set_link,
        .port_sync_link = mv88e6xxx_port_sync_link,
        .port_set_rgmii_delay = mv88e6320_port_set_rgmii_delay,
@@ -5117,8 +5186,10 @@ static const struct mv88e6xxx_ops mv88e6341_ops = {
        .get_eeprom = mv88e6xxx_g2_get_eeprom8,
        .set_eeprom = mv88e6xxx_g2_set_eeprom8,
        .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
-       .phy_read = mv88e6xxx_g2_smi_phy_read,
-       .phy_write = mv88e6xxx_g2_smi_phy_write,
+       .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
+       .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
+       .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
+       .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
        .port_set_link = mv88e6xxx_port_set_link,
        .port_sync_link = mv88e6xxx_port_sync_link,
        .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
@@ -5183,8 +5254,10 @@ static const struct mv88e6xxx_ops mv88e6350_ops = {
        .ip_pri_map = mv88e6085_g1_ip_pri_map,
        .irl_init_all = mv88e6352_g2_irl_init_all,
        .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
-       .phy_read = mv88e6xxx_g2_smi_phy_read,
-       .phy_write = mv88e6xxx_g2_smi_phy_write,
+       .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
+       .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
+       .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
+       .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
        .port_set_link = mv88e6xxx_port_set_link,
        .port_sync_link = mv88e6xxx_port_sync_link,
        .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
@@ -5227,8 +5300,10 @@ static const struct mv88e6xxx_ops mv88e6351_ops = {
        .ip_pri_map = mv88e6085_g1_ip_pri_map,
        .irl_init_all = mv88e6352_g2_irl_init_all,
        .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
-       .phy_read = mv88e6xxx_g2_smi_phy_read,
-       .phy_write = mv88e6xxx_g2_smi_phy_write,
+       .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
+       .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
+       .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
+       .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
        .port_set_link = mv88e6xxx_port_set_link,
        .port_sync_link = mv88e6xxx_port_sync_link,
        .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
@@ -5275,8 +5350,10 @@ static const struct mv88e6xxx_ops mv88e6352_ops = {
        .get_eeprom = mv88e6xxx_g2_get_eeprom16,
        .set_eeprom = mv88e6xxx_g2_set_eeprom16,
        .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
-       .phy_read = mv88e6xxx_g2_smi_phy_read,
-       .phy_write = mv88e6xxx_g2_smi_phy_write,
+       .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
+       .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
+       .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
+       .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
        .port_set_link = mv88e6xxx_port_set_link,
        .port_sync_link = mv88e6xxx_port_sync_link,
        .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
@@ -5340,8 +5417,10 @@ static const struct mv88e6xxx_ops mv88e6390_ops = {
        .get_eeprom = mv88e6xxx_g2_get_eeprom8,
        .set_eeprom = mv88e6xxx_g2_set_eeprom8,
        .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
-       .phy_read = mv88e6xxx_g2_smi_phy_read,
-       .phy_write = mv88e6xxx_g2_smi_phy_write,
+       .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
+       .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
+       .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
+       .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
        .port_set_link = mv88e6xxx_port_set_link,
        .port_sync_link = mv88e6xxx_port_sync_link,
        .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
@@ -5407,8 +5486,10 @@ static const struct mv88e6xxx_ops mv88e6390x_ops = {
        .get_eeprom = mv88e6xxx_g2_get_eeprom8,
        .set_eeprom = mv88e6xxx_g2_set_eeprom8,
        .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
-       .phy_read = mv88e6xxx_g2_smi_phy_read,
-       .phy_write = mv88e6xxx_g2_smi_phy_write,
+       .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
+       .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
+       .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
+       .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
        .port_set_link = mv88e6xxx_port_set_link,
        .port_sync_link = mv88e6xxx_port_sync_link,
        .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
@@ -5473,8 +5554,10 @@ static const struct mv88e6xxx_ops mv88e6393x_ops = {
        .get_eeprom = mv88e6xxx_g2_get_eeprom8,
        .set_eeprom = mv88e6xxx_g2_set_eeprom8,
        .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
-       .phy_read = mv88e6xxx_g2_smi_phy_read,
-       .phy_write = mv88e6xxx_g2_smi_phy_write,
+       .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
+       .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
+       .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
+       .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
        .port_set_link = mv88e6xxx_port_set_link,
        .port_sync_link = mv88e6xxx_port_sync_link,
        .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
index f635a5bb47ce0c54fa5f30696e8248bccf6c63bc..945a6696ad72bbfb119d37fafb19554155d74f6e 100644 (file)
@@ -454,6 +454,13 @@ struct mv88e6xxx_ops {
                         struct mii_bus *bus,
                         int addr, int reg, u16 val);
 
+       int (*phy_read_c45)(struct mv88e6xxx_chip *chip,
+                           struct mii_bus *bus,
+                           int addr, int devad, int reg, u16 *val);
+       int (*phy_write_c45)(struct mv88e6xxx_chip *chip,
+                            struct mii_bus *bus,
+                            int addr, int devad, int reg, u16 val);
+
        /* Priority Override Table operations */
        int (*pot_clear)(struct mv88e6xxx_chip *chip);
 
index fa65ecd9cb85364cdbec3077303dd90fbe79f35c..ed3b2f88e7835d7b7449d4b1f7c8e6ce80f188cd 100644 (file)
@@ -739,20 +739,18 @@ static int mv88e6xxx_g2_smi_phy_read_data_c45(struct mv88e6xxx_chip *chip,
        return mv88e6xxx_g2_read(chip, MV88E6XXX_G2_SMI_PHY_DATA, data);
 }
 
-static int mv88e6xxx_g2_smi_phy_read_c45(struct mv88e6xxx_chip *chip,
-                                        bool external, int port, int reg,
-                                        u16 *data)
+static int _mv88e6xxx_g2_smi_phy_read_c45(struct mv88e6xxx_chip *chip,
+                                         bool external, int port, int devad,
+                                         int reg, u16 *data)
 {
-       int dev = (reg >> 16) & 0x1f;
-       int addr = reg & 0xffff;
        int err;
 
-       err = mv88e6xxx_g2_smi_phy_write_addr_c45(chip, external, port, dev,
-                                                 addr);
+       err = mv88e6xxx_g2_smi_phy_write_addr_c45(chip, external, port, devad,
+                                                 reg);
        if (err)
                return err;
 
-       return mv88e6xxx_g2_smi_phy_read_data_c45(chip, external, port, dev,
+       return mv88e6xxx_g2_smi_phy_read_data_c45(chip, external, port, devad,
                                                  data);
 }
 
@@ -771,51 +769,65 @@ static int mv88e6xxx_g2_smi_phy_write_data_c45(struct mv88e6xxx_chip *chip,
        return mv88e6xxx_g2_smi_phy_access_c45(chip, external, op, port, dev);
 }
 
-static int mv88e6xxx_g2_smi_phy_write_c45(struct mv88e6xxx_chip *chip,
-                                         bool external, int port, int reg,
-                                         u16 data)
+static int _mv88e6xxx_g2_smi_phy_write_c45(struct mv88e6xxx_chip *chip,
+                                          bool external, int port, int devad,
+                                          int reg, u16 data)
 {
-       int dev = (reg >> 16) & 0x1f;
-       int addr = reg & 0xffff;
        int err;
 
-       err = mv88e6xxx_g2_smi_phy_write_addr_c45(chip, external, port, dev,
-                                                 addr);
+       err = mv88e6xxx_g2_smi_phy_write_addr_c45(chip, external, port, devad,
+                                                 reg);
        if (err)
                return err;
 
-       return mv88e6xxx_g2_smi_phy_write_data_c45(chip, external, port, dev,
+       return mv88e6xxx_g2_smi_phy_write_data_c45(chip, external, port, devad,
                                                   data);
 }
 
-int mv88e6xxx_g2_smi_phy_read(struct mv88e6xxx_chip *chip, struct mii_bus *bus,
-                             int addr, int reg, u16 *val)
+int mv88e6xxx_g2_smi_phy_read_c22(struct mv88e6xxx_chip *chip,
+                                 struct mii_bus *bus,
+                                 int addr, int reg, u16 *val)
 {
        struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv;
        bool external = mdio_bus->external;
 
-       if (reg & MII_ADDR_C45)
-               return mv88e6xxx_g2_smi_phy_read_c45(chip, external, addr, reg,
-                                                    val);
-
        return mv88e6xxx_g2_smi_phy_read_data_c22(chip, external, addr, reg,
                                                  val);
 }
 
-int mv88e6xxx_g2_smi_phy_write(struct mv88e6xxx_chip *chip, struct mii_bus *bus,
-                              int addr, int reg, u16 val)
+int mv88e6xxx_g2_smi_phy_read_c45(struct mv88e6xxx_chip *chip,
+                                 struct mii_bus *bus, int addr, int devad,
+                                 int reg, u16 *val)
 {
        struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv;
        bool external = mdio_bus->external;
 
-       if (reg & MII_ADDR_C45)
-               return mv88e6xxx_g2_smi_phy_write_c45(chip, external, addr, reg,
-                                                     val);
+       return _mv88e6xxx_g2_smi_phy_read_c45(chip, external, addr, devad, reg,
+                                             val);
+}
+
+int mv88e6xxx_g2_smi_phy_write_c22(struct mv88e6xxx_chip *chip,
+                                  struct mii_bus *bus, int addr, int reg,
+                                  u16 val)
+{
+       struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv;
+       bool external = mdio_bus->external;
 
        return mv88e6xxx_g2_smi_phy_write_data_c22(chip, external, addr, reg,
                                                   val);
 }
 
+int mv88e6xxx_g2_smi_phy_write_c45(struct mv88e6xxx_chip *chip,
+                                  struct mii_bus *bus, int addr, int devad,
+                                  int reg, u16 val)
+{
+       struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv;
+       bool external = mdio_bus->external;
+
+       return _mv88e6xxx_g2_smi_phy_write_c45(chip, external, addr, devad, reg,
+                                              val);
+}
+
 /* Offset 0x1B: Watchdog Control */
 static int mv88e6097_watchdog_action(struct mv88e6xxx_chip *chip, int irq)
 {
index 7536b8b0ad011b70395bda7e519af146d20c3319..e973114d689069998c6934787d614d779910db7b 100644 (file)
@@ -314,12 +314,18 @@ int mv88e6xxx_g2_wait_bit(struct mv88e6xxx_chip *chip, int reg,
 int mv88e6352_g2_irl_init_all(struct mv88e6xxx_chip *chip, int port);
 int mv88e6390_g2_irl_init_all(struct mv88e6xxx_chip *chip, int port);
 
-int mv88e6xxx_g2_smi_phy_read(struct mv88e6xxx_chip *chip,
-                             struct mii_bus *bus,
-                             int addr, int reg, u16 *val);
-int mv88e6xxx_g2_smi_phy_write(struct mv88e6xxx_chip *chip,
-                              struct mii_bus *bus,
-                              int addr, int reg, u16 val);
+int mv88e6xxx_g2_smi_phy_read_c22(struct mv88e6xxx_chip *chip,
+                                 struct mii_bus *bus,
+                                 int addr, int reg, u16 *val);
+int mv88e6xxx_g2_smi_phy_write_c22(struct mv88e6xxx_chip *chip,
+                                  struct mii_bus *bus,
+                                  int addr, int reg, u16 val);
+int mv88e6xxx_g2_smi_phy_read_c45(struct mv88e6xxx_chip *chip,
+                                 struct mii_bus *bus,
+                                 int addr, int devad, int reg, u16 *val);
+int mv88e6xxx_g2_smi_phy_write_c45(struct mv88e6xxx_chip *chip,
+                                  struct mii_bus *bus,
+                                  int addr, int devad, int reg, u16 val);
 int mv88e6xxx_g2_set_switch_mac(struct mv88e6xxx_chip *chip, u8 *addr);
 
 int mv88e6xxx_g2_get_eeprom8(struct mv88e6xxx_chip *chip,
index 252b5b3a3efef893271c846af74e272b937fbb73..8bb88b3d900db377d7bf6b34725646f12a5568ec 100644 (file)
@@ -55,6 +55,38 @@ int mv88e6xxx_phy_write(struct mv88e6xxx_chip *chip, int phy, int reg, u16 val)
        return chip->info->ops->phy_write(chip, bus, addr, reg, val);
 }
 
+int mv88e6xxx_phy_read_c45(struct mv88e6xxx_chip *chip, int phy, int devad,
+                          int reg, u16 *val)
+{
+       int addr = phy; /* PHY devices addresses start at 0x0 */
+       struct mii_bus *bus;
+
+       bus = mv88e6xxx_default_mdio_bus(chip);
+       if (!bus)
+               return -EOPNOTSUPP;
+
+       if (!chip->info->ops->phy_read_c45)
+               return -EOPNOTSUPP;
+
+       return chip->info->ops->phy_read_c45(chip, bus, addr, devad, reg, val);
+}
+
+int mv88e6xxx_phy_write_c45(struct mv88e6xxx_chip *chip, int phy, int devad,
+                           int reg, u16 val)
+{
+       int addr = phy; /* PHY devices addresses start at 0x0 */
+       struct mii_bus *bus;
+
+       bus = mv88e6xxx_default_mdio_bus(chip);
+       if (!bus)
+               return -EOPNOTSUPP;
+
+       if (!chip->info->ops->phy_write_c45)
+               return -EOPNOTSUPP;
+
+       return chip->info->ops->phy_write_c45(chip, bus, addr, devad, reg, val);
+}
+
 static int mv88e6xxx_phy_page_get(struct mv88e6xxx_chip *chip, int phy, u8 page)
 {
        return mv88e6xxx_phy_write(chip, phy, MV88E6XXX_PHY_PAGE, page);
index 05ea0d5469698fd6e4c80fab795ff1dc34fd0da9..5f47722364cc02b8271c5dc40094ce2d3b34a176 100644 (file)
@@ -28,6 +28,10 @@ int mv88e6xxx_phy_read(struct mv88e6xxx_chip *chip, int phy,
                       int reg, u16 *val);
 int mv88e6xxx_phy_write(struct mv88e6xxx_chip *chip, int phy,
                        int reg, u16 val);
+int mv88e6xxx_phy_read_c45(struct mv88e6xxx_chip *chip, int phy, int devad,
+                          int reg, u16 *val);
+int mv88e6xxx_phy_write_c45(struct mv88e6xxx_chip *chip, int phy, int devad,
+                           int reg, u16 val);
 int mv88e6xxx_phy_page_read(struct mv88e6xxx_chip *chip, int phy,
                            u8 page, int reg, u16 *val);
 int mv88e6xxx_phy_page_write(struct mv88e6xxx_chip *chip, int phy,
index d94150d8f3f47c40269351d00540fca87a226385..72faec8f44dcaee9abe666fbc3ae23e15671114c 100644 (file)
@@ -36,17 +36,13 @@ static int mv88e6352_serdes_write(struct mv88e6xxx_chip *chip, int reg,
 static int mv88e6390_serdes_read(struct mv88e6xxx_chip *chip,
                                 int lane, int device, int reg, u16 *val)
 {
-       int reg_c45 = MII_ADDR_C45 | device << 16 | reg;
-
-       return mv88e6xxx_phy_read(chip, lane, reg_c45, val);
+       return mv88e6xxx_phy_read_c45(chip, lane, device, reg, val);
 }
 
 static int mv88e6390_serdes_write(struct mv88e6xxx_chip *chip,
                                  int lane, int device, int reg, u16 val)
 {
-       int reg_c45 = MII_ADDR_C45 | device << 16 | reg;
-
-       return mv88e6xxx_phy_write(chip, lane, reg_c45, val);
+       return mv88e6xxx_phy_write_c45(chip, lane, device, reg, val);
 }
 
 static int mv88e6xxx_serdes_pcs_get_state(struct mv88e6xxx_chip *chip,