drm/i915/display: Handle fused off HDCP

HDCP could be fused off, so not all GEN9+ platforms will support it.

Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Martin Peres <martin.peres@linux.intel.com>
Reviewed-by: Ramalingam C <ramalingam.c@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20191026001323.216052-2-jose.souza@intel.com

diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c b/drivers/gpu/drm/i915/display/intel_hdcp.c
index e69fa34528df29fcd9c00fda2a31156f56fa89a3..f1f41ca8402bf79585047d2c269c6bbe40675e4b 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_hdcp.c
+++ b/drivers/gpu/drm/i915/display/intel_hdcp.c
@@ -922,7 +922,7 @@ static void intel_hdcp_prop_work(struct work_struct *work)
 bool is_hdcp_supported(struct drm_i915_private *dev_priv, enum port port)
 {
        /* PORT E doesn't have HDCP, and PORT F is disabled */
-       return INTEL_GEN(dev_priv) >= 9 && port < PORT_E;
+       return INTEL_INFO(dev_priv)->display.has_hdcp && port < PORT_E;
 }
 
 static int

diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 04307e111f57daf13af4ed12ce3cbc09e15f24db..430da2d4082a26b5f3bdcf64d594cda17f60953d 100644 (file)
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -612,6 +612,7 @@ static const struct intel_device_info intel_cherryview_info = {
        .has_logical_ring_preemption = 1, \
        .display.has_csr = 1, \
        .has_gt_uc = 1, \
+       .display.has_hdcp = 1, \
        .display.has_ipc = 1, \
        .ddb_size = 896
 
@@ -655,6 +656,7 @@ static const struct intel_device_info intel_skylake_gt4_info = {
        .display.has_ddi = 1, \
        .has_fpga_dbg = 1, \
        .display.has_fbc = 1, \
+       .display.has_hdcp = 1, \
        .display.has_psr = 1, \
        .has_runtime_pm = 1, \
        .display.has_csr = 1, \

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 2ddeeb2c414d3e7b85cc8c4894762e3b467a1726..d90adf02e0a5431897bd66a2aef5c0d7481928f6 100644 (file)
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7743,6 +7743,7 @@ enum {
 #define   CNL_DDI_CLOCK_REG_ACCESS_ON  (1 << 7)
 
 #define SKL_DFSM                       _MMIO(0x51000)
+#define   SKL_DFSM_DISPLAY_HDCP_DISABLE        (1 << 25)
 #define   SKL_DFSM_CDCLK_LIMIT_MASK    (3 << 23)
 #define   SKL_DFSM_CDCLK_LIMIT_675     (0 << 23)
 #define   SKL_DFSM_CDCLK_LIMIT_540     (1 << 23)

diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
index 85e480bdc6737ffb4138af8631e9e75f75375b54..e7dd6092c1053fe2098ea1c7a225fb1324774c56 100644 (file)
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -981,6 +981,9 @@ void intel_device_info_runtime_init(struct drm_i915_private *dev_priv)
                                  enabled_mask);
                else
                        info->pipe_mask = enabled_mask;
+
+               if (dfsm & SKL_DFSM_DISPLAY_HDCP_DISABLE)
+                       info->display.has_hdcp = 0;
        }
 
        /* Initialize slice/subslice/EU info */

diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
index 78a383f63957fc6a91f05f55ae402fd9e3e38bd0..64e4f1923c6881fc1b491cabfbbd4a94c66cb1d6 100644 (file)
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -139,6 +139,7 @@ enum intel_ppgtt_type {
        func(has_dsb); \
        func(has_fbc); \
        func(has_gmch); \
+       func(has_hdcp); \
        func(has_hotplug); \
        func(has_ipc); \
        func(has_modular_fia); \