arm64: dts: renesas: Add initial SoC DTSI for RZ/V2H(P) SoC

Add initial SoC DTSI for Renesas RZ/V2H(P) ("R9A09G057") SoC, below are
the list of blocks added:
- EXT CLKs
- 4X CA55
- SCIF
- PFC
- CPG
- SYS
- GIC
- ARMv8 Timer

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20240828124134.188864-3-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

diff --git a/arch/arm64/boot/dts/renesas/r9a09g057.dtsi b/arch/arm64/boot/dts/renesas/r9a09g057.dtsi
new file mode 100644 (file)
index 0000000..35b34c4
--- /dev/null
+++ b/arch/arm64/boot/dts/renesas/r9a09g057.dtsi
@@ -0,0 +1,165 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+/*
+ * Device Tree Source for the RZ/V2H(P) SoC
+ *
+ * Copyright (C) 2024 Renesas Electronics Corp.
+ */
+
+#include <dt-bindings/clock/renesas,r9a09g057-cpg.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+/ {
+       compatible = "renesas,r9a09g057";
+       #address-cells = <2>;
+       #size-cells = <2>;
+
+       audio_extal_clk: audio-clk {
+               compatible = "fixed-clock";
+               #clock-cells = <0>;
+               /* This value must be overridden by the board */
+               clock-frequency = <0>;
+       };
+
+       cpus {
+               #address-cells = <1>;
+               #size-cells = <0>;
+
+               cpu0: cpu@0 {
+                       compatible = "arm,cortex-a55";
+                       reg = <0>;
+                       device_type = "cpu";
+                       next-level-cache = <&L3_CA55>;
+                       enable-method = "psci";
+               };
+
+               cpu1: cpu@100 {
+                       compatible = "arm,cortex-a55";
+                       reg = <0x100>;
+                       device_type = "cpu";
+                       next-level-cache = <&L3_CA55>;
+                       enable-method = "psci";
+               };
+
+               cpu2: cpu@200 {
+                       compatible = "arm,cortex-a55";
+                       reg = <0x200>;
+                       device_type = "cpu";
+                       next-level-cache = <&L3_CA55>;
+                       enable-method = "psci";
+               };
+
+               cpu3: cpu@300 {
+                       compatible = "arm,cortex-a55";
+                       reg = <0x300>;
+                       device_type = "cpu";
+                       next-level-cache = <&L3_CA55>;
+                       enable-method = "psci";
+               };
+
+               L3_CA55: cache-controller-0 {
+                       compatible = "cache";
+                       cache-unified;
+                       cache-size = <0x100000>;
+                       cache-level = <3>;
+               };
+       };
+
+       psci {
+               compatible = "arm,psci-1.0", "arm,psci-0.2";
+               method = "smc";
+       };
+
+       qextal_clk: qextal-clk {
+               compatible = "fixed-clock";
+               #clock-cells = <0>;
+               /* This value must be overridden by the board */
+               clock-frequency = <0>;
+       };
+
+       rtxin_clk: rtxin-clk {
+               compatible = "fixed-clock";
+               #clock-cells = <0>;
+               /* This value must be overridden by the board */
+               clock-frequency = <0>;
+       };
+
+       soc: soc {
+               compatible = "simple-bus";
+               interrupt-parent = <&gic>;
+               #address-cells = <2>;
+               #size-cells = <2>;
+               ranges;
+
+               pinctrl: pinctrl@10410000 {
+                       compatible = "renesas,r9a09g057-pinctrl";
+                       reg = <0 0x10410000 0 0x10000>;
+                       clocks = <&cpg CPG_CORE R9A09G057_IOTOP_0_SHCLK>;
+                       gpio-controller;
+                       #gpio-cells = <2>;
+                       gpio-ranges = <&pinctrl 0 0 96>;
+                       #interrupt-cells = <2>;
+                       interrupt-controller;
+                       power-domains = <&cpg>;
+                       resets = <&cpg 0xa5>, <&cpg 0xa6>;
+               };
+
+               cpg: clock-controller@10420000 {
+                       compatible = "renesas,r9a09g057-cpg";
+                       reg = <0 0x10420000 0 0x10000>;
+                       clocks = <&audio_extal_clk>, <&rtxin_clk>, <&qextal_clk>;
+                       clock-names = "audio_extal", "rtxin", "qextal";
+                       #clock-cells = <2>;
+                       #reset-cells = <1>;
+                       #power-domain-cells = <0>;
+               };
+
+               sys: system-controller@10430000 {
+                       compatible = "renesas,r9a09g057-sys";
+                       reg = <0 0x10430000 0 0x10000>;
+                       clocks = <&cpg CPG_CORE R9A09G057_SYS_0_PCLK>;
+                       resets = <&cpg 0x30>;
+                       status = "disabled";
+               };
+
+               scif: serial@11c01400 {
+                       compatible = "renesas,scif-r9a09g057";
+                       reg = <0 0x11c01400 0 0x400>;
+                       interrupts = <GIC_SPI 529 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 532 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 533 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 534 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 531 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 535 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 536 IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 537 IRQ_TYPE_EDGE_RISING>;
+                       interrupt-names = "eri", "rxi", "txi", "bri", "dri",
+                                         "tei", "tei-dri", "rxi-edge", "txi-edge";
+                       clocks = <&cpg CPG_MOD 0x8f>;
+                       clock-names = "fck";
+                       power-domains = <&cpg>;
+                       resets = <&cpg 0x95>;
+                       status = "disabled";
+               };
+
+               gic: interrupt-controller@14900000 {
+                       compatible = "arm,gic-v3";
+                       reg = <0x0 0x14900000 0 0x20000>,
+                             <0x0 0x14940000 0 0x80000>;
+                       #interrupt-cells = <3>;
+                       #address-cells = <0>;
+                       interrupt-controller;
+                       interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
+               };
+       };
+
+       timer {
+               compatible = "arm,armv8-timer";
+               interrupts-extended = <&gic GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
+                                     <&gic GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
+                                     <&gic GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
+                                     <&gic GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>,
+                                     <&gic GIC_PPI 12 IRQ_TYPE_LEVEL_LOW>;
+               interrupt-names = "sec-phys", "phys", "virt", "hyp-phys", "hyp-virt";
+       };
+};