/* Do not reorder/change members after here */
        void    *buf;
        dma_addr_t buf_dma;
-       int     idx;
+       u16     idx;
 };
 
 struct hisi_sas_hw {
 
        if (task->lldd_task && task->task_proto & SAS_PROTOCOL_SSP) {
                struct scsi_cmnd *cmnd = task->uldd_task;
                struct hisi_sas_slot *slot = task->lldd_task;
-               u32 tag = slot->idx;
+               u16 tag = slot->idx;
                int rc2;
 
                int_to_scsilun(cmnd->device->lun, &lun);
                tmf_task.tmf = TMF_ABORT_TASK;
-               tmf_task.tag_of_task_to_be_managed = cpu_to_le16(tag);
+               tmf_task.tag_of_task_to_be_managed = tag;
 
                rc = hisi_sas_debug_issue_ssp_tmf(task->dev, lun.scsi_lun,
                                                  &tmf_task);
 
                int_to_scsilun(cmnd->device->lun, &lun);
                tmf_task.tmf = TMF_QUERY_TASK;
-               tmf_task.tag_of_task_to_be_managed = cpu_to_le16(tag);
+               tmf_task.tag_of_task_to_be_managed = tag;
 
                rc = hisi_sas_debug_issue_ssp_tmf(device,
                                                  lun.scsi_lun,
 
        struct hisi_sas_itct *itct = &hisi_hba->itct[device_id];
        struct asd_sas_port *sas_port = device->port;
        struct hisi_sas_port *port = to_hisi_sas_port(sas_port);
+       u64 sas_addr;
 
        memset(itct, 0, sizeof(*itct));
 
        itct->qw0 = cpu_to_le64(qw0);
 
        /* qw1 */
-       memcpy(&itct->sas_addr, device->sas_addr, SAS_ADDR_SIZE);
-       itct->sas_addr = __swab64(itct->sas_addr);
+       memcpy(&sas_addr, device->sas_addr, SAS_ADDR_SIZE);
+       itct->sas_addr = cpu_to_le64(__swab64(sas_addr));
 
        /* qw2 */
        itct->qw2 = cpu_to_le64((500ULL << ITCT_HDR_IT_NEXUS_LOSS_TL_OFF) |
        reg_val &= ~CFG_AGING_TIME_ITCT_REL_MSK;
        hisi_sas_write32(hisi_hba, CFG_AGING_TIME, reg_val);
 
-       qw0 = cpu_to_le64(itct->qw0);
+       qw0 = le64_to_cpu(itct->qw0);
        qw0 &= ~ITCT_HDR_VALID_MSK;
        itct->qw0 = cpu_to_le64(qw0);
 }
        case SAS_PROTOCOL_SSP:
        {
                int error = -1;
-               u32 dma_err_type = cpu_to_le32(err_record->dma_err_type);
+               u32 dma_err_type = le32_to_cpu(err_record->dma_err_type);
                u32 dma_tx_err_type = ((dma_err_type &
                                        ERR_HDR_DMA_TX_ERR_TYPE_MSK)) >>
                                        ERR_HDR_DMA_TX_ERR_TYPE_OFF;
                                        ERR_HDR_DMA_RX_ERR_TYPE_MSK)) >>
                                        ERR_HDR_DMA_RX_ERR_TYPE_OFF;
                u32 trans_tx_fail_type =
-                               cpu_to_le32(err_record->trans_tx_fail_type);
+                               le32_to_cpu(err_record->trans_tx_fail_type);
                u32 trans_rx_fail_type =
-                               cpu_to_le32(err_record->trans_rx_fail_type);
+                               le32_to_cpu(err_record->trans_rx_fail_type);
 
                if (dma_tx_err_type) {
                        /* dma tx err */
                u32 cmplt_hdr_data;
 
                complete_hdr = &complete_queue[rd_point];
-               cmplt_hdr_data = cpu_to_le32(complete_hdr->data);
+               cmplt_hdr_data = le32_to_cpu(complete_hdr->data);
                idx = (cmplt_hdr_data & CMPLT_HDR_IPTT_MSK) >>
                      CMPLT_HDR_IPTT_OFF;
                slot = &hisi_hba->slot_info[idx];
 
        struct domain_device *parent_dev = device->parent;
        struct asd_sas_port *sas_port = device->port;
        struct hisi_sas_port *port = to_hisi_sas_port(sas_port);
+       u64 sas_addr;
 
        memset(itct, 0, sizeof(*itct));
 
        itct->qw0 = cpu_to_le64(qw0);
 
        /* qw1 */
-       memcpy(&itct->sas_addr, device->sas_addr, SAS_ADDR_SIZE);
-       itct->sas_addr = __swab64(itct->sas_addr);
+       memcpy(&sas_addr, device->sas_addr, SAS_ADDR_SIZE);
+       itct->sas_addr = cpu_to_le64(__swab64(sas_addr));
 
        /* qw2 */
        if (!dev_is_sata(device))
        struct task_status_struct *ts = &task->task_status;
        struct hisi_sas_err_record_v2 *err_record =
                        hisi_sas_status_buf_addr_mem(slot);
-       u32 trans_tx_fail_type = cpu_to_le32(err_record->trans_tx_fail_type);
-       u32 trans_rx_fail_type = cpu_to_le32(err_record->trans_rx_fail_type);
-       u16 dma_tx_err_type = cpu_to_le16(err_record->dma_tx_err_type);
-       u16 sipc_rx_err_type = cpu_to_le16(err_record->sipc_rx_err_type);
-       u32 dma_rx_err_type = cpu_to_le32(err_record->dma_rx_err_type);
+       u32 trans_tx_fail_type = le32_to_cpu(err_record->trans_tx_fail_type);
+       u32 trans_rx_fail_type = le32_to_cpu(err_record->trans_rx_fail_type);
+       u16 dma_tx_err_type = le16_to_cpu(err_record->dma_tx_err_type);
+       u16 sipc_rx_err_type = le16_to_cpu(err_record->sipc_rx_err_type);
+       u32 dma_rx_err_type = le32_to_cpu(err_record->dma_rx_err_type);
        int error = -1;
 
        if (err_phase == 1) {
                                        trans_tx_fail_type);
        } else if (err_phase == 2) {
                /* error in RX phase, the priority is: DW1 > DW3 > DW2 */
-               error = parse_trans_rx_err_code_v2_hw(
-                                       trans_rx_fail_type);
+               error = parse_trans_rx_err_code_v2_hw(trans_rx_fail_type);
                if (error == -1) {
                        error = parse_dma_rx_err_code_v2_hw(
                                        dma_rx_err_type);
                        &complete_queue[slot->cmplt_queue_slot];
        unsigned long flags;
        bool is_internal = slot->is_internal;
+       u32 dw0;
 
        if (unlikely(!task || !task->lldd_task || !task->dev))
                return -EINVAL;
        }
 
        /* Use SAS+TMF status codes */
-       switch ((complete_hdr->dw0 & CMPLT_HDR_ABORT_STAT_MSK)
-                       >> CMPLT_HDR_ABORT_STAT_OFF) {
+       dw0 = le32_to_cpu(complete_hdr->dw0);
+       switch ((dw0 & CMPLT_HDR_ABORT_STAT_MSK) >>
+               CMPLT_HDR_ABORT_STAT_OFF) {
        case STAT_IO_ABORTED:
                /* this io has been aborted by abort command */
                ts->stat = SAS_ABORTED_TASK;
                break;
        }
 
-       if ((complete_hdr->dw0 & CMPLT_HDR_ERX_MSK) &&
-               (!(complete_hdr->dw0 & CMPLT_HDR_RSPNS_XFRD_MSK))) {
-               u32 err_phase = (complete_hdr->dw0 & CMPLT_HDR_ERR_PHASE_MSK)
+       if ((dw0 & CMPLT_HDR_ERX_MSK) && (!(dw0 & CMPLT_HDR_RSPNS_XFRD_MSK))) {
+               u32 err_phase = (dw0 & CMPLT_HDR_ERR_PHASE_MSK)
                                >> CMPLT_HDR_ERR_PHASE_OFF;
                u32 *error_info = hisi_sas_status_buf_addr_mem(slot);
 
        struct hisi_sas_tmf_task *tmf = slot->tmf;
        u8 *buf_cmd;
        int has_data = 0, hdr_tag = 0;
-       u32 dw1 = 0, dw2 = 0;
+       u32 dw0, dw1 = 0, dw2 = 0;
 
        /* create header */
        /* dw0 */
-       hdr->dw0 = cpu_to_le32(port->id << CMD_HDR_PORT_OFF);
+       dw0 = port->id << CMD_HDR_PORT_OFF;
        if (parent_dev && DEV_IS_EXPANDER(parent_dev->dev_type))
-               hdr->dw0 |= cpu_to_le32(3 << CMD_HDR_CMD_OFF);
+               dw0 |= 3 << CMD_HDR_CMD_OFF;
        else
-               hdr->dw0 |= cpu_to_le32(4 << CMD_HDR_CMD_OFF);
+               dw0 |= 4 << CMD_HDR_CMD_OFF;
 
        if (tmf && tmf->force_phy) {
-               hdr->dw0 |= CMD_HDR_FORCE_PHY_MSK;
-               hdr->dw0 |= cpu_to_le32((1 << tmf->phy_id)
-                               << CMD_HDR_PHY_ID_OFF);
+               dw0 |= CMD_HDR_FORCE_PHY_MSK;
+               dw0 |= (1 << tmf->phy_id) << CMD_HDR_PHY_ID_OFF;
        }
 
+       hdr->dw0 = cpu_to_le32(dw0);
+
        /* dw1 */
        switch (task->data_dir) {
        case DMA_TO_DEVICE:
 
                /* Check for NCQ completion */
                if (complete_hdr->act) {
-                       u32 act_tmp = complete_hdr->act;
+                       u32 act_tmp = le32_to_cpu(complete_hdr->act);
                        int ncq_tag_count = ffs(act_tmp);
+                       u32 dw1 = le32_to_cpu(complete_hdr->dw1);
 
-                       dev_id = (complete_hdr->dw1 & CMPLT_HDR_DEV_ID_MSK) >>
+                       dev_id = (dw1 & CMPLT_HDR_DEV_ID_MSK) >>
                                 CMPLT_HDR_DEV_ID_OFF;
                        itct = &hisi_hba->itct[dev_id];
 
                        /* The NCQ tags are held in the itct header */
                        while (ncq_tag_count) {
-                               __le64 *ncq_tag = &itct->qw4_15[0];
+                               __le64 *_ncq_tag = &itct->qw4_15[0], __ncq_tag;
+                               u64 ncq_tag;
 
-                               ncq_tag_count -= 1;
-                               iptt = (ncq_tag[ncq_tag_count / 5]
-                                       >> (ncq_tag_count % 5) * 12) & 0xfff;
+                               ncq_tag_count--;
+                               __ncq_tag = _ncq_tag[ncq_tag_count / 5];
+                               ncq_tag = le64_to_cpu(__ncq_tag);
+                               iptt = (ncq_tag >> (ncq_tag_count % 5) * 12) &
+                                      0xfff;
 
                                slot = &hisi_hba->slot_info[iptt];
                                slot->cmplt_queue_slot = rd_point;
                                ncq_tag_count = ffs(act_tmp);
                        }
                } else {
-                       iptt = (complete_hdr->dw1) & CMPLT_HDR_IPTT_MSK;
+                       u32 dw1 = le32_to_cpu(complete_hdr->dw1);
+
+                       iptt = dw1 & CMPLT_HDR_IPTT_MSK;
                        slot = &hisi_hba->slot_info[iptt];
                        slot->cmplt_queue_slot = rd_point;
                        slot->cmplt_queue = queue;
        dev_dbg(dev, "wait commands complete %dms\n", time);
 }
 
-struct device_attribute *host_attrs_v2_hw[] = {
+static struct device_attribute *host_attrs_v2_hw[] = {
        &dev_attr_phy_event_threshold,
        NULL
 };
 
        struct domain_device *parent_dev = device->parent;
        struct asd_sas_port *sas_port = device->port;
        struct hisi_sas_port *port = to_hisi_sas_port(sas_port);
+       u64 sas_addr;
 
        memset(itct, 0, sizeof(*itct));
 
        itct->qw0 = cpu_to_le64(qw0);
 
        /* qw1 */
-       memcpy(&itct->sas_addr, device->sas_addr, SAS_ADDR_SIZE);
-       itct->sas_addr = __swab64(itct->sas_addr);
+       memcpy(&sas_addr, device->sas_addr, SAS_ADDR_SIZE);
+       itct->sas_addr = cpu_to_le64(__swab64(sas_addr));
 
        /* qw2 */
        if (!dev_is_sata(device))
                        &complete_queue[slot->cmplt_queue_slot];
        struct hisi_sas_err_record_v3 *record =
                        hisi_sas_status_buf_addr_mem(slot);
-       u32 dma_rx_err_type = record->dma_rx_err_type;
-       u32 trans_tx_fail_type = record->trans_tx_fail_type;
+       u32 dma_rx_err_type = le32_to_cpu(record->dma_rx_err_type);
+       u32 trans_tx_fail_type = le32_to_cpu(record->trans_tx_fail_type);
+       u32 dw3 = le32_to_cpu(complete_hdr->dw3);
 
        switch (task->task_proto) {
        case SAS_PROTOCOL_SSP:
                if (dma_rx_err_type & RX_DATA_LEN_UNDERFLOW_MSK) {
                        ts->residual = trans_tx_fail_type;
                        ts->stat = SAS_DATA_UNDERRUN;
-               } else if (complete_hdr->dw3 & CMPLT_HDR_IO_IN_TARGET_MSK) {
+               } else if (dw3 & CMPLT_HDR_IO_IN_TARGET_MSK) {
                        ts->stat = SAS_QUEUE_FULL;
                        slot->abort = 1;
                } else {
                if (dma_rx_err_type & RX_DATA_LEN_UNDERFLOW_MSK) {
                        ts->residual = trans_tx_fail_type;
                        ts->stat = SAS_DATA_UNDERRUN;
-               } else if (complete_hdr->dw3 & CMPLT_HDR_IO_IN_TARGET_MSK) {
+               } else if (dw3 & CMPLT_HDR_IO_IN_TARGET_MSK) {
                        ts->stat = SAS_PHY_DOWN;
                        slot->abort = 1;
                } else {
                        &complete_queue[slot->cmplt_queue_slot];
        unsigned long flags;
        bool is_internal = slot->is_internal;
+       u32 dw0, dw1, dw3;
 
        if (unlikely(!task || !task->lldd_task || !task->dev))
                return -EINVAL;
                goto out;
        }
 
+       dw0 = le32_to_cpu(complete_hdr->dw0);
+       dw1 = le32_to_cpu(complete_hdr->dw1);
+       dw3 = le32_to_cpu(complete_hdr->dw3);
+
        /*
         * Use SAS+TMF status codes
         */
-       switch ((complete_hdr->dw0 & CMPLT_HDR_ABORT_STAT_MSK)
-                       >> CMPLT_HDR_ABORT_STAT_OFF) {
+       switch ((dw0 & CMPLT_HDR_ABORT_STAT_MSK) >> CMPLT_HDR_ABORT_STAT_OFF) {
        case STAT_IO_ABORTED:
                /* this IO has been aborted by abort command */
                ts->stat = SAS_ABORTED_TASK;
        }
 
        /* check for erroneous completion */
-       if ((complete_hdr->dw0 & CMPLT_HDR_CMPLT_MSK) == 0x3) {
+       if ((dw0 & CMPLT_HDR_CMPLT_MSK) == 0x3) {
                u32 *error_info = hisi_sas_status_buf_addr_mem(slot);
 
                slot_err_v3_hw(hisi_hba, task, slot);
                                "CQ hdr: 0x%x 0x%x 0x%x 0x%x "
                                "Error info: 0x%x 0x%x 0x%x 0x%x\n",
                                slot->idx, task, sas_dev->device_id,
-                               complete_hdr->dw0, complete_hdr->dw1,
-                               complete_hdr->act, complete_hdr->dw3,
+                               dw0, dw1, complete_hdr->act, dw3,
                                error_info[0], error_info[1],
                                error_info[2], error_info[3]);
                if (unlikely(slot->abort))
        while (rd_point != wr_point) {
                struct hisi_sas_complete_v3_hdr *complete_hdr;
                struct device *dev = hisi_hba->dev;
+               u32 dw1;
                int iptt;
 
                complete_hdr = &complete_queue[rd_point];
+               dw1 = le32_to_cpu(complete_hdr->dw1);
 
-               iptt = (complete_hdr->dw1) & CMPLT_HDR_IPTT_MSK;
+               iptt = dw1 & CMPLT_HDR_IPTT_MSK;
                if (likely(iptt < HISI_SAS_COMMAND_ENTRIES_V3_HW)) {
                        slot = &hisi_hba->slot_info[iptt];
                        slot->cmplt_queue_slot = rd_point;
 }
 static DEVICE_ATTR_RW(intr_coal_count_v3_hw);
 
-struct device_attribute *host_attrs_v3_hw[] = {
+static struct device_attribute *host_attrs_v3_hw[] = {
        &dev_attr_phy_event_threshold,
        &dev_attr_intr_conv_v3_hw,
        &dev_attr_intr_coal_ticks_v3_hw,
        struct hisi_hba *hisi_hba = sha->lldd_ha;
        struct device *dev = hisi_hba->dev;
        struct Scsi_Host *shost = hisi_hba->shost;
-       u32 device_state;
+       pci_power_t device_state;
        int rc;
 
        if (!pdev->pm_cap) {
        struct Scsi_Host *shost = hisi_hba->shost;
        struct device *dev = hisi_hba->dev;
        unsigned int rc;
-       u32 device_state = pdev->current_state;
+       pci_power_t device_state = pdev->current_state;
 
        dev_warn(dev, "resuming from operating state [D%d]\n",
                        device_state);