arm64: dts: renesas: rzg2ul: Enable Ethernet TXC output

Configure ET0_TXC and ET1_TXC as outputs on the Renesas RZ/G2UL and
RZ/Five SMARC SoMs, as per RGMII specification.

Signed-off-by: Paul Barker <paul.barker.ct@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Link: https://lore.kernel.org/20240625200316.4282-7-paul.barker.ct@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

diff --git a/arch/arm64/boot/dts/renesas/rzg2ul-smarc-som.dtsi b/arch/arm64/boot/dts/renesas/rzg2ul-smarc-som.dtsi
index 97cdad2a12e2ee26243e50fac8c066244c5e6b69..417f49090b1599724c40a981d077d07281a2f931 100644 (file)
--- a/arch/arm64/boot/dts/renesas/rzg2ul-smarc-som.dtsi
+++ b/arch/arm64/boot/dts/renesas/rzg2ul-smarc-som.dtsi
@@ -142,41 +142,53 @@
        };
 
        eth0_pins: eth0 {
-               pinmux = <RZG2L_PORT_PINMUX(4, 5, 1)>, /* ET0_LINKSTA */
-                        <RZG2L_PORT_PINMUX(4, 3, 1)>, /* ET0_MDC */
-                        <RZG2L_PORT_PINMUX(4, 4, 1)>, /* ET0_MDIO */
-                        <RZG2L_PORT_PINMUX(1, 0, 1)>, /* ET0_TXC */
-                        <RZG2L_PORT_PINMUX(1, 1, 1)>, /* ET0_TX_CTL */
-                        <RZG2L_PORT_PINMUX(1, 2, 1)>, /* ET0_TXD0 */
-                        <RZG2L_PORT_PINMUX(1, 3, 1)>, /* ET0_TXD1 */
-                        <RZG2L_PORT_PINMUX(1, 4, 1)>, /* ET0_TXD2 */
-                        <RZG2L_PORT_PINMUX(2, 0, 1)>, /* ET0_TXD3 */
-                        <RZG2L_PORT_PINMUX(3, 0, 1)>, /* ET0_RXC */
-                        <RZG2L_PORT_PINMUX(3, 1, 1)>, /* ET0_RX_CTL */
-                        <RZG2L_PORT_PINMUX(3, 2, 1)>, /* ET0_RXD0 */
-                        <RZG2L_PORT_PINMUX(3, 3, 1)>, /* ET0_RXD1 */
-                        <RZG2L_PORT_PINMUX(4, 0, 1)>, /* ET0_RXD2 */
-                        <RZG2L_PORT_PINMUX(4, 1, 1)>, /* ET0_RXD3 */
-                        <RZG2L_PORT_PINMUX(5, 1, 7)>; /* IRQ2 */
+               txc {
+                       pinmux = <RZG2L_PORT_PINMUX(1, 0, 1)>; /* ET0_TXC */
+                       output-enable;
+               };
+
+               mux {
+                       pinmux = <RZG2L_PORT_PINMUX(4, 5, 1)>, /* ET0_LINKSTA */
+                                <RZG2L_PORT_PINMUX(4, 3, 1)>, /* ET0_MDC */
+                                <RZG2L_PORT_PINMUX(4, 4, 1)>, /* ET0_MDIO */
+                                <RZG2L_PORT_PINMUX(1, 1, 1)>, /* ET0_TX_CTL */
+                                <RZG2L_PORT_PINMUX(1, 2, 1)>, /* ET0_TXD0 */
+                                <RZG2L_PORT_PINMUX(1, 3, 1)>, /* ET0_TXD1 */
+                                <RZG2L_PORT_PINMUX(1, 4, 1)>, /* ET0_TXD2 */
+                                <RZG2L_PORT_PINMUX(2, 0, 1)>, /* ET0_TXD3 */
+                                <RZG2L_PORT_PINMUX(3, 0, 1)>, /* ET0_RXC */
+                                <RZG2L_PORT_PINMUX(3, 1, 1)>, /* ET0_RX_CTL */
+                                <RZG2L_PORT_PINMUX(3, 2, 1)>, /* ET0_RXD0 */
+                                <RZG2L_PORT_PINMUX(3, 3, 1)>, /* ET0_RXD1 */
+                                <RZG2L_PORT_PINMUX(4, 0, 1)>, /* ET0_RXD2 */
+                                <RZG2L_PORT_PINMUX(4, 1, 1)>, /* ET0_RXD3 */
+                                <RZG2L_PORT_PINMUX(5, 1, 7)>; /* IRQ2 */
+               };
        };
 
        eth1_pins: eth1 {
-               pinmux = <RZG2L_PORT_PINMUX(10, 4, 1)>, /* ET1_LINKSTA */
-                        <RZG2L_PORT_PINMUX(10, 2, 1)>, /* ET1_MDC */
-                        <RZG2L_PORT_PINMUX(10, 3, 1)>, /* ET1_MDIO */
-                        <RZG2L_PORT_PINMUX(7, 0, 1)>, /* ET1_TXC */
-                        <RZG2L_PORT_PINMUX(7, 1, 1)>, /* ET1_TX_CTL */
-                        <RZG2L_PORT_PINMUX(7, 2, 1)>, /* ET1_TXD0 */
-                        <RZG2L_PORT_PINMUX(7, 3, 1)>, /* ET1_TXD1 */
-                        <RZG2L_PORT_PINMUX(7, 4, 1)>, /* ET1_TXD2 */
-                        <RZG2L_PORT_PINMUX(8, 0, 1)>, /* ET1_TXD3 */
-                        <RZG2L_PORT_PINMUX(8, 4, 1)>, /* ET1_RXC */
-                        <RZG2L_PORT_PINMUX(9, 0, 1)>, /* ET1_RX_CTL */
-                        <RZG2L_PORT_PINMUX(9, 1, 1)>, /* ET1_RXD0 */
-                        <RZG2L_PORT_PINMUX(9, 2, 1)>, /* ET1_RXD1 */
-                        <RZG2L_PORT_PINMUX(9, 3, 1)>, /* ET1_RXD2 */
-                        <RZG2L_PORT_PINMUX(10, 0, 1)>, /* ET1_RXD3 */
-                        <RZG2L_PORT_PINMUX(18, 5, 1)>; /* IRQ7 */
+               txc {
+                       pinmux = <RZG2L_PORT_PINMUX(7, 0, 1)>; /* ET1_TXC */
+                       output-enable;
+               };
+
+               mux {
+                       pinmux = <RZG2L_PORT_PINMUX(10, 4, 1)>, /* ET1_LINKSTA */
+                                <RZG2L_PORT_PINMUX(10, 2, 1)>, /* ET1_MDC */
+                                <RZG2L_PORT_PINMUX(10, 3, 1)>, /* ET1_MDIO */
+                                <RZG2L_PORT_PINMUX(7, 1, 1)>, /* ET1_TX_CTL */
+                                <RZG2L_PORT_PINMUX(7, 2, 1)>, /* ET1_TXD0 */
+                                <RZG2L_PORT_PINMUX(7, 3, 1)>, /* ET1_TXD1 */
+                                <RZG2L_PORT_PINMUX(7, 4, 1)>, /* ET1_TXD2 */
+                                <RZG2L_PORT_PINMUX(8, 0, 1)>, /* ET1_TXD3 */
+                                <RZG2L_PORT_PINMUX(8, 4, 1)>, /* ET1_RXC */
+                                <RZG2L_PORT_PINMUX(9, 0, 1)>, /* ET1_RX_CTL */
+                                <RZG2L_PORT_PINMUX(9, 1, 1)>, /* ET1_RXD0 */
+                                <RZG2L_PORT_PINMUX(9, 2, 1)>, /* ET1_RXD1 */
+                                <RZG2L_PORT_PINMUX(9, 3, 1)>, /* ET1_RXD2 */
+                                <RZG2L_PORT_PINMUX(10, 0, 1)>, /* ET1_RXD3 */
+                                <RZG2L_PORT_PINMUX(18, 5, 1)>; /* IRQ7 */
+               };
        };
 
        sdhi0_emmc_pins: sd0emmc {